sergiotarxz/nuttx
sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Squashed commit of the following:

Browse Source 
arch/arm/src/tiva/cc13xx:  Trim code now kind of looks like NuttX code.  But does not yet compile.

    arch/arm/src/tiva/cc13xx:  The first few, feeble steps toward getting the overall trim files compatible with the requirements of the NuttX coding standard.

    arch/arm/src/tiva/cc13xx:  Replace last of TI hardware access macros with NuttX hardware access macros.

    arch/arm/src/tiva/cc13xx: Change TI HWREGB to NuttX getreg8 or putreg8 in trim logic.

    arch/arm/src/tiva/cc13xx: Change TI HWREGBITW to NuttX getreg32/putreg32 sequence in trim logic.

    arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h:  Completes the DDIO OSC header file.

    cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h:  Updated, but still not finished.

    arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ddi0_osc.h:  Add DDI0 OSC header file.  Still a work in progress. Does not yet conform to the NuttX coding standard.

    Change _M and _S to _MASK and _SHIFT.

    Some minor improvements.

    Clean up typos in some comments.

    Run all new files against tools/indent.sh

    arch/arm/src/tiva/cc13xx:  Bring in trim files from SDK.  Convert to C-style comments, lowercase hex contants.  Remove Windows-style line endings.
This commit is contained in:
Gregory Nutt 2019-01-12 08:43:45 -06:00
parent 546b6fcbc8
commit 5299e87b2c
5 changed files with 1410 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/src/tiva/Make.defs
View File

@ -103,9 +103,15 @@ endif
else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y) else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y)
CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_chipinfo.c cc13xx_gpio.c CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_chipinfo.c cc13xx_gpio.c
CHIP_CSRCS += cc13xx_gpioirq.c cc13xx_enableclks.c cc13xx_enablepwr.c CHIP_CSRCS += cc13xx_gpioirq.c cc13xx_enableclks.c cc13xx_enablepwr.c
CHIP_CSRCS += cc13x0_trim.c
else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y) else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y)
CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_chipinfo.c cc13xx_gpio.c CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_chipinfo.c cc13xx_gpio.c
CHIP_CSRCS += cc13xx_gpioirq.c cc13xx_enableclks.c cc13xx_enablepwr.c CHIP_CSRCS += cc13xx_gpioirq.c cc13xx_enableclks.c cc13xx_enablepwr.c
ifeq ($(CONFIG_ARCH_CHIP_CC13XX_V1),y)
CHIP_CSRCS += cc13x2_v1_trim.c
else
CHIP_CSRCS += cc13x2_v2_trim.c
endif
endif endif
ifeq ($(CONFIG_DEBUG_GPIO_INFO),y) ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)

405
arch/arm/src/tiva/cc13xx/cc13x0_trim.c Normal file
View File

@ -0,0 +1,405 @@
/****************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's setup.c file (revision 49363) which has a fully
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name NuttX nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
/******************************************************************************
* Included Files
******************************************************************************/
#include <nuttx/config.h>
#include "cc13xx/cc13xx_chipinfo.h"
/******************************************************************************
* Private Functions
******************************************************************************/
/******************************************************************************
* Name: trim_wakeup_frompowerdown
*
* Description:
* Trims to be applied when coming from POWER_DOWN (also called when
* coming from SHUTDOWN and PIN_RESET).
*
* Returned Value:
* None
*
******************************************************************************/
static void trim_wakeup_frompowerdown(void)
{
/* Currently no specific trim for Powerdown */
}
/******************************************************************************
* Name: trim_wakeup_fromshutdown
*
* Description:
* Trims to be applied when coming from SHUTDOWN (also called when
* coming from PIN_RESET).
*
* Input Parameters:
* fcfg1_revision
*
* Returned Value:
* None
*
******************************************************************************/
static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
{
uint32_t ccfg_modeconf;
uint32_t mp1rev;
/* Force AUX on and enable clocks No need to save the current status of the
* power/clock registers. At this point both AUX and AON should have been
* reset to 0x0.
*/
putreg32(AON_WUC_AUXCTL_AUX_FORCE_ON, TIVA_AON_WUC_AUXCTL);
/* Wait for power on on the AUX domain */
while ((getreg32(TIVA_AON_WUC_PWRSTAT) & AON_WUC_PWRSTAT_AUX_PD_ON) == 0)
{
}
/* Enable the clocks for AUX_DDI0_OSC and AUX_ADI4 */
putreg32(AUX_WUC_MODCLKEN0_AUX_DDI0_OSC | AUX_WUC_MODCLKEN0_AUX_ADI4,
TIVA_AON_WUC_MODCLKEN0);
/* Check in CCFG for alternative DCDC setting */
if ((getreg32(TIVA_CCFG_SIZE_AND_DIS_FLAGS) &
CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING) == 0)
{
/* ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
* (=ALT_DCDC_DITHER_EN) ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked
* write since layout is equal for both source and destination
*/
regval = getreg32(TIVA_CCFG_MODE_CONF_1);
regval = (0xf0 | (regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT));
putreg8((uint8_t)regval, TIVA_ADI3_MASK4B + (ADI_3_REFSYS_DCDCCTL5_OFFSET * 2));
}
/* Enable for JTAG to be powered down(will still be powered on if debugger
* is connected)
*/
AONWUCJtagPowerOff();
/* read the MODE_CONF register in CCFG */
ccfg_modeconf = getreg32(TIVA_CCFG_MODE_CONF);
/* First part of trim done after cold reset and wakeup from shutdown:
* -Configure cc13x0 boost mode. -Adjust the VDDR_TRIM_SLEEP value.
* -Configure DCDC.
*/
SetupAfterColdResetWakeupFromShutDownCfg1(ccfg_modeconf);
/* Second part of trim done after cold reset and wakeup from shutdown:
* -Configure XOSC.
*/
#if CCFG_BASE == CCFG_BASE_DEFAULT
SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
ccfg_modeconf);
#else
NOROM_SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
ccfg_modeconf);
#endif
/* Increased margin between digital supply voltage and VDD BOD during
* standby. VTRIM_UDIG: signed 4 bits value to be incremented by 2 (max = 7)
* VTRIM_BOD: unsigned 4 bits value to be decremented by 1 (min = 0) This
* applies to chips with mp1rev < 542 for cc13x0 and for mp1rev < 527 for
* cc26x0
*/
mp1rev =
((getreg32(TIVA_FCFG1_TRIM_CAL_REVISION) &
FCFG1_TRIM_CAL_REVISION_MP1_M) >> FCFG1_TRIM_CAL_REVISION_MP1_SHIFT);
if (mp1rev < 542)
{
uint32_t ldoTrimReg = getreg32(TIVA_FCFG1_BAT_RC_LDO_TRIM);
uint32_t vtrim_bod;
uint32_t vtrim_udig;
/* bit[27:24] unsigned */
vtrim_bod = ((ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_M) >>
FCFG1_BAT_RC_LDO_TRIM_VTRIM_BOD_SHIFT);
/* bit[19:16] signed but treated as unsigned */
vtrim_udig = ((ldoTrimReg & FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_M) >>
FCFG1_BAT_RC_LDO_TRIM_VTRIM_UDIG_SHIFT);
if (vtrim_bod > 0)
{
vtrim_bod -= 1;
}
if (vtrim_udig != 7)
{
if (vtrim_udig == 6)
{
vtrim_udig = 7;
}
else
{
vtrim_udig = ((vtrim_udig + 2) & 0xf);
}
}
regval8 = (vtrim_udig << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_SHIFT) |
(vtrim_bod << ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_SHIFT);
putreg8(regval, TIVA_ADI2_SOCLDOCTL0);
}
/* Third part of trim done after cold reset and wakeup from shutdown:
* -Configure HPOSC. -Setup the LF clock.
*/
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
#else
NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
#endif
/* Allow AUX to power down */
AUXWUCPowerCtrl(AUX_WUC_POWER_DOWN);
/* Leaving on AUX and clock for AUX_DDI0_OSC on but turn off clock for
* AUX_ADI4
*/
putreg32(AUX_WUC_MODCLKEN0_AUX_DDI0_OSC, TIVA_AON_WUC_MODCLKEN0);
/* Disable EFUSE clock */
regval = getreg32(TIVA_FLASH_CFG);
regval |= FLASH_CFG_DIS_EFUSECLK;
putreg32(regval, TIVA_FLASH_CFG)
}
/******************************************************************************
* Name: trim_coldreset
*
* Description:
* Trims to be applied when coming from PIN_RESET.
*
* Returned Value:
* None
*
******************************************************************************/
static void trim_coldreset(void)
{
/* Currently no specific trim for Cold Reset */
}
/******************************************************************************
* Public Functions
******************************************************************************/
/******************************************************************************
* Name: cc13x0_trim_device
*
* Description:
* Perform the necessary trim of the device which is not done in boot code
*
* This function should only execute coming from ROM boot. The current
* implementation does not take soft reset into account. However, it does no
* damage to execute it again. It only consumes time.
*
******************************************************************************/
void cc13x0_trim_device(void)
{
uint32_t fcfg1_revision;
uint32_t aon_sysresetctrl;
/* Get layout revision of the factory configuration area (Handle undefined
* revision as revision = 0)
*/
fcfg1_revision = getreg32(TIVA_FCFG1_FCFG1_REVISION);
if (fcfg1_revision == 0xffffffff)
{
fcfg1_revision = 0;
}
/* This setup file is for CC13x0 PG2.0 and later. Halt if violated */
chipinfo_verify();
/* Enable standby in flash bank */
regval = getreg32(TIVA_FLASH_CFG);
regval &= ~FLASH_CFG_DIS_STANDBY;
putreg32(regval, TIVA_FLASH_CFG)
/* Clock must always be enabled for the semaphore module (due to ADI/DDI HW
* workaround)
*/
putreg32(AUX_WUC_MODCLKEN1_SMPH, TIVA_AON_WUC_MODCLKEN1);
/* Warm resets on CC13x0 and CC26x0 complicates software design because much
* of our software expect that initialization is done from a full system
* reset. This includes RTC setup, oscillator configuration and AUX setup. To
* ensure a full reset of the device is done when customers get e.g. a
* Watchdog reset, the following is set here:
*/
regval = getreg32(TIVA_PRCM_WARMRESET);
regval |= PRCM_WARMRESET_WR_TO_PINRESET;
putreg32(regval, TIVA_PRCM_WARMRESET)
/* Select correct CACHE mode and set correct CACHE configuration */
#if CCFG_BASE == CCFG_BASE_DEFAULT
SetupSetCacheModeAccordingToCcfgSetting();
#else
NOROM_SetupSetCacheModeAccordingToCcfgSetting();
#endif
/* 1. Check for powerdown 2. Check for shutdown 3. Assume cold reset if none
* of the above. It is always assumed that the application will freeze the
* latches in AON_IOC when going to powerdown in order to retain the values
* on the IOs. NB. If this bit is not cleared before proceeding to
* powerdown, the IOs will all default to the reset configuration when
* restarting.
*/
if ((getreg32(TIVA_AON_IOC_IOCLATCH) & AON_IOC_IOCLATCH_EN) == 0)
{
/* NB. This should be calling a ROM implementation of required trim and
* compensation e.g.
* trim_wakeup_frompowerdown()
*/
trim_wakeup_frompowerdown();
}
/* Check for shutdown When device is going to shutdown the hardware will
* automatically clear the SLEEPDIS bit in the SLEEP register in the
* AON_SYSCTL module. It is left for the application to assert this bit when
* waking back up, but not before the desired IO configuration has been
* re-established.
*/
else if ((getreg32(TIVA_AON_SYSCTL_SLEEPCTL) & AON_SYSCTL_SLEEPCTL_IO_PAD_SLEEP_DIS) == 0)
{
/* NB. This should be calling a ROM implementation of required trim and
* compensation e.g. trim_wakeup_fromshutdown() -->
* trim_wakeup_frompowerdown();
*/
trim_wakeup_fromshutdown(fcfg1_revision);
trim_wakeup_frompowerdown();
}
else
{
/* Consider adding a check for soft reset to allow debugging to skip this
* section!!! NB. This should be calling a ROM implementation of
* required trim and compensation e.g. trim_coldreset() -->
* trim_wakeup_fromshutdown() -->
* trim_wakeup_frompowerdown()
*/
trim_coldreset();
trim_wakeup_fromshutdown(fcfg1_revision);
trim_wakeup_frompowerdown();
}
/* Set VIMS power domain control. PDCTL1VIMS = 0 ==> VIMS power domain is
* only powered when CPU power domain is powered
*/
putreg32(0, TIVA_PRCM_PDCTL1VIMS);
/* Configure optimal wait time for flash FSM in cases where flash pump wakes
* up from sleep
*/
regval = getreg32(TIVA_FLASH_FPAC1);
regval &= ~FLASH_FPAC1_PSLEEPTDIS_MASK;
regval |= (0x139 << FLASH_FPAC1_PSLEEPTDIS_SHIFT);
putreg32(regval, TIVA_FLASH_FPAC1);
/* And finally at the end of the flash boot process: SET BOOT_DET bits in
* AON_SYSCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET bits
* must be manually cleared
*/
if (((getreg32(TIVA_AON_SYSCTL_RESETCTL) &
(AON_SYSCTL_RESETCTL_BOOT_DET_1_MASK | AON_SYSCTL_RESETCTL_BOOT_DET_0_MASK))
>> AON_SYSCTL_RESETCTL_BOOT_DET_0_SHIFT) == 1)
{
aon_sysresetctrl = (getreg32(TIVA_AON_SYSCTL_RESETCTL) &
~(AON_SYSCTL_RESETCTL_BOOT_DET_1_CLR_MASK |
AON_SYSCTL_RESETCTL_BOOT_DET_0_CLR_MASK |
AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_MASK |
AON_SYSCTL_RESETCTL_BOOT_DET_0_SET_MASK));
putreg32(aon_sysresetctrl | AON_SYSCTL_RESETCTL_BOOT_DET_1_SET_MASK,
TIVA_AON_SYSCTL_RESETCTL);
putreg32(aon_sysresetctrl, TIVA_AON_SYSCTL_RESETCTL);
}
/* Make sure there are no ongoing VIMS mode change when leaving
* cc13x0_trim_device() (There should typically be no wait time here, but
* need to be sure)
*/
while ((getreg32(TIVA_VIMS_STAT) & VIMS_STAT_MODE_CHANGING) != 0)
{
/* Do nothing - wait for an eventual ongoing mode change to complete. */
}
}

613
arch/arm/src/tiva/cc13xx/cc13x2_v1_trim.c Normal file
View File

@ -0,0 +1,613 @@
/******************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's setup.c file (revision 49363) which has a fully
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name NuttX nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
/******************************************************************************
* Included Files
******************************************************************************/
#include <nuttx/config.h>
#include "chipinfo.h"
/******************************************************************************
* Pre-processor Definitions
******************************************************************************/
/* Handle support for DriverLib in ROM:
* This section will undo prototype renaming made in the header file
*/
#undef cc13x2_cc26x2_trim_device
#define cc13x2_cc26x2_trim_device NOROM_cc13x2_cc26x2_trim_device
/******************************************************************************
* Private Functions
******************************************************************************/
/******************************************************************************
* Name: trim_wakeup_frompowerdown
*
* Description:
* Trims to be applied when coming from POWER_DOWN (also called when
* coming from SHUTDOWN and PIN_RESET).
*
* Returned Value:
* None
*
******************************************************************************/
static void trim_wakeup_frompowerdown(void)
{
/* Currently no specific trim for Powerdown */
}
/******************************************************************************
* Name: Step_RCOSCHF_CTRIM
*
* Description:
* Special shadow register trim propagation on first batch of devices.
*
* Returned Value:
* None
*
******************************************************************************/
static void Step_RCOSCHF_CTRIM(uint32_t toCode)
{
uint32_t current_rcoschfctrl;
uint32_t current_trim;
current_rcoschfctrl = getreg16(TIVA_AUX_DDI0_OSCRCOSCHFCTL);
current_trim =
(((current_rcoschfctrl & DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_MASK) >>
DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_SHIFT) ^ 0xc0);
while (toCode != current_trim)
{
/* Wait for next edge on SCLK_LF (positive or negative) */
(void)getreg32(TIVA_AON_RTC_SYNCLF);
if (toCode > current_trim)
{
current_trim++;
}
else
{
current_trim--;
}
regval16 = (current_rcoschfctrl &
~DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_MASK) |
((current_trim ^ 0xc0) <<
DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_SHIFT);
putreg16(regval16, TIVA_AUX_DDI0_OSCRCOSCHFCTL);
}
}
/******************************************************************************
* Name: Step_VBG
*
* Description:
* Special shadow register trim propagation on first batch of devices.
*
* Returned Value:
* None
*
******************************************************************************/
static void Step_VBG(int32_t target_signed)
{
/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG) */
uint32_t ref_sysctl;
int32_t current_signed;
do
{
ref_sysctl = getreg8(TIVA_ADI3_REFSYS_REFSYSCTL3);
current_signed =
(((int32_t)
(ref_sysctl <<
(32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W -
ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT))) >>
(32 - ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W));
/* Wait for next edge on SCLK_LF (positive or negative) */
HWREG(TIVA_AON_RTC_SYNCLF);
if (target_signed != current_signed)
{
if (target_signed > current_signed)
{
current_signed++;
}
else
{
current_signed--;
}
regval = (ref_sysctl &
~(ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN |
ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK)) |
((((uint32_t)current_signed) <<
ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_SHIFT) &
ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_MASK);
putreg8((uint8_t)regval, TIVA_ADI3_REFSYS_REFSYSCTL3);
regval |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
putreg8((uint8_t)regval, TIVA_ADI3_REFSYS_REFSYSCTL3);
}
}
while (target_signed != current_signed);
}
/******************************************************************************
* Name: trim_wakeup_fromshutdown
*
* Description:
* Trims to be applied when coming from SHUTDOWN (also called when
* coming from PIN_RESET).
*
* Input Parameters:
* fcfg1_revision
*
* Returned Value:
* None
*
******************************************************************************/
static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
{
uint32_t ccfg_modeconf;
/* Check in CCFG for alternative DCDC setting */
if ((getreg32(TIVA_CCFG_SIZE_AND_DIS_FLAGS) &
CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING) == 0)
{
/* ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
* (=ALT_DCDC_DITHER_EN) ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked
* write since layout is equal for both source and destination
*/
regval = getreg32(TIVA_CCFG_MODE_CONF_1);
regval = (0xf0 | (regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT));
putreg8((uint8_t)regval,
TIVA_ADI3_MASK4B + (ADI_3_REFSYS_DCDCCTL5_OFFSET * 2));
}
/* TBD - Temporarily removed for CC13x2 / CC26x2 */
/* Force DCDC to use RCOSC before starting up XOSC. Clock loss detector does
* not use XOSC until SCLK_HF actually switches and thus DCDC is not
* protected from clock loss on XOSC in that time frame. The force must be
* released when the switch to XOSC has happened. This is done in
* OSCHfSourceSwitch().
*/
HWREG(TIVA_AUX_DDI0_OSCMASK16B + (DDI_0_OSC_CTL0_OFFSET << 1) + 4) =
DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK |
(DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK >> 16);
/* Dummy read to ensure that the write has propagated */
(void)getreg16(TIVA_AUX_DDI0_OSCCTL0);
/* read the MODE_CONF register in CCFG */
ccfg_modeconf = getreg32(TIVA_CCFG_MODE_CONF);
/* First part of trim done after cold reset and wakeup from shutdown: -Adjust
* the VDDR_TRIM_SLEEP value. -Configure DCDC.
*/
SetupAfterColdResetWakeupFromShutDownCfg1(ccfg_modeconf);
/* Second part of trim done after cold reset and wakeup from shutdown:
* -Configure XOSC.
*/
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
ccfg_modeconf);
#else
NOROM_SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
ccfg_modeconf);
#endif
/* Special shadow register trim propagation on first batch of devices */
{
uint32_t fusedata;
uint32_t org_resetctl;
/* Get VTRIM_COARSE and VTRIM_DIG from EFUSE shadow register
* OSC_BIAS_LDO_TRIM
*/
fusedata = getreg32(TIVA_FCFG1_SHDW_OSC_BIAS_LDO_TRIM);
Step_RCOSCHF_CTRIM((fusedata &
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_MASK) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_SHIFT);
/* Write to register SOCLDO_0_1 (addr offset 3) bits[7:4] (VTRIM_COARSE)
* and bits[3:0] (VTRIM_DIG) in ADI_2_REFSYS. Direct write can be used
* since all register bit fields are trimmed.
*/
regval8 = ((((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_MASK) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_SHIFT) <<
ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_SHIFT) |
(((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_MASK) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_SHIFT) <<
ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_SHIFT));
putreg8(regval8, TIVA_ADI2_DIR + ADI_2_REFSYS_SOCLDOCTL1_OFFSET);
/* Write to register CTLSOCREFSYS0 (addr offset 0) bits[4:0] (TRIMIREF) in
* ADI_2_REFSYS. Avoid using masked write access since bit field spans
* nibble boundary. Direct write can be used since this is the only defined
* bit field in this register.
*/
regval8 = (((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_MASK) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_SHIFT) <<
ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_SHIFT);
putreg8(regval8, TIVA_ADI2_DIR + ADI_2_REFSYS_REFSYSCTL0_OFFSET);
/* Write to register CTLSOCREFSYS2 (addr offset 4) bits[7:4] (TRIMMAG) in
* ADI_3_REFSYS
*/
regval16 = (ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_MASK << 8) |
(((fusedata & FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_MASK) >>
FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_SHIFT) <<
ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_SHIFT);
putreg16(regval16, TIVA_ADI3_MASK8B + (ADI_3_REFSYS_REFSYSCTL2_OFFSET << 1));
/* Get TRIMBOD_EXTMODE or TRIMBOD_INTMODE from EFUSE shadow register in
* FCFG1
*/
fusedata = getreg32(TIVA_FCFG1_SHDW_ANA_TRIM);
org_resetctl =
(getreg32(TIVA_AON_PMCTL_RESETCTL) &
~AON_PMCTL_RESETCTL_MCU_WARM_RESET_MASK);
HWREG(TIVA_AON_PMCTL_RESETCTL) =
(org_resetctl &
~(AON_PMCTL_RESETCTL_CLK_LOSS_EN | AON_PMCTL_RESETCTL_VDD_LOSS_EN |
AON_PMCTL_RESETCTL_VDDR_LOSS_EN | AON_PMCTL_RESETCTL_VDDS_LOSS_EN));
/* Wait for xxx_LOSS_EN setting to propagate */
HWREG(TIVA_AON_RTC_SYNC);
/* The VDDS_BOD trim and the VDDR trim is already stepped up to max/HH if
* "CC1352 boost mode" is requested. See function
* SetupAfterColdResetWakeupFromShutDownCfg1() in setup_rom.c for details.
*/
if (((ccfg_modeconf & CCFG_MODE_CONF_VDDR_EXT_LOAD) != 0) ||
((ccfg_modeconf & CCFG_MODE_CONF_VDDS_BOD_LEVEL) == 0))
{
if (getreg32(TIVA_AON_PMCTL_PWRCTL) &
AON_PMCTL_PWRCTL_EXT_REG_MODE)
{
/* Apply VDDS BOD trim value Write to register CTLSOCREFSYS1 (addr
* offset 3) bit[7:3] (TRIMBOD) in ADI_3_REFSYS
*/
regval16 = (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) |
(((fusedata & FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_MASK) >>
FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_SHIFT) <<
ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT);
putreg16(regval16,
TIVA_ADI3_MASK8B + (ADI_3_REFSYS_REFSYSCTL1_OFFSET << 1));
}
else
{
/* Apply VDDS BOD trim value Write to register CTLSOCREFSYS1 (addr
* offset 3) bit[7:3] (TRIMBOD) in ADI_3_REFSYS
*/
regval16 = (ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_MASK << 8) |
(((fusedata & FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_MASK) >>
FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_SHIFT) <<
ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_SHIFT);
putreg16(regval16,
TIVA_ADI3_MASK8B + (ADI_3_REFSYS_REFSYSCTL1_OFFSET << 1));
}
/* Load the new VDDS_BOD setting */
regval8 = getreg8(TIVA_ADI3_REFSYS_REFSYSCTL3);
regval8 &= ~ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
putreg8(regval8, TIVA_ADI3_REFSYS_REFSYSCTL3);
regval8 |= ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN;
putreg8(regval8, TIVA_ADI3_REFSYS_REFSYSCTL3);
SetupStepVddrTrimTo((fusedata &
FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_MASK) >>
FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_SHIFT);
}
/* VBG (ANA_TRIM[5:0]=TRIMTEMP --> ADI_3_REFSYS:REFSYSCTL3.TRIM_VBG) */
Step_VBG(((int32_t)
(fusedata <<
(32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W -
FCFG1_SHDW_ANA_TRIM_TRIMTEMP_SHIFT))) >>
(32 - FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W));
/* Wait two more LF edges before restoring xxx_LOSS_EN settings */
/* Wait for next edge on SCLK_LF (positive or negative) */
HWREG(TIVA_AON_RTC_SYNCLF);
/* Wait for next edge on SCLK_LF (positive or negative) */
HWREG(TIVA_AON_RTC_SYNCLF);
HWREG(TIVA_AON_PMCTL_RESETCTL) = org_resetctl;
/* Wait for xxx_LOSS_EN setting to propagate */
HWREG(TIVA_AON_RTC_SYNC);
}
{
uint32_t trimreg;
uint32_t trimvalue;
/*Propagate the LPM_BIAS trim */
trimreg = getreg32(TIVA_FCFG1_DAC_BIAS_CNF);
trimvalue = ((trimreg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_MASK) >>
FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_SHIFT);
regval8 = ((trimvalue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT) &
ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_MASK);
putreg8(regval8, TIVA_AUX_ADI4_LPMBIAS);
/* Set fixed LPM_BIAS values --- LPM_BIAS_BACKUP_EN = 1 and
* LPM_BIAS_WIDTH_TRIM = 3
*/
putreg8(ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
TIVA_ADI3_SET + ADI_3_REFSYS_AUX_DEBUG_OFFSET);
/* Set LPM_BIAS_WIDTH_TRIM = 3
* Set mask (bits to be written) in [15:8]
* Set value (in correct bit pos) in [7:0]
*/
regval16 = ((ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK << 8) |
(3 << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT));
putreg16(regval16, TIVA_AUX_ADI4_MASK8B + (ADI_4_AUX_COMP_OFFSET * 2));
}
/* Third part of trim done after cold reset and wakeup from shutdown:
* -Configure HPOSC. -Setup the LF clock.
*/
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
#else
NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_modeconf);
#endif
/* Set AUX into power down active mode */
AUXSYSIFOpModeChange(AUX_SYSIF_OPMODE_TARGET_PDA);
/* Disable EFUSE clock */
regval = getreg32(TIVA_FLASH_CFG);
regval |= FLASH_CFG_DIS_EFUSECLK;
putreg32(regval, TIVA_FLASH_CFG)
}
/******************************************************************************
* Name: trim_coldreset
*
* Description:
* Trims to be applied when coming from PIN_RESET.
*
* Returned Value:
* None
*
******************************************************************************/
static void trim_coldreset(void)
{
/* Currently no specific trim for Cold Reset */
}
/******************************************************************************
* Public Functions
******************************************************************************/
/******************************************************************************
* Name: cc13x2_cc26x2_trim_device
*
* Descriptions:
* Perform the necessary trim of the device which is not done in boot code
*
* This function should only execute coming from ROM boot. The current
* implementation does not take soft reset into account. However, it does no
* damage to execute it again. It only consumes time.
*
******************************************************************************/
void cc13x2_cc26x2_trim_device(void)
{
uint32_t fcfg1_revision;
uint32_t aon_sysresetctrl;
/* Get layout revision of the factory configuration area (Handle undefined
* revision as revision = 0)
*/
fcfg1_revision = getreg32(TIVA_FCFG1_FCFG1_REVISION);
if (fcfg1_revision == 0xffffffff)
{
fcfg1_revision = 0;
}
/* This setup file is for the CC13x2, CC26x2 chips. Halt if violated */
chipinfo_verify();
/* Enable standby in flash bank */
regval = getreg32(TIVA_FLASH_CFG);
regval &= ~FLASH_CFG_DIS_STANDBY;
putreg32(regval, TIVA_FLASH_CFG)
/* Select correct CACHE mode and set correct CACHE configuration */
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
SetupSetCacheModeAccordingToCcfgSetting();
#else
NOROM_SetupSetCacheModeAccordingToCcfgSetting();
#endif
/* 1. Check for powerdown 2. Check for shutdown 3. Assume cold reset if none
* of the above. It is always assumed that the application will freeze the
* latches in AON_IOC when going to powerdown in order to retain the values
* on the IOs. NB. If this bit is not cleared before proceeding to
* powerdown, the IOs will all default to the reset configuration when
* restarting.
*/
if ((getreg32(TIVA_AON_IOC_IOCLATCH) & AON_IOC_IOCLATCH_EN) == 0)
{
/* NB. This should be calling a ROM implementation of required trim and
* compensation e.g.
* trim_wakeup_frompowerdown()
*/
trim_wakeup_frompowerdown();
}
/* Check for shutdown When device is going to shutdown the hardware will
* automatically clear the SLEEPDIS bit in the SLEEP register in the
* AON_PMCTL module. It is left for the application to assert this bit when
* waking back up, but not before the desired IO configuration has been
* re-established.
*/
else if ((getreg32(TIVA_AON_PMCTL_SLEEPCTL) & AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS)
== 0)
{
/* NB. This should be calling a ROM implementation of required trim and
* compensation e.g. trim_wakeup_fromshutdown() -->
* trim_wakeup_frompowerdown();
*/
trim_wakeup_fromshutdown(fcfg1_revision);
trim_wakeup_frompowerdown();
}
else
{
/* Consider adding a check for soft reset to allow debugging to skip this
* section!!! NB. This should be calling a ROM implementation of
* required trim and compensation e.g. trim_coldreset() -->
* trim_wakeup_fromshutdown() -->
* trim_wakeup_frompowerdown()
*/
trim_coldreset();
trim_wakeup_fromshutdown(fcfg1_revision);
trim_wakeup_frompowerdown();
}
/* Set VIMS power domain control. PDCTL1VIMS = 0 ==> VIMS power domain is
* only powered when CPU power domain is powered
*/
putreg32(0, TIVA_PRCM_PDCTL1VIMS);
/* Configure optimal wait time for flash FSM in cases where flash pump wakes
* up from sleep
*/
regval = getreg32(TIVA_FLASH_FPAC1);
regval &= ~FLASH_FPAC1_PSLEEPTDIS_MASK;
regval |= (0x139 << FLASH_FPAC1_PSLEEPTDIS_SHIFT);
putreg32(regval, TIVA_FLASH_FPAC1);
/* And finally at the end of the flash boot process: SET BOOT_DET bits in
* AON_PMCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET bits
* must be manually cleared
*/
if (((getreg32(TIVA_AON_PMCTL_RESETCTL) &
(AON_PMCTL_RESETCTL_BOOT_DET_1_MASK | AON_PMCTL_RESETCTL_BOOT_DET_0_MASK)) >>
AON_PMCTL_RESETCTL_BOOT_DET_0_SHIFT) == 1)
{
aon_sysresetctrl = (getreg32(TIVA_AON_PMCTL_RESETCTL) &
~(AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_MASK |
AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_MASK |
AON_PMCTL_RESETCTL_BOOT_DET_1_SET_MASK |
AON_PMCTL_RESETCTL_BOOT_DET_0_SET_MASK |
AON_PMCTL_RESETCTL_MCU_WARM_RESET_MASK));
putreg32(aon_sysresetctrl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_MASK,
TIVA_AON_PMCTL_RESETCTL);
putreg32(aon_sysresetctrl, TIVA_AON_PMCTL_RESETCTL);
}
/* Make sure there are no ongoing VIMS mode change when leaving
* cc13x2_cc26x2_trim_device() (There should typically be no wait time here,
* but need to be sure)
*/
while ((getreg32(TIVA_VIMS_STAT) & VIMS_STAT_MODE_CHANGING) != 0)
{
/* Do nothing - wait for an eventual ongoing mode change to complete. */
}
}

385
arch/arm/src/tiva/cc13xx/cc13x2_v2_trim.c Normal file
View File

@ -0,0 +1,385 @@
/******************************************************************************
* arch/arm/src/tiva/cc13xx/cc13x_start.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* This is a port of TI's setup.c file (revision 49363) which has a fully
* compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name NuttX nor the names of its contributors may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
/******************************************************************************
* Included Files
******************************************************************************/
#include <nuttx/config.h>
#include "chipinfo.h"
/******************************************************************************
* Pre-processor Definitions
******************************************************************************/
/* Temporarily adding these defines as they are missing in hw_adi_4_aux.h */
#define ADI_4_AUX_LPMBIAS_OFFSET 0x0000000e
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_MASK 0x0000003f
#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT 0
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT 3
#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK 0x00000038
/******************************************************************************
* Private Functions
******************************************************************************/
/******************************************************************************
* Name: trim_wakeup_frompowerdown
*
* Description:
* Trims to be applied when coming from POWER_DOWN (also called when
* coming from SHUTDOWN and PIN_RESET).
*
* Returned Value:
* None
*
******************************************************************************/
static void trim_wakeup_frompowerdown(void)
{
/* Currently no specific trim for Powerdown */
}
/******************************************************************************
* Name: trim_wakeup_fromshutdown
*
* Description:
* Trims to be applied when coming from SHUTDOWN (also called when
* coming from PIN_RESET).
*
* Input Parameters:
* fcfg1_revision
*
* Returned Value:
* None
*
******************************************************************************/
static void trim_wakeup_fromshutdown(uint32_t fcfg1_revision)
{
uint32_t ccfg_ModeConfReg;
/* Check in CCFG for alternative DCDC setting */
if ((getreg32(TIVA_CCFG_SIZE_AND_DIS_FLAGS) &
CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING) == 0)
{
/* ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19]
* (=ALT_DCDC_DITHER_EN) ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) =
* CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) Using a single 4-bit masked
* write since layout is equal for both source and destination
*/
regval = getreg32(TIVA_CCFG_MODE_CONF_1);
regval = (0xf0 | regval >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_SHIFT);
putreg8((uint8_t)regval,
TIVA_ADI3_MASK4B + (ADI_3_REFSYS_DCDCCTL5_OFFSET * 2));
}
/* TBD - Temporarily removed for CC13x2 / CC26x2 */
/* Force DCDC to use RCOSC before starting up XOSC. Clock loss detector does
* not use XOSC until SCLK_HF actually switches and thus DCDC is not
* protected from clock loss on XOSC in that time frame. The force must be
* released when the switch to XOSC has happened. This is done in
* OSCHfSourceSwitch().
*/
regval = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK |
(DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_MASK >> 16);
putreg32(regval, TIVA_AUX_DDI0_OSCMASK16B + (DDI_0_OSC_CTL0_OFFSET << 1) + 4);
/* Dummy read to ensure that the write has propagated */
(void)getret16(TIVA_AUX_DDI0_OSCCTL0);
/* read the MODE_CONF register in CCFG */
ccfg_ModeConfReg = getreg32(TIVA_CCFG_MODE_CONF);
/* First part of trim done after cold reset and wakeup from shutdown: -Adjust
* the VDDR_TRIM_SLEEP value. -Configure DCDC.
*/
SetupAfterColdResetWakeupFromShutDownCfg1(ccfg_ModeConfReg);
/* Second part of trim done after cold reset and wakeup from shutdown:
* -Configure XOSC.
*/
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
ccfg_ModeConfReg);
#else
NOROM_SetupAfterColdResetWakeupFromShutDownCfg2(fcfg1_revision,
ccfg_ModeConfReg);
#endif
{
uint32_t trimreg;
uint32_t trimvalue;
/* Propagate the LPM_BIAS trim */
trimreg = getreg32(TIVA_FCFG1_DAC_BIAS_CNF);
trimvalue = ((trimreg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_MASK) >>
FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_SHIFT);
regval = ((trimvalue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_SHIFT) &
ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_MASK);
putreg8((uint8_t)regval, TIVA_AUX_ADI4_LPMBIAS);
/* Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration */
if (trimreg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN)
{
putreg8(ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
TIVA_ADI3_SET + ADI_3_REFSYS_AUX_DEBUG_OFFSET);
}
else
{
putreg8(ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN,
TIVA_ADI3_CLR + ADI_3_REFSYS_AUX_DEBUG_OFFSET);
}
/* Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration */
{
uint32_t trimwidth =
((trimreg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_MASK) >>
FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_SHIFT);
/* Set LPM_BIAS_WIDTH_TRIM = 3
* Set mask (bits to be written) in [15:8]
* Set value (in correct bit pos) in [7:0]
*/
regval16 = ((ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_MASK << 8) |
(trimwidth << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_SHIFT));
putreg16(regval16, TIVA_AUX_ADI4_MASK8B + (ADI_4_AUX_COMP_OFFSET * 2));
}
}
/* Third part of trim done after cold reset and wakeup from shutdown:
* -Configure HPOSC. -Setup the LF clock.
*/
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_ModeConfReg);
#else
NOROM_SetupAfterColdResetWakeupFromShutDownCfg3(ccfg_ModeConfReg);
#endif
/* Set AUX into power down active mode */
AUXSYSIFOpModeChange(AUX_SYSIF_OPMODE_TARGET_PDA);
/* Disable EFUSE clock */
regval = getreg32(TIVA_FLASH_CFG);
regval |= FLASH_CFG_DIS_EFUSECLK;
putreg32(regval, TIVA_FLASH_CFG)
}
/******************************************************************************
* Name:
*
* Description:
* Trims to be applied when coming from PIN_RESET.
*
* Returned Value:
* None
*
******************************************************************************/
static void trim_coldreset(void)
{
/* Currently no specific trim for Cold Reset */
}
/****************************************************************************
* Public Functions
****************************************************************************/
/******************************************************************************
* Name:
*
* Description:
* Perform the necessary trim of the device which is not done in boot code
*
* This function should only execute coming from ROM boot. The current
* implementation does not take soft reset into account. However, it does no
* damage to execute it again. It only consumes time.
*
******************************************************************************/
void cc13x2_cc26x2_trim_device(void)
{
uint32_t fcfg1_revision;
uint32_t aon_sysresetctrl;
/* Get layout revision of the factory configuration area (Handle undefined
* revision as revision = 0)
*/
fcfg1_revision = getreg32(TIVA_FCFG1_FCFG1_REVISION);
if (fcfg1_revision == 0xffffffff)
{
fcfg1_revision = 0;
}
/* This setup file is for the CC13x2, CC26x2 PG2.0 or later chips. Halt if
* violated
*/
chipinfo_verify();
/* Enable standby in flash bank */
regval = getreg32(TIVA_FLASH_CFG);
regval &= ~FLASH_CFG_DIS_STANDBY;
putreg32(regval, TIVA_FLASH_CFG)
/* Select correct CACHE mode and set correct CACHE configuration */
#if ( CCFG_BASE == CCFG_BASE_DEFAULT )
SetupSetCacheModeAccordingToCcfgSetting();
#else
NOROM_SetupSetCacheModeAccordingToCcfgSetting();
#endif
/* 1. Check for powerdown 2. Check for shutdown 3. Assume cold reset if none
* of the above. It is always assumed that the application will freeze the
* latches in AON_IOC when going to powerdown in order to retain the values
* on the IOs. NB. If this bit is not cleared before proceeding to
* powerdown, the IOs will all default to the reset configuration when
* restarting.
*/
if ((getreg32(TIVA_AON_IOC_IOCLATCH) & AON_IOC_IOCLATCH_EN) == 0)
{
/* NB. This should be calling a ROM implementation of required trim and
* compensation e.g.
* trim_wakeup_frompowerdown()
*/
trim_wakeup_frompowerdown();
}
/* Check for shutdown When device is going to shutdown the hardware will
* automatically clear the SLEEPDIS bit in the SLEEP register in the
* AON_PMCTL module. It is left for the application to assert this bit when
* waking back up, but not before the desired IO configuration has been
* re-established.
*/
else if ((getreg32(TIVA_AON_PMCTL_SLEEPCTL) & AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS)
== 0)
{
/* NB. This should be calling a ROM implementation of required trim and
* compensation e.g. trim_wakeup_fromshutdown() -->
* trim_wakeup_frompowerdown();
*/
trim_wakeup_fromshutdown(fcfg1_revision);
trim_wakeup_frompowerdown();
}
else
{
/* Consider adding a check for soft reset to allow debugging to skip this
* section!!! NB. This should be calling a ROM implementation of
* required trim and compensation e.g. trim_coldreset() -->
* trim_wakeup_fromshutdown() -->
* trim_wakeup_frompowerdown()
*/
trim_coldreset();
trim_wakeup_fromshutdown(fcfg1_revision);
trim_wakeup_frompowerdown();
}
/* Set VIMS power domain control. PDCTL1VIMS = 0 ==> VIMS power domain is
* only powered when CPU power domain is powered
*/
putreg32(0, TIVA_PRCM_PDCTL1VIMS);
/* Configure optimal wait time for flash FSM in cases where flash pump wakes
* up from sleep
*/
regval = getreg32(TIVA_FLASH_FPAC1);
regval &= ~FLASH_FPAC1_PSLEEPTDIS_MASK;
regval |= (0x139 << FLASH_FPAC1_PSLEEPTDIS_SHIFT);
putreg32(regval, TIVA_FLASH_FPAC1);
/* And finally at the end of the flash boot process: SET BOOT_DET bits in
* AON_PMCTL to 3 if already found to be 1 Note: The BOOT_DET_x_CLR/SET bits
* must be manually cleared
*/
if (((getreg32(TIVA_AON_PMCTL_RESETCTL) &
(AON_PMCTL_RESETCTL_BOOT_DET_1_MASK | AON_PMCTL_RESETCTL_BOOT_DET_0_MASK)) >>
AON_PMCTL_RESETCTL_BOOT_DET_0_SHIFT) == 1)
{
aon_sysresetctrl = (getreg32(TIVA_AON_PMCTL_RESETCTL) &
~(AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_MASK |
AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_MASK |
AON_PMCTL_RESETCTL_BOOT_DET_1_SET_MASK |
AON_PMCTL_RESETCTL_BOOT_DET_0_SET_MASK |
AON_PMCTL_RESETCTL_MCU_WARM_RESET_MASK));
putreg32(aon_sysresetctrl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_MASK,
TIVA_AON_PMCTL_RESETCTL);
putreg32(aon_sysresetctrl, TIVA_AON_PMCTL_RESETCTL);
}
/* Make sure there are no ongoing VIMS mode change when leaving
* cc13x2_cc26x2_trim_device() (There should typically be no wait time here,
* but need to be sure)
*/
while ((getreg32(TIVA_VIMS_STAT0 & VIMS_STAT_MODE_CHANGING) != 0)
{
/* Do nothing - wait for an eventual ongoing mode change to complete. */
}
}

2
drivers/timers/mcp794xx.c
View File

@ -2,7 +2,7 @@
* drivers/timers/mcp794xx.c * drivers/timers/mcp794xx.c
* *
* Copyright (C) 2019 Abdelatif Guettouche. All rights reserved. * Copyright (C) 2019 Abdelatif Guettouche. All rights reserved.
* Author: 2019 Abdelatif Guettouche <abdelatif.guettouche@gmail.com> * Author: Abdelatif Guettouche <abdelatif.guettouche@gmail.com>
* *
* This file is a part of NuttX: * This file is a part of NuttX:
* *