From 529ac8dd9bc68ebe7035f44ca596ee65def170e8 Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Wed, 27 Jun 2018 06:50:00 -0600 Subject: [PATCH] arch/arm/src/lc823450: Fix setintstack macro in chip.h. In case of CONFIG_SMP=y, g_cpu0_instack_base and g_cpu1_instack_base are not allocated just after g_instack_alloc but these values show the addresses for interrupt stack of each CPU. So to set the stack pointer based on these variables, temporal register has to be used. --- arch/arm/src/lc823450/chip.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/lc823450/chip.h b/arch/arm/src/lc823450/chip.h index d981ed55ca..c729dcc95d 100644 --- a/arch/arm/src/lc823450/chip.h +++ b/arch/arm/src/lc823450/chip.h @@ -47,6 +47,7 @@ # include # include "up_arch.h" # include "lc823450_irq.h" +# include "up_arch.h" #endif /**************************************************************************** @@ -105,13 +106,16 @@ and \tmp1, \tmp1, 1 /* \tmp = COREID */ cmp \tmp1, #0 bne 1f - ldr sp, =g_cpu0_instack_base + ldr \tmp1, =g_cpu0_instack_base + ldr sp, [\tmp1, 0] /* sp = getreg32(g_cpu0_instack_base) */ b 2f 1: - ldr sp, =g_cpu1_instack_base + ldr \tmp1, =g_cpu1_instack_base + ldr sp, [\tmp1, 0] /* sp = getreg32(g_cpu1_instack_base) */ 2: #else - ldr sp, =g_cpu0_instack_base + ldr \tmp1, =g_cpu0_instack_base + ldr sp, [\tmp1, 0] /* sp = getreg32(g_cpu0_instack_base) */ #endif .endm #endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */