From 52cfdccd7ab8ec5fd31d15970f0ad51646324373 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 3 Apr 2014 17:12:17 -0600 Subject: [PATCH] SAMA5 boards: Add set up for 528MHz CPU clock --- configs/sama5d3-xplained/Kconfig | 15 ++ configs/sama5d3-xplained/include/board.h | 32 ++- .../sama5d3-xplained/include/board_384mhz.h | 15 +- .../sama5d3-xplained/include/board_396mhz.h | 15 +- .../sama5d3-xplained/include/board_528mhz.h | 207 ++++++++++++++++++ configs/sama5d3x-ek/Kconfig | 15 ++ configs/sama5d3x-ek/include/board.h | 34 ++- configs/sama5d3x-ek/include/board_384mhz.h | 17 +- configs/sama5d3x-ek/include/board_396mhz.h | 17 +- configs/sama5d3x-ek/include/board_528mhz.h | 207 ++++++++++++++++++ 10 files changed, 493 insertions(+), 81 deletions(-) create mode 100644 configs/sama5d3-xplained/include/board_528mhz.h create mode 100644 configs/sama5d3x-ek/include/board_528mhz.h diff --git a/configs/sama5d3-xplained/Kconfig b/configs/sama5d3-xplained/Kconfig index c0c5428088..242eb0c8a5 100644 --- a/configs/sama5d3-xplained/Kconfig +++ b/configs/sama5d3-xplained/Kconfig @@ -5,6 +5,21 @@ if ARCH_BOARD_SAMA5D3_XPLAINED +choice + prompt "CPU Frequency" + default SAMA5D3XPLAINED_396MHZ + +config SAMA5D3XPLAINED_384MHZ + bool "384 MHz" + +config SAMA5D3XPLAINED_396MHZ + bool "396 MHz" + +config SAMA5D3XPLAINED_528MHZ + bool "528 MHz" + +endchoice # CPU Frequency + choice prompt "SAMA5D3-Xplained DRAM Type" default SAMA5D3XPLAINED_MT47H128M16RT diff --git a/configs/sama5d3-xplained/include/board.h b/configs/sama5d3-xplained/include/board.h index c98c629add..29ee7a9624 100644 --- a/configs/sama5d3-xplained/include/board.h +++ b/configs/sama5d3-xplained/include/board.h @@ -43,7 +43,7 @@ #include /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ @@ -63,7 +63,26 @@ # include -#elif 1 /* #elif !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI) */ +#elif defined(CONFIG_SAMA5D3XPLAINED_384MHZ) +/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz + * USB clock with the required accuracy using only PLLA. When PPLA is used to clock + * OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup + * results in a CPU clock of 384MHz. + * + * This case is only interesting for experimentation. + */ + +# include + +#elif defined(CONFIG_SAMA5D3XPLAINED_528MHZ) +/* This is the configuration results in a CPU clock of 528MHz. + * + * In this configuration, UPLL is the source of the UHPHS clock (if enabled). + */ + +# include + +#else /* #elif defined(CONFIG_SAMA5D3XPLAINED_396MHZ) */ /* This is the configuration provided in the Atmel example code. This setup results * in a CPU clock of 396MHz. * @@ -72,15 +91,6 @@ # include -#else -/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz - * USB clock with the required accuracy using only PLLA. When PPLA is used to clock - * OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup - * results in a CPU clock of 384MHz. - */ - -# include - #endif /* LED definitions ******************************************************************/ diff --git a/configs/sama5d3-xplained/include/board_384mhz.h b/configs/sama5d3-xplained/include/board_384mhz.h index 350d661eff..75b4167774 100644 --- a/configs/sama5d3-xplained/include/board_384mhz.h +++ b/configs/sama5d3-xplained/include/board_384mhz.h @@ -43,7 +43,7 @@ #include /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ @@ -190,19 +190,6 @@ #define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT) #define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV -/* FLASH wait states - * - * FWS Max frequency - * 1.62V 1.8V - * --- ----- ------ - * 0 24MHz 27MHz - * 1 40MHz 47MHz - * 2 72MHz 84MHz - * 3 84MHz 96MHz - */ - -#define BOARD_FWS 3 - /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/sama5d3-xplained/include/board_396mhz.h b/configs/sama5d3-xplained/include/board_396mhz.h index 0bac554d7d..a16190a0bd 100644 --- a/configs/sama5d3-xplained/include/board_396mhz.h +++ b/configs/sama5d3-xplained/include/board_396mhz.h @@ -43,7 +43,7 @@ #include /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ @@ -181,19 +181,6 @@ #define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT) #define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV -/* FLASH wait states - * - * FWS Max frequency - * 1.62V 1.8V - * --- ----- ------ - * 0 24MHz 27MHz - * 1 40MHz 47MHz - * 2 72MHz 84MHz - * 3 84MHz 96MHz - */ - -#define BOARD_FWS 3 - /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/sama5d3-xplained/include/board_528mhz.h b/configs/sama5d3-xplained/include/board_528mhz.h new file mode 100644 index 0000000000..ff1b88ca68 --- /dev/null +++ b/configs/sama5d3-xplained/include/board_528mhz.h @@ -0,0 +1,207 @@ +/************************************************************************************ + * configs/sama5d3-xplained/include/board_528mhz.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_528MHZ_H +#define __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_528MHZ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. These + * definitions will configure operational clocking. + * + * This is the configuration results in a CPU clock of 528MHz: + * + * MAINOSC: Frequency = 12MHz (crystal) + * PLLA: PLL Divider = 1, Multiplier = 43+1 to generate PLLACK = 528MHz + * Master Clock (MCK): Source = PLLACK/1, Prescalar = 1, MDIV = 4 to generate + * MCK = 132MHz + * CPU clock = 528MHz + */ + +/* Main oscillator register settings. + * + * The start up time should be should be: + * Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles. + */ + +#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ + +/* PLLA configuration. + * + * Divider = 1 + * Multipler = 43+1 + */ + +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_CKGR_PLLAR_OUT (0) +#define BOARD_CKGR_PLLAR_MUL (43 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS + +/* PMC master clock register settings. + * + * Master/Processor Clock Source Selection = PLLA + * Master/Processor Clock Prescaler = 1 + * PLLA Divider = 1 + * Master Clock Division (MDIV) = 4 + * + * NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3. + * + * Prescaler input = 528MHz / 1 = 528MHz + * Prescaler output = 528MHz / 1 = 528MHz + * Processor Clock (PCK) = 528MHz + * Master clock (MCK) = 528MHz / 4 = 132MHz + */ + +#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA +#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 +#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV1 +#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV4 + +/* ADC Configuration + * + * ADCClock = MCK / ((PRESCAL+1) * 2) + * + * Given: + * MCK = 132MHz + * ADCClock = 8MHz + * Then: + * PRESCAL = 7.25 + * + * PRESCAL=7 and MCK=132MHz yields ADC clock of 8.25MHz + */ + +#define BOARD_ADC_PRESCAL (7) +#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */ +#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */ +#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */ + +/* Resulting frequencies */ + +#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */ +#define BOARD_PLLA_FREQUENCY (528000000) /* PLLACK: 44 * 12Mhz / 1 */ +#define BOARD_PCK_FREQUENCY (528000000) /* CPU: PLLACK / 1 / 1 */ +#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 1 / 1 / 4 */ +#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */ + +#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \ + defined(CONFIG_SAMA5_UDPHS) + +/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded + * High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL + * (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either + * the 12MHz internal RC oscillator on a an external 12MHz crystal. The + * Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier. + * + * For High-speed operations, the user has to perform the following: + * + * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in + * PMC_PCER register. + * 2) Write CKGR_PLLCOUNT field in PMC_UCKR register. + * 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register. + * 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register + * 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register. + * 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB + * register. + * 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in + * PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is + * selected. + * 8) Enable OHCI clocks, UHP bit in PMC_SCER register. + * + * Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI + * driver is initialized. + */ + +# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ +# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ +# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ +#endif + +/* HSMCI clocking + * + * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV) + CLOCKODD + 2). + * + * MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2) + * + * Where CLKDIV has a range of 0-255. + */ + +/* MCK = 132MHz, CLKDIV = 164, MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz */ + +#define HSMCI_INIT_CLKDIV (164 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz */ + +#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD) + +/* MCK = 132MHz, CLKDIV = 2, MCI_SPEED = 132MHz /(2*2 + 0 + 2) = 22 MHz */ + +#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* !__ASSEMBLY__ */ +#endif /* __CONFIGS_SAMA5D3_XPLAINED_INCLUDE_BOARD_528MHZ_H */ diff --git a/configs/sama5d3x-ek/Kconfig b/configs/sama5d3x-ek/Kconfig index 7539ae2c60..1ef0998aa2 100644 --- a/configs/sama5d3x-ek/Kconfig +++ b/configs/sama5d3x-ek/Kconfig @@ -5,6 +5,21 @@ if ARCH_BOARD_SAMA5D3X_EK +choice + prompt "CPU Frequency" + default SAMA5D3xEK_396MHZ + +config SAMA5D3xEK_384MHZ + bool "384 MHz" + +config SAMA5D3xEK_396MHZ + bool "396 MHz" + +config SAMA5D3xEK_528MHZ + bool "528 MHz" + +endchoice # CPU Frequency + choice prompt "SAMA5D3x-EK DRAM Type" default SAMA5D3xEK_MT47H128M16RT diff --git a/configs/sama5d3x-ek/include/board.h b/configs/sama5d3x-ek/include/board.h index ad48e19444..2aad81d95e 100644 --- a/configs/sama5d3x-ek/include/board.h +++ b/configs/sama5d3x-ek/include/board.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d3x-ek/include/board.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,7 +43,7 @@ #include /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ @@ -63,7 +63,26 @@ # include -#elif 1 /* #elif !defined(CONFIG_SAMA5_OHCI) || defined(CONFIG_SAMA5_EHCI) */ +#elif defined(CONFIG_SAMA5D3xEK_384MHZ) +/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz + * USB clock with the required accuracy using only PLLA. When PPLA is used to clock + * OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup + * results in a CPU clock of 384MHz. + * + * This case is only interesting for experimentation. + */ + +# include + +#elif defined(CONFIG_SAMA5D3xEK_528MHZ) +/* This is the configuration results in a CPU clock of 528MHz. + * + * In this configuration, UPLL is the source of the UHPHS clock (if enabled). + */ + +# include + +#else /* #elif defined(CONFIG_SAMA5D3xEK_396MHZ) */ /* This is the configuration provided in the Atmel example code. This setup results * in a CPU clock of 396MHz. * @@ -72,15 +91,6 @@ # include -#else -/* OHCI Only. This is an alternative slower configuration that will produce a 48MHz - * USB clock with the required accuracy using only PLLA. When PPLA is used to clock - * OHCI, an additional requirement is the PLLACK be a multiple of 48MHz. This setup - * results in a CPU clock of 384MHz. - */ - -# include - #endif /* LCD Interface, Geometry and Timing */ diff --git a/configs/sama5d3x-ek/include/board_384mhz.h b/configs/sama5d3x-ek/include/board_384mhz.h index 4c899f24c8..3dee820444 100644 --- a/configs/sama5d3x-ek/include/board_384mhz.h +++ b/configs/sama5d3x-ek/include/board_384mhz.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d3x-ek/include/board_384mhz.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,7 +43,7 @@ #include /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ @@ -190,19 +190,6 @@ #define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT) #define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV -/* FLASH wait states - * - * FWS Max frequency - * 1.62V 1.8V - * --- ----- ------ - * 0 24MHz 27MHz - * 1 40MHz 47MHz - * 2 72MHz 84MHz - * 3 84MHz 96MHz - */ - -#define BOARD_FWS 3 - /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/sama5d3x-ek/include/board_396mhz.h b/configs/sama5d3x-ek/include/board_396mhz.h index 9580e1aaba..707ffd8783 100644 --- a/configs/sama5d3x-ek/include/board_396mhz.h +++ b/configs/sama5d3x-ek/include/board_396mhz.h @@ -1,7 +1,7 @@ /************************************************************************************ * configs/sama5d3x-ek/include/board_396mhz.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -43,7 +43,7 @@ #include /************************************************************************************ - * Definitions + * Pre-processor Definitions ************************************************************************************/ /* Clocking *************************************************************************/ @@ -181,19 +181,6 @@ #define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT) #define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV -/* FLASH wait states - * - * FWS Max frequency - * 1.62V 1.8V - * --- ----- ------ - * 0 24MHz 27MHz - * 1 40MHz 47MHz - * 2 72MHz 84MHz - * 3 84MHz 96MHz - */ - -#define BOARD_FWS 3 - /************************************************************************************ * Public Data ************************************************************************************/ diff --git a/configs/sama5d3x-ek/include/board_528mhz.h b/configs/sama5d3x-ek/include/board_528mhz.h new file mode 100644 index 0000000000..4f79ecd4a6 --- /dev/null +++ b/configs/sama5d3x-ek/include/board_528mhz.h @@ -0,0 +1,207 @@ +/************************************************************************************ + * configs/sama5d3x-ek/include/board_528mhz.h + * + * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_528MHZ_H +#define __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_528MHZ_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC. These + * definitions will configure operational clocking. + * + * This is the configuration results in a CPU clock of 528MHz: + * + * MAINOSC: Frequency = 12MHz (crystal) + * PLLA: PLL Divider = 1, Multiplier = 43+1 to generate PLLACK = 528MHz + * Master Clock (MCK): Source = PLLACK/1, Prescalar = 1, MDIV = 4 to generate + * MCK = 132MHz + * CPU clock = 528MHz + */ + +/* Main oscillator register settings. + * + * The start up time should be should be: + * Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles. + */ + +#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */ + +/* PLLA configuration. + * + * Divider = 1 + * Multipler = 43+1 + */ + +#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT) +#define BOARD_CKGR_PLLAR_OUT (0) +#define BOARD_CKGR_PLLAR_MUL (43 << PMC_CKGR_PLLAR_MUL_SHIFT) +#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS + +/* PMC master clock register settings. + * + * Master/Processor Clock Source Selection = PLLA + * Master/Processor Clock Prescaler = 1 + * PLLA Divider = 1 + * Master Clock Division (MDIV) = 4 + * + * NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3. + * + * Prescaler input = 528MHz / 1 = 528MHz + * Prescaler output = 528MHz / 1 = 528MHz + * Processor Clock (PCK) = 528MHz + * Master clock (MCK) = 528MHz / 4 = 132MHz + */ + +#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA +#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1 +#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV1 +#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV4 + +/* ADC Configuration + * + * ADCClock = MCK / ((PRESCAL+1) * 2) + * + * Given: + * MCK = 132MHz + * ADCClock = 8MHz + * Then: + * PRESCAL = 7.25 + * + * PRESCAL=7 and MCK=132MHz yields ADC clock of 8.25MHz + */ + +#define BOARD_ADC_PRESCAL (7) +#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */ +#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */ +#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */ + +/* Resulting frequencies */ + +#define BOARD_MAINOSC_FREQUENCY (12000000) /* MAINOSC: 12MHz crystal on-board */ +#define BOARD_PLLA_FREQUENCY (528000000) /* PLLACK: 44 * 12Mhz / 1 */ +#define BOARD_PCK_FREQUENCY (528000000) /* CPU: PLLACK / 1 / 1 */ +#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 1 / 1 / 4 */ +#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */ + +#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \ + defined(CONFIG_SAMA5_UDPHS) + +/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded + * High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL + * (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either + * the 12MHz internal RC oscillator on a an external 12MHz crystal. The + * Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier. + * + * For High-speed operations, the user has to perform the following: + * + * 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in + * PMC_PCER register. + * 2) Write CKGR_PLLCOUNT field in PMC_UCKR register. + * 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register. + * 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register + * 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register. + * 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB + * register. + * 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in + * PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is + * selected. + * 8) Enable OHCI clocks, UHP bit in PMC_SCER register. + * + * Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI + * driver is initialized. + */ + +# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */ +# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */ +# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */ +#endif + +/* HSMCI clocking + * + * Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) + * divided by (2*(CLKDIV) + CLOCKODD + 2). + * + * MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2) + * + * Where CLKDIV has a range of 0-255. + */ + +/* MCK = 132MHz, CLKDIV = 164, MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz */ + +#define HSMCI_INIT_CLKDIV (164 << HSMCI_MR_CLKDIV_SHIFT) + +/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz */ + +#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD) + +/* MCK = 132MHz, CLKDIV = 2, MCI_SPEED = 132MHz /(2*2 + 0 + 2) = 22 MHz */ + +#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT) +#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* !__ASSEMBLY__ */ +#endif /* __CONFIGS_SAMA5D3X_EK_INCLUDE_BOARD_528MHZ_H */