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risc-v/toolchain: move zicsr/zifencei extension into Kconfig

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Signed-off-by: chao an <anchao@lixiang.com>
This commit is contained in:
chao an 2024-01-16 08:57:01 +08:00 committed by Xiang Xiao
parent f95bbb2949
commit 52e99bc66b
2 changed files with 21 additions and 3 deletions
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14
arch/risc-v/Kconfig
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@ -288,6 +288,20 @@ config ARCH_RV_ISA_V
default n
depends on ARCH_FPU
config ARCH_RV_ISA_ZICSR_ZIFENCEI
bool
default y
---help---
https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd
GCC-12.1.0 bumped the default ISA spec to the newer 20191213 version,
which moves some instructions from the I extension to the Zicsr and
Zifencei extensions. This requires explicitly specifying Zicsr and
Zifencei when GCC >= 12.1.0. To make life easier, and avoid forcing
toolchains that default to a newer ISA spec to version 2.2. For
clang < 17 or GCC < 11.3.0, for which this is not possible or need
special treatment.
config ARCH_RV_MMIO_BITS
int
# special cases

10
arch/risc-v/src/common/Toolchain.defs
View File

@ -185,9 +185,13 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG)
ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)v
endif
GCC_VERSION = ${shell $(CROSSDEV)gcc --version | grep gcc | grep -oE '[0-9]+\.[0-9]+\.[0-9]+' | tail -n 1 | cut -d"." -f1 }
ifeq ($(shell expr $(GCC_VERSION) \>= 12), 1)
ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)_zicsr_zifencei
ifeq ($(CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI),y)
ifeq ($(GCCVER),)
export GCCVER = ${shell $(CROSSDEV)gcc --version | grep gcc | grep -oE '[0-9]+\.[0-9]+\.[0-9]+' | tail -n 1 | cut -d"." -f1 }
endif
ifeq ($(shell expr $(GCCVER) \>= 12), 1)
ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)_zicsr_zifencei
endif
endif
# Detect abi type