xtensa_context.S: Use Zephyr's version of spilling the window register
file. Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche
Xiang Xiao
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2445de173d
commit
5305f76b1d
@ -106,13 +106,10 @@
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#endif
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#ifndef __XTENSA_CALL0_ABI__
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/* Temporary space for saving stuff during window spill.
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* REVISIT: I don't think that we need so many temporaries.
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*/
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/* Temporary space for saving stuff during window spill. */
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# define REG_TMP0 (_REG_WINDOW_TMPS + 0)
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# define REG_TMP1 (_REG_WINDOW_TMPS + 1)
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# define _REG_OVLY_START (_REG_WINDOW_TMPS + 2)
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# define _REG_OVLY_START (_REG_WINDOW_TMPS + 1)
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#else
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# define _REG_OVLY_START _REG_WINDOW_TMPS
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#endif
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76
arch/xtensa/src/common/xtensa_asm_utils.h
Normal file
76
arch/xtensa/src/common/xtensa_asm_utils.h
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@ -0,0 +1,76 @@
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/****************************************************************************
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* arch/xtensa/src/common/xtensa_asm_utils.h
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*
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* Copyright (c) 2017, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_COMMON_XTENSA_ASM_UTILS_H
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#define __ARCH_XTENSA_SRC_COMMON_XTENSA_ASM_UTILS_H
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/****************************************************************************
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* Assembly Language Macros
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****************************************************************************/
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/****************************************************************************
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*
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* Name: SPILL_ALL_WINDOWS
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*
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* Spills all windowed registers (i.e. registers not visible as
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* A0-A15) to their ABI-defined spill regions on the stack.
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*
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* Unlike the Xtensa HAL implementation, this code requires that the
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* EXCM and WOE bit be enabled in PS, and relies on repeated hardware
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* exception handling to do the register spills. The trick is to do a
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* noop write to the high registers, which the hardware will trap
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* (into an overflow exception) in the case where those registers are
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* already used by an existing call frame. Then it rotates the window
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* and repeats until all but the A0-A3 registers of the original frame
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* are guaranteed to be spilled, eventually rotating back around into
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* the original frame. Advantages:
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*
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* - Vastly smaller code size
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*
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* - More easily maintained if changes are needed to window over/underflow
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* exception handling.
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*
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* - Requires no scratch registers to do its work, so can be used safely in
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* any context.
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*
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* - If the WOE bit is not enabled (for example, in code written for
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* the CALL0 ABI), this becomes a silent noop and operates compatbily.
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*
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* - Hilariously it's ACTUALLY FASTER than the HAL routine. And not
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* just a little bit, it's MUCH faster. With a mostly full register
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* file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill
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* registers with this vs. 279 (!) to do it with
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* xthal_spill_windows().
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****************************************************************************/
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.macro SPILL_ALL_WINDOWS
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#if XCHAL_NUM_AREGS == 64
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 4
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#elif XCHAL_NUM_AREGS == 32
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a4, a4, a4
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rotw 2
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#else
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#error Unrecognized XCHAL_NUM_AREGS
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#endif
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.endm
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#endif /* __ARCH_XTENSA_SRC_COMMON_XTENSA_ASM_UTILS_H */
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@ -68,6 +68,7 @@
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#include "syscall.h"
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#include "xtensa_swi.h"
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#include "xtensa_asm_utils.h"
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/****************************************************************************
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* Public Functions
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@ -160,16 +161,43 @@ _xtensa_context_save:
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#error Overlay support is not implemented
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#endif
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s32i a0, sp, (4 * REG_TMP0) /* Save return address */
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s32i sp, sp, (4 * REG_TMP1) /* Save current stack pointer */
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wsr sp, EXCSAVE_1 /* Preserve register save area */
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/* SPILL_ALL_WINDOWS macro requires window overflow exceptions to be enabled,
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* i.e. PS.EXCM cleared and PS.WOE set.
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* Since we are going to clear PS.EXCM, we also need to increase INTLEVEL
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* at least to XCHAL_EXCM_LEVEL. This matches that value of effective INTLEVEL
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* at entry (CINTLEVEL=max(PS.INTLEVEL, XCHAL_EXCM_LEVEL) when PS.EXCM is set.
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* Since WindowOverflow exceptions will trigger inside SPILL_ALL_WINDOWS,
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* we need to save/restore EPC1 as well.
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* NOTE: Even though a4-a15 are saved into the exception frame, we should not
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* clobber them until after SPILL_ALL_WINDOWS. This is because these registers
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* may contain live windows belonging to previous frames in the call stack.
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* These frames will be spilled by SPILL_ALL_WINDOWS, and if the register was
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* used as a temporary by this code, the temporary value would get stored
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* onto the stack, instead of the real value.
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*/
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l32i sp, sp, (4 * REG_A1) /* Restore the interruptee's SP */
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call0 _xtensa_window_spill /* Preserves only a4-a5, a8-a9, a12-a13 */
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s32i a0, sp, (4 * REG_TMP0) /* Save return address */
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rsr a2, PS /* To be restored after SPILL_ALL_WINDOWS */
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movi a0, PS_INTLEVEL_MASK
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and a3, a2, a0 /* Get the current INTLEVEL */
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bgeui a3, XCHAL_EXCM_LEVEL, 1f /* Calculate max(INTLEVEL, XCHAL_EXCM_LEVEL) */
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movi a3, XCHAL_EXCM_LEVEL
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1:
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movi a0, PS_UM | PS_WOE /* Clear EXCM, enable window overflow, set new INTLEVEL */
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or a3, a3, a0
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wsr a3, ps
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rsync
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rsr a0, EPC1 /* To be restored after SPILL_ALL_WINDOWS */
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addi sp, sp, XCPTCONTEXT_SIZE /* Go back to spill register region */
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SPILL_ALL_WINDOWS /* Place the live register windows there */
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addi sp, sp, -XCPTCONTEXT_SIZE /* Return the current stack pointer and proceed with context save*/
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wsr a2, PS /* Restore PS to the value at entry */
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wsr a0, EPC1 /* Restore EPC1 to the value at entry */
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rsync
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l32i a0, sp, (4 * REG_TMP0) /* Restore return address */
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rsr sp, EXCSAVE_1 /* Save interruptee's a0 */
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l32i a0, sp, (4 * REG_TMP0) /* Save return address */
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l32i sp, sp, (4 * REG_TMP1) /* Save current stack pointer */
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#endif
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ret
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@ -352,7 +352,7 @@ _xtensa_level1_handler:
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l32i a0, a2, (4 * REG_PC) /* Retrieve interruptee's PC */
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wsr a0, EPC_1
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l32i a0, a2, (4 * REG_A0) /* Retrieve interruptee's A0 */
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l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt stack frame */
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l32i sp, a2, (4 * REG_A1) /* Retrieve interrupt stack frame */
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l32i a2, a2, (4 * REG_A2) /* Retrieve interruptee's A2 */
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rsync /* Ensure PS and EPC written */
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