Add SPI register definitions for the Freescale KL25Z
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Gregory Nutt
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arch/arm/src/kl/chip/kl_spi.h
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arch/arm/src/kl/chip/kl_spi.h
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/********************************************************************************************
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* arch/arm/src/kl/kl_spi.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KL_CHIP_KL_SPI_H
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#define __ARCH_ARM_SRC_KL_CHIP_KL_SPI_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* Register Offsets *************************************************************************/
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#define KL_SPI_C1_OFFSET 0x0000 /* SPI control register 1 */
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#define KL_SPI_C2_OFFSET 0x0001 /* SPI control register 2 */
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#define KL_SPI_BR_OFFSET 0x0002 /* SPI baud rate register */
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#define KL_SPI_S_OFFSET 0x0003 /* SPI status register */
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#define KL_SPI_D_OFFSET 0x0005 /* SPI data register */
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#define KL_SPI_M_OFFSET 0x0007 /* SPI match register */
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/* Register Addresses ***********************************************************************/
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#define KL_SPI0_C1 (KL_SPI0_BASE+KL_SPI_C1_OFFSET)
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#define KL_SPI0_C2 (KL_SPI0_BASE+KL_SPI_C2_OFFSET)
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#define KL_SPI0_BR (KL_SPI0_BASE+KL_SPI_BR_OFFSET)
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#define KL_SPI0_S (KL_SPI0_BASE+KL_SPI_S_OFFSET)
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#define KL_SPI0_D (KL_SPI0_BASE+KL_SPI_D_OFFSET)
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#define KL_SPI0_M (KL_SPI0_BASE+KL_SPI_M_OFFSET)
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#define KL_SPI1_C1 (KL_SPI1_BASE+KL_SPI_C1_OFFSET)
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#define KL_SPI1_C2 (KL_SPI1_BASE+KL_SPI_C2_OFFSET)
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#define KL_SPI1_BR (KL_SPI1_BASE+KL_SPI_BR_OFFSET)
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#define KL_SPI1_S (KL_SPI1_BASE+KL_SPI_S_OFFSET)
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#define KL_SPI1_D (KL_SPI1_BASE+KL_SPI_D_OFFSET)
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#define KL_SPI1_M (KL_SPI1_BASE+KL_SPI_M_OFFSET)
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/* Register Bit Definitions *****************************************************************/
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/* SPI control register 1 */
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#define SPI_C1_LSBFE (1 << 0) /* Bit 0: LSB first (shifter direction) */
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#define SPI_C1_SSOE (1 << 1) /* Bit 1: Slave select output enable */
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#define SPI_C1_CPHA (1 << 2) /* Bit 2: Clock phase */
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#define SPI_C1_CPOL (1 << 3) /* Bit 3: Clock polarity */
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#define SPI_C1_MSTR (1 << 4) /* Bit 4: Master/slave mode select */
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#define SPI_C1_SPTIE (1 << 5) /* Bit 5: SPI transmit interrupt enable */
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#define SPI_C1_SPE (1 << 6) /* Bit 6: SPI system enable */
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#define SPI_C1_SPIE (1 << 7) /* Bit 7: SPI interrupt enable: for SPRF and MODF */
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/* SPI control register 2 */
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#define SPI_C2_SPC0 (1 << 0) /* Bit 0: SPI pin control 0 */
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#define SPI_C2_SPISWAI (1 << 1) /* Bit 1: SPI stop in wait mode */
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#define SPI_C2_RXDMAE (1 << 2) /* Bit 2: Receive DMA enable */
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#define SPI_C2_BIDIROE (1 << 3) /* Bit 3: Bidirectional mode output enable */
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#define SPI_C2_MODFEN (1 << 4) /* Bit 4: Master mode-fault function enable */
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#define SPI_C2_TXDMAE (1 << 5) /* Bit 5: Transmit DMA enable */
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#define SPI_C2_SPMIE (1 << 7) /* Bit 7: SPI match interrupt enable */
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/* SPI baud rate register */
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#define SPI_BR_SPR_SHIFT (0) /* Bits 0-3: SPI baud rate divisor */
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#define SPI_BR_SPR_MASK (15 << SPI_BR_SPR_SHIFT)
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# define SPI_BR_SPR_DIV2 (0 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 2 */
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# define SPI_BR_SPR_DIV4 (1 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 4 */
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# define SPI_BR_SPR_DIV8 (2 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 8 */
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# define SPI_BR_SPR_DIV16 (3 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 16 */
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# define SPI_BR_SPR_DIV32 (4 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 32 */
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# define SPI_BR_SPR_DIV64 (5 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 64 */
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# define SPI_BR_SPR_DIV128 (6 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 128 */
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# define SPI_BR_SPR_DIV256 (7 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 256 */
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# define SPI_BR_SPR_DIV512 (8 << SPI_BR_SPR_SHIFT) /* Baud rate divisor is 512 */
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#define SPI_BR_SPPR_SHIFT (4) /* Bits 4-6: SPI baud rate prescale divisor */
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#define SPI_BR_SPPR_MASK (7 << SPI_BR_SPPR_SHIFT)
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# define SPI_BR_SPPR(n) (((n)-1) << SPI_BR_SPPR_SHIFT) /* Prescaler=n, n=1-8 */
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/* Bit 7: Reserved */
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/* SPI status register */
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/* Bits 0-3: Reserved */
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#define SPI_S_MODF (1 << 4) /* Bit 4: Master mode fault flag */
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#define SPI_S_SPTEF (1 << 5) /* Bit 5: SPI transmit buffer empty flag */
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#define SPI_S_SPMF (1 << 6) /* Bit 6: SPI match flag */
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#define SPI_S_SPRF (1 << 7) /* Bit 7: SPI read buffer full flag */
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/* SPI data register (8-bit data, low byte) */
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/* SPI match register (8-bit match value) */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_KL_CHIP_KL_SPI_H */
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