arch/arm/src/samdl: In sam_spibus_initialize(), the pinmux configuration was smashing the previous CTRLA register configuration. There are also some typos in samd_spi.h
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@ -247,8 +247,8 @@
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#endif
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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# define SPI_INT_ SSL (1 << 3) /* Bit 3: Slave select low interrupt */
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# define SPI_INT_ ERROR (1 << 7) /* Bit 7: Error interrupt */
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# define SPI_INT_SSL (1 << 3) /* Bit 3: Slave select low interrupt */
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# define SPI_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
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# define SPI_INT_ALL (0x8f)
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#endif
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/samdl/sam_spi.c
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*
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* Copyright (C) 2014-2017 Gregory Nutt. All rights reserved.
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* Copyright (C) 2014-2018 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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@ -1421,7 +1421,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
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/* Set the SERCOM in SPI master mode (no address) */
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regval = spi_getreg32(priv, SAM_SPI_CTRLA_OFFSET);
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regval &= ~SPI_CTRLA_MODE_MASK;
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regval &= ~(SPI_CTRLA_MODE_MASK | SPI_CTRLA_FORM_MASK);
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regval |= (SPI_CTRLA_MODE_MASTER | SPI_CTRLA_FORM_SPI);
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spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
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@ -1435,11 +1435,13 @@ struct spi_dev_s *sam_spibus_initialize(int port)
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(void)spi_setfrequency((struct spi_dev_s *)priv, 400000);
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/* Set MSB first data order and the configured pad mux setting,
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* Note that SPI mode 0 is assumed initially (CPOL=0 and CPHA=0).
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/* Set MSB first data order and the configured pad mux setting.
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* SPI mode 0 is assumed initially (CPOL=0 and CPHA=0).
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*/
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regval = (SPI_CTRLA_MSBFIRST | priv->muxconfig);
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regval &= ~(SPI_CTRLA_DOPO_MASK | SPI_CTRLA_DIPO_MASK);
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regval &= ~(SPI_CTRLA_CPHA | SPI_CTRLA_CPOL);
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regval |= (SPI_CTRLA_MSBFIRST | priv->muxconfig);
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spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
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/* Enable the receiver. Note that 8-bit data width is assumed initially */
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