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arch/arm/src/samdl: In sam_spibus_initialize(), the pinmux configuration was smashing the previous CTRLA register configuration. There are also some typos in samd_spi.h

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This commit is contained in:
Matt Thompson 2018-01-11 07:34:56 -06:00 committed by Gregory Nutt
parent 0eca2c6fef
commit 537c9a27d1
2 changed files with 9 additions and 7 deletions
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4
arch/arm/src/samdl/chip/samd_spi.h
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@ -247,8 +247,8 @@
#endif #endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21 #ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SPI_INT_ SSL (1 << 3) /* Bit 3: Slave select low interrupt */ # define SPI_INT_SSL (1 << 3) /* Bit 3: Slave select low interrupt */
# define SPI_INT_ ERROR (1 << 7) /* Bit 7: Error interrupt */ # define SPI_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
# define SPI_INT_ALL (0x8f) # define SPI_INT_ALL (0x8f)
#endif #endif

12
arch/arm/src/samdl/sam_spi.c
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@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/samdl/sam_spi.c * arch/arm/src/samdl/sam_spi.c
* *
* Copyright (C) 2014-2017 Gregory Nutt. All rights reserved. * Copyright (C) 2014-2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org> * Authors: Gregory Nutt <gnutt@nuttx.org>
* *
* References: * References:
@ -1421,7 +1421,7 @@ struct spi_dev_s *sam_spibus_initialize(int port)
/* Set the SERCOM in SPI master mode (no address) */ /* Set the SERCOM in SPI master mode (no address) */
regval = spi_getreg32(priv, SAM_SPI_CTRLA_OFFSET); regval = spi_getreg32(priv, SAM_SPI_CTRLA_OFFSET);
regval &= ~SPI_CTRLA_MODE_MASK; regval &= ~(SPI_CTRLA_MODE_MASK | SPI_CTRLA_FORM_MASK);
regval |= (SPI_CTRLA_MODE_MASTER | SPI_CTRLA_FORM_SPI); regval |= (SPI_CTRLA_MODE_MASTER | SPI_CTRLA_FORM_SPI);
spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET); spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
@ -1435,11 +1435,13 @@ struct spi_dev_s *sam_spibus_initialize(int port)
(void)spi_setfrequency((struct spi_dev_s *)priv, 400000); (void)spi_setfrequency((struct spi_dev_s *)priv, 400000);
/* Set MSB first data order and the configured pad mux setting, /* Set MSB first data order and the configured pad mux setting.
* Note that SPI mode 0 is assumed initially (CPOL=0 and CPHA=0). * SPI mode 0 is assumed initially (CPOL=0 and CPHA=0).
*/ */
regval = (SPI_CTRLA_MSBFIRST | priv->muxconfig); regval &= ~(SPI_CTRLA_DOPO_MASK | SPI_CTRLA_DIPO_MASK);
regval &= ~(SPI_CTRLA_CPHA | SPI_CTRLA_CPOL);
regval |= (SPI_CTRLA_MSBFIRST | priv->muxconfig);
spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET); spi_putreg32(priv, regval, SAM_SPI_CTRLA_OFFSET);
/* Enable the receiver. Note that 8-bit data width is assumed initially */ /* Enable the receiver. Note that 8-bit data width is assumed initially */