Xtensa: Add up_cpu_index()
This commit is contained in:
Gregory Nutt
parent
764ef72641
commit
53de345f05
@ -160,7 +160,7 @@ _xtensa_context_save:
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#endif
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#if XTENSA_EXTRA_SA_SIZE > 0 || !defined(CONFIG_XTENSA_CALL0_ABI)
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mov a9, a0 /* Preserve ret addr */
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mov a9, a0 /* Preserve ret addr */
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#endif
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#ifndef CONFIG_XTENSA_CALL0_ABI
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@ -171,7 +171,7 @@ _xtensa_context_save:
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* disabled (assured by PS.EXCM == 1).
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*/
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s32i a12, a2, (4 * REG_TMP0) /* Temp. save stuff in stack frame */
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s32i a12, a2, (4 * REG_TMP0) /* Temp. save stuff in stack frame */
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s32i a13, a2, (4 * REG_TMP1)
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s32i a9, a2, (4 * REG_TMP2)
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@ -181,9 +181,9 @@ _xtensa_context_save:
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*/
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#ifdef CONFIG_XTENSA_USE_OVLY
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l32i a9, a2, (4 * REG_PC) /* Recover saved PC */
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l32i a9, a2, (4 * REG_PC) /* Recover saved PC */
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_xt_overlay_get_state a9, a12, a13
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s32i a9, a2, (4 * REG_OVLY) /* Save overlay state */
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s32i a9, a2, (4 * REG_OVLY) /* Save overlay state */
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#endif
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l32i a12, a2, (4 * REG_A12) /* Recover original a9,12,13 */
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@ -167,12 +167,12 @@
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l32i a6, a3, 4 /* a6 = _xt_vpri_mask */
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neg a2, a2
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addi a2, a2, -1 /* a2 = mask to apply */
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and a5, a6, a2 /* mask off all bits <= a4 bit */
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s32i a5, a3, 4 /* update _xt_vpri_mask */
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and a5, a6, a2 /* Mask off all bits <= a4 bit */
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s32i a5, a3, 4 /* Update _xt_vpri_mask */
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rsr a3, INTENABLE
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and a3, a3, a2 /* mask off all bits <= a4 bit */
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and a3, a3, a2 /* Mask off all bits <= a4 bit */
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wsr a3, INTENABLE
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rsil a3, \level - 1 /* lower interrupt level by 1 */
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rsil a3, \level - 1 /* Lower interrupt level by 1 */
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#endif
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movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */
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@ -226,7 +226,7 @@
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#ifdef CONFIG_XTENSA_USE_SWPRI
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j 8f
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#else
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j .L_xt_user_int_&level& /* check for more interrupts */
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j .L_xt_user_int_&level& /* Check for more interrupts */
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#endif
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#ifdef CONFIG_XTENSA_USE_SWPRI
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@ -237,9 +237,9 @@
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movi a3, _xt_intdata
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l32i a4, a3, 0 /* a4 = _xt_intenable */
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s32i a2, a3, 4 /* update _xt_vpri_mask */
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s32i a2, a3, 4 /* Update _xt_vpri_mask */
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and a4, a4, a2 /* a4 = masked intenable */
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wsr a4, INTENABLE /* update INTENABLE */
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wsr a4, INTENABLE /* Update INTENABLE */
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#endif
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9:
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@ -498,7 +498,7 @@ _xtensa_level5_handler:
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* ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
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*/
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rsr a0, EXCSAVE_5 /* restore a0 */
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rsr a0, EXCSAVE_5 /* Restore a0 */
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rfi 5
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#endif /* XCHAL_INT_NLEVELS >=5 && XCHAL_EXCM_LEVEL < 5 && XCHAL_DEBUGLEVEL !=5 */
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@ -30,6 +30,8 @@
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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****************************************************************************/
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.file "xtensa_irq.S"
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/****************************************************************************
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* Included Files
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****************************************************************************/
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@ -80,7 +80,7 @@ CHIP_CSRCS = esp32_allocateheap.c esp32_intdecode.c esp32_start.c
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# Configuration-dependent ESP32 files
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ifeq ($(CONFIG_SMP),y)
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#CMN_CSRCS += esp32_cpuindex.c esp32_cpustart.c esp32_cpupause.c
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#CMN_CSRCS += esp32_cpuidlestack.c
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CHIP_ASRCS = esp32_cpuindex.S
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#CMN_CSRCS += esp32_cpustart.c esp32_cpupause.c esp32_cpuidlestack.c
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CMN_CSRCS += esp32_cpustart.c
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endif
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76
arch/xtensa/src/esp32/esp32_cpuindex.S
Normal file
76
arch/xtensa/src/esp32/esp32_cpuindex.S
Normal file
@ -0,0 +1,76 @@
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/****************************************************************************
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* arch/xtensa/src/esp32/exp32_cpuindex.S
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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.file "xtensa_cpumacros.S"
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "chip_macros.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_cpu_index
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*
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* Description:
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* Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
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* corresponds to the currently executing CPU.
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*
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* If TLS is enabled, then the RTOS can get this information from the TLS
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* info structure. Otherwise, the MCU-specific logic must provide some
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* mechanism to provide the CPU index.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that
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* corresponds to the currently executing CPU.
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*
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****************************************************************************/
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.text
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.align 4
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.global up_cpu_index
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.type up_cpu_index, @function
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up_cpu_index:
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getcoreid a2
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ret
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.size up_cpu_index, . - up_cpu_index
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