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STM32: Correct some spacing issues

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This commit is contained in:
Gregory Nutt 2015-10-07 13:45:15 -06:00
parent b6638315a4
commit 53f6fd6e66
43 changed files with 1209 additions and 1184 deletions
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93
arch/arm/src/stm32/stm32_adc.c
View File

@ -311,8 +311,8 @@ static struct stm32_dev_s g_adcpriv1 =
static struct adc_dev_s g_adcdev1 =
{
.ad_ops = &g_adcops,
.ad_priv= &g_adcpriv1,
.ad_ops = &g_adcops,
.ad_priv = &g_adcpriv1,
};
#endif
@ -345,8 +345,8 @@ static struct stm32_dev_s g_adcpriv2 =
static struct adc_dev_s g_adcdev2 =
{
.ad_ops = &g_adcops,
.ad_priv= &g_adcpriv2,
.ad_ops = &g_adcops,
.ad_priv = &g_adcpriv2,
};
#endif
@ -379,8 +379,8 @@ static struct stm32_dev_s g_adcpriv3 =
static struct adc_dev_s g_adcdev3 =
{
.ad_ops = &g_adcops,
.ad_priv= &g_adcpriv3,
.ad_ops = &g_adcops,
.ad_priv = &g_adcpriv3,
};
#endif
@ -515,20 +515,20 @@ static void adc_tim_dumpregs(struct stm32_dev_s *priv, FAR const char *msg)
tim_getreg(priv, STM32_GTIM_CCR3_OFFSET),
tim_getreg(priv, STM32_GTIM_CCR4_OFFSET));
# ifndef CONFIG_STM32_STM32L15XX
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
{
avdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
tim_getreg(priv, STM32_ATIM_DMAR_OFFSET));
}
else
{
avdbg(" DCR: %04x DMAR: %04x\n",
tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
}
if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE)
{
avdbg(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
tim_getreg(priv, STM32_ATIM_RCR_OFFSET),
tim_getreg(priv, STM32_ATIM_BDTR_OFFSET),
tim_getreg(priv, STM32_ATIM_DCR_OFFSET),
tim_getreg(priv, STM32_ATIM_DMAR_OFFSET));
}
else
{
avdbg(" DCR: %04x DMAR: %04x\n",
tim_getreg(priv, STM32_GTIM_DCR_OFFSET),
tim_getreg(priv, STM32_GTIM_DMAR_OFFSET));
}
# endif
#endif
}
@ -857,7 +857,7 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
ccmr1 |= ocmode1;
ccmr2 |= ocmode2;
/* Reset the output polarity level of all channels (selects high polarity)*/
/* Reset the output polarity level of all channels (selects high polarity) */
ccer &= ~(ATIM_CCER_CC1P | ATIM_CCER_CC2P | ATIM_CCER_CC3P | ATIM_CCER_CC4P);
@ -1302,15 +1302,15 @@ static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev)
uint8_t i, shift;
/* Sampling time individually for each channel
* 000: 4 cycles
* 001: 9 cycles
* 010: 16 cycles
* 011: 24 cycles
* 100: 48 cycles
* 101: 96 cycles
* 110: 192 cycles
* 111: 384 cycles - selected for all channels
*/
* 000: 4 cycles
* 001: 9 cycles
* 010: 16 cycles
* 011: 24 cycles
* 100: 48 cycles
* 101: 96 cycles
* 110: 192 cycles
* 111: 384 cycles - selected for all channels
*/
for (i = 0, shift = 0; i < 32; i++)
{
@ -1369,7 +1369,7 @@ static void adc_write_sample_time_registers(FAR struct adc_dev_s *dev)
#ifdef ADC_HAVE_DMA
static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
{
FAR struct adc_dev_s *dev = (FAR struct adc_dev_s*) arg;
FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg;
FAR struct stm32_dev_s *priv = dev->ad_priv;
uint32_t regval;
int i;
@ -1562,9 +1562,10 @@ static void adc_reset(FAR struct adc_dev_s *dev)
#if ADC_MAX_SAMPLES == 1
/* Select on first indexed channel for backward compatibility. */
adc_set_ch_idx(dev,0);
adc_set_ch_idx(dev, 0);
#else
adc_set_ch(dev,0);
adc_set_ch(dev, 0);
#endif
/* ADC CCR configuration */
@ -1643,10 +1644,10 @@ static void adc_reset(FAR struct adc_dev_s *dev)
#ifdef ADC_HAVE_TIMER
ret = adc_timinit(priv);
if (ret!=OK)
{
if (ret != OK)
{
adbg("Error initializing the timers\n");
}
}
#elif !defined(CONFIG_ADC_NO_STARTUP_CONV)
#ifdef CONFIG_STM32_STM32F10XX
@ -2280,9 +2281,9 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
regval = adc_getreg(priv, STM32_ADC_SQR1_OFFSET) & ADC_SQR1_RESERVED;
for (i = 24, offset = 0; i < priv->nchannels && i < 28; i++, offset += 5)
{
regval |= (uint32_t)priv->chanlist[i] << offset;
}
{
regval |= (uint32_t)priv->chanlist[i] << offset;
}
#else
priv->nchannels = priv->cchannels;
@ -2316,7 +2317,7 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
{
if ((uint32_t)priv->chanlist[i] == ch)
{
ret = adc_set_ch_idx(dev,i);
ret = adc_set_ch_idx(dev, i);
if (ret < 0)
{
break;
@ -2335,7 +2336,7 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch)
ret = -ENODEV;
}
return ret;
return ret;
}
/****************************************************************************
@ -2382,7 +2383,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
case IO_ENABLE_DISABLE_JEOCIE:
case IO_ENABLE_DISABLE_OVRIE:
case IO_ENABLE_DISABLE_ALL_INTS:
adc_ioc_change_ints(dev, cmd, *(bool*)arg);
adc_ioc_change_ints(dev, cmd, *(bool *)arg);
break;
case IO_START_CONV:
@ -2396,7 +2397,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
return ret;
}
ret = adc_set_ch(dev,ch);
ret = adc_set_ch(dev, ch);
if (ret < 0)
{
set_errno(-ret);
@ -2828,9 +2829,9 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist,
}
else
#endif
{
DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_NODMA);
}
{
DEBUGASSERT(priv->nchannels <= ADC_MAX_CHANNELS_NODMA);
}
priv->cchannels = cchannels;

2
arch/arm/src/stm32/stm32_aes.c
View File

@ -157,7 +157,7 @@ static void aes_encryptblock(void *block_out, const void *block_in)
in++;
putreg32(*in, STM32_AES_DINR);
while(!(getreg32(STM32_AES_SR) & AES_SR_CCF))
while (!(getreg32(STM32_AES_SR) & AES_SR_CCF))
;
aes_ccfc();

16
arch/arm/src/stm32/stm32_allocateheap.c
View File

@ -512,12 +512,12 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)ubase;
*heap_start = (FAR void *)ubase;
*heap_size = usize;
/* Colorize the heap for debug */
up_heap_color((FAR void*)ubase, usize);
up_heap_color((FAR void *)ubase, usize);
/* Allow user-mode access to the user heap memory */
@ -527,7 +527,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;
/* Colorize the heap for debug */
@ -575,7 +575,7 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
* that was not dedicated to the user heap).
*/
*heap_start = (FAR void*)USERSPACE->us_bssend;
*heap_start = (FAR void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
@ -603,11 +603,11 @@ void up_addregion(void)
/* Colorize the heap for debug */
up_heap_color((FAR void*)SRAM2_START, SRAM2_END-SRAM2_START);
up_heap_color((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
/* Add the STM32F20xxx/STM32F40xxx CCM SRAM user heap region. */
kumm_addregion((FAR void*)SRAM2_START, SRAM2_END-SRAM2_START);
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
#endif
#ifdef CONFIG_STM32_FSMC_SRAM
@ -621,11 +621,11 @@ void up_addregion(void)
/* Colorize the heap for debug */
up_heap_color((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
/* Add the external FSMC SRAM user heap region. */
kumm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
}
#endif

76
arch/arm/src/stm32/stm32_bbsram.c
View File

@ -101,7 +101,7 @@ struct bbsramfh_s
* starting at fileno */
uint8_t fileno; /* The minor number */
uint8_t dirty; /* Data has been written to the file */
uint16_t len; /* Total Bytes in this file*/
uint16_t len; /* Total Bytes in this file */
struct timespec lastwrite; /* Last write time */
uint8_t data[]; /* Data in the file */
};
@ -119,13 +119,17 @@ struct stm32_bbsram_s
static int stm32_bbsram_open(FAR struct file *filep);
static int stm32_bbsram_close(FAR struct file *filep);
static off_t stm32_bbsram_seek(FAR struct file *filep, off_t offset, int whence);
static ssize_t stm32_bbsram_read(FAR struct file *, FAR char *, size_t);
static ssize_t stm32_bbsram_write(FAR struct file *, FAR const char *, size_t);
static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
static off_t stm32_bbsram_seek(FAR struct file *filep, off_t offset,
int whence);
static ssize_t stm32_bbsram_read(FAR struct file *filep, FAR char *buffer,
size_t len);
static ssize_t stm32_bbsram_write(FAR struct file *filep,
FAR const char *buffer, size_t len);
static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
unsigned long arg);
#ifndef CONFIG_DISABLE_POLL
static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
bool setup);
bool setup);
#endif
#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS
static int stm32_bbsram_unlink(FAR struct inode *inode);
@ -167,7 +171,7 @@ static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES];
#if defined(CONFIG_BBSRAM_DEBUG)
static void stm32_bbsram_rd(void)
{
memcpy(&debug,(uint8_t*)STM32_BKPSRAM_BASE,sizeof debug);
memcpy(&debug, (uint8_t *)STM32_BKPSRAM_BASE, sizeof debug);
}
#endif
@ -179,7 +183,7 @@ static void stm32_bbsram_rd(void)
static void stm32_bbsram_dump(FAR struct bbsramfh_s *bbf, char *op)
{
BBSRAM_DEBUG_READ();
lldbg("%s:\n",op);
lldbg("%s:\n", op);
lldbg(" File Address:0x%8x\n", bbf);
lldbg(" crc:0x%8x\n", bbf->crc);
lldbg(" fileno:%d\n", (int) bbf->fileno);
@ -287,7 +291,7 @@ static inline void stm32_bbsram_lock(void)
static uint32_t stm32_bbsram_crc(FAR struct bbsramfh_s *pf)
{
return crc32((uint8_t*)pf + BBSRAM_CRCED_OFFSET, BBSRAM_CRCED_SIZE(pf->len));
return crc32((uint8_t *)pf + BBSRAM_CRCED_OFFSET, BBSRAM_CRCED_SIZE(pf->len));
}
/****************************************************************************
@ -335,7 +339,7 @@ static int stm32_bbsram_internal_close(FAR struct bbsramfh_s *bbf)
(void)clock_gettime(CLOCK_REALTIME, &bbf->lastwrite);
bbf->crc = stm32_bbsram_crc(bbf);
BBSRAM_DUMP(bbf,"close done");
BBSRAM_DUMP(bbf, "close done");
return bbf->len;
}
@ -357,7 +361,7 @@ static int stm32_bbsram_close(FAR struct file *filep)
stm32_bbsram_semtake(bbr);
BBSRAM_DUMP(bbr->bbf,"close");
BBSRAM_DUMP(bbr->bbf, "close");
if (bbr->refs == 0)
{
@ -473,7 +477,7 @@ static ssize_t stm32_bbsram_read(FAR struct file *filep, FAR char *buffer,
len = bbr->bbf->len - filep->f_pos;
}
memcpy(buffer,&bbr->bbf->data[filep->f_pos], len);
memcpy(buffer, &bbr->bbf->data[filep->f_pos], len);
filep->f_pos += len;
stm32_bbsram_semgive(bbr);
return len;
@ -520,12 +524,12 @@ static ssize_t stm32_bbsram_write(FAR struct file *filep, FAR const char *buffer
ret = len; /* save number of bytes written */
stm32_bbsram_semtake(bbr);
BBSRAM_DUMP(bbr->bbf,"write");
BBSRAM_DUMP(bbr->bbf, "write");
stm32_bbsram_unlock();
stm32_bbsram_internal_write(bbr->bbf, buffer, filep->f_pos, len);
stm32_bbsram_lock();
filep->f_pos += len;
BBSRAM_DUMP(bbr->bbf,"write done");
BBSRAM_DUMP(bbr->bbf, "write done");
stm32_bbsram_semgive(bbr);
}
@ -543,7 +547,7 @@ static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
{
if (setup)
{
fds->revents |= (fds->events & (POLLIN|POLLOUT));
fds->revents |= (fds->events & (POLLIN | POLLOUT));
if (fds->revents != 0)
{
sem_post(fds->sem);
@ -650,7 +654,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[])
for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++)
{
/* Validate the actual allocations against what is in the BBSRAM*/
/* Validate the actual allocations against what is in the BBSRAM */
size = ent[i];
@ -680,11 +684,11 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[])
/* Not Valid so wipe the file in BBSRAM */
memset((uint8_t*)pf, 0, alloc);
memset((uint8_t *)pf, 0, alloc);
pf->fileno = i;
pf->len = size;
pf->crc = stm32_bbsram_crc(pf);
BBSRAM_DUMP(pf,"probe reset");
BBSRAM_DUMP(pf, "probe reset");
}
pdev[i].bbf = pf;
@ -769,8 +773,8 @@ int stm32_bbsraminitialize(char *devpath, int *sizes)
fcnt = stm32_bbsram_probe(sizes, g_bbsram);
strncpy(path,devpath,sizeof(path));
strcat(path,"%d");
strncpy(path, devpath, sizeof(path));
strcat(path, "%d");
for (i = 0; i < fcnt && ret >= OK; i++)
{
@ -785,22 +789,22 @@ int stm32_bbsraminitialize(char *devpath, int *sizes)
}
/****************************************************************************
* Function: stm32_bbsram_savepanic
*
* Description:
* Saves the panic context in a previously allocated BBSRAM file
*
* Parameters:
* fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL
* context - Pointer to a any array of bytes to save
* length - The length of the data pointed to byt context
*
* Returned Value:
* Length saved or negated errno.
*
* Assumptions:
*
****************************************************************************/
* Function: stm32_bbsram_savepanic
*
* Description:
* Saves the panic context in a previously allocated BBSRAM file
*
* Parameters:
* fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL
* context - Pointer to a any array of bytes to save
* length - The length of the data pointed to byt context
*
* Returned Value:
* Length saved or negated errno.
*
* Assumptions:
*
****************************************************************************/
#if defined(CONFIG_STM32_SAVE_CRASHDUMP)
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length)

91
arch/arm/src/stm32/stm32_can.c
View File

@ -249,10 +249,11 @@ static uint32_t can_vgetreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}
@ -261,20 +262,20 @@ static uint32_t can_vgetreg(uint32_t addr)
else
{
/* Did we print "..." for the previous value? */
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
lldbg("[repeats %d more times]\n", count-3);
}
lldbg("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
/* Save the new address, value, and count */
prevaddr = addr;
preval = val;
count = 1;
prevaddr = addr;
preval = val;
count = 1;
}
/* Show the register value read */
@ -500,8 +501,8 @@ static void can_dumpfiltregs(struct stm32_can_s *priv, FAR const char *msg)
for (i = 0; i < CAN_NFILTERS; i++)
{
lldbg(" F%dR1: %08x F%dR2: %08x\n",
i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i,1)),
i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i,2)));
i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)),
i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2)));
}
}
#endif
@ -883,22 +884,22 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
regval = tmp << CAN_TDLR_DATA0_SHIFT;
if (dlc > 1)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDLR_DATA1_SHIFT;
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDLR_DATA1_SHIFT;
if (dlc > 2)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDLR_DATA2_SHIFT;
if (dlc > 2)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDLR_DATA2_SHIFT;
if (dlc > 3)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDLR_DATA3_SHIFT;
}
}
}
if (dlc > 3)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDLR_DATA3_SHIFT;
}
}
}
}
can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval);
@ -909,22 +910,22 @@ static int can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg)
regval = tmp << CAN_TDHR_DATA4_SHIFT;
if (dlc > 5)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDHR_DATA5_SHIFT;
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDHR_DATA5_SHIFT;
if (dlc > 6)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDHR_DATA6_SHIFT;
if (dlc > 6)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDHR_DATA6_SHIFT;
if (dlc > 7)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDHR_DATA7_SHIFT;
}
}
}
if (dlc > 7)
{
tmp = (uint32_t)*ptr++;
regval |= tmp << CAN_TDHR_DATA7_SHIFT;
}
}
}
}
can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval);
@ -1357,7 +1358,7 @@ static int can_bittiming(struct stm32_can_s *priv)
ts1 = CONFIG_CAN_TSEG1;
ts2 = CONFIG_CAN_TSEG2;
brp = (tmp + (CAN_BIT_QUANTA/2)) / CAN_BIT_QUANTA;
DEBUGASSERT(brp >=1 && brp <= CAN_BTR_BRP_MAX);
DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX);
}
canllvdbg("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);

26
arch/arm/src/stm32/stm32_dma2d.c
View File

@ -693,7 +693,7 @@ static int stm32_dma2d_pixelformat(uint8_t fmt, uint8_t *fmtmap)
* A4
*/
switch(fmt)
switch (fmt)
{
#ifdef CONFIG_STM32_DMA2D_RGB565
case FB_FMT_RGB16_565:
@ -738,7 +738,7 @@ static int stm32_dma2d_bpp(uint8_t fmt, uint8_t *bpp)
{
gvdbg("fmt=%d, bpp=%p\n", fmt, bpp);
switch(fmt)
switch (fmt)
{
#ifdef CONFIG_STM32_DMA2D_RGB565
case FB_FMT_RGB16_565:
@ -1030,7 +1030,7 @@ static void stm32_dma2d_llnr(FAR struct stm32_dma2d_s *layer,
gvdbg("pixel per line: %d, number of lines: %d\n", area->xres, area->yres);
nlrreg = getreg32(STM32_DMA2D_NLR);
nlrreg = (DMA2D_NLR_PL(area->xres)|DMA2D_NLR_NL(area->yres));
nlrreg = (DMA2D_NLR_PL(area->xres) | DMA2D_NLR_NL(area->yres));
putreg32(nlrreg, STM32_DMA2D_NLR);
}
@ -1315,7 +1315,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer,
sem_post(priv->lock);
return ret;
}
}
#endif
if (priv->fmt != DMA2D_PF_L8)
@ -1342,7 +1342,7 @@ static int stm32_dma2dsetclut(FAR struct dma2d_layer_s *layer,
/* Update the layer clut entry */
#ifndef CONFIG_FB_TRANSPARENCY
uint8_t *clut888 = (uint8_t*)clut;
uint8_t *clut888 = (uint8_t *)clut;
uint16_t offset = 3 * n;
clut888[offset] = cmap->blue[n];
@ -1431,7 +1431,7 @@ static int stm32_dma2dgetclut(FAR struct dma2d_layer_s *layer,
for (n = cmap->first; n < cmap->len && n < STM32_DMA2D_NCLUT; n++)
{
#ifndef CONFIG_FB_TRANSPARENCY
uint8_t *clut888 = (uint8_t*)clut;
uint8_t *clut888 = (uint8_t *)clut;
uint16_t offset = 3 * n;
cmap->blue[n] = clut888[offset];
@ -2155,9 +2155,9 @@ int up_dma2dinitialize(void)
up_dma2duninitialize();
/* Enable dma2d is done in rcc_enableahb1, see
* arch/arm/src/stm32/stm32f40xxx_rcc.c
*/
/* Enable dma2d is done in rcc_enableahb1, see
* arch/arm/src/stm32/stm32f40xxx_rcc.c
*/
/* Initialize the DMA2D semaphore that enforces mutually exclusive access
* to the driver
@ -2172,13 +2172,13 @@ int up_dma2dinitialize(void)
#ifdef CONFIG_STM32_DMA2D_L8
/* Enable dma2d transfer and clut loading interrupts only */
stm32_dma2d_control(DMA2D_CR_TCIE|DMA2D_CR_CTCIE, DMA2D_CR_TEIE|
DMA2D_CR_TWIE|DMA2D_CR_CAEIE||DMA2D_CR_CEIE);
stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE, DMA2D_CR_TEIE |
DMA2D_CR_TWIE | DMA2D_CR_CAEIE | DMA2D_CR_CEIE);
#else
/* Enable dma transfer interrupt only */
stm32_dma2d_control(DMA2D_CR_TCIE, DMA2D_CR_TEIE|DMA2D_CR_TWIE|
DMA2D_CR_CAEIE|DMA2D_CR_CTCIE|DMA2D_CR_CEIE);
stm32_dma2d_control(DMA2D_CR_TCIE, DMA2D_CR_TEIE | DMA2D_CR_TWIE |
DMA2D_CR_CAEIE | DMA2D_CR_CTCIE | DMA2D_CR_CEIE);
#endif
/* Attach DMA2D interrupt vector */

53
arch/arm/src/stm32/stm32_eth.c
View File

@ -541,7 +541,7 @@
*/
#define ETH_DMAINT_NORMAL \
(ETH_DMAINT_TI | ETH_DMAINT_TBUI |ETH_DMAINT_RI | ETH_DMAINT_ERI)
(ETH_DMAINT_TI | ETH_DMAINT_TBUI | ETH_DMAINT_RI | ETH_DMAINT_ERI)
#define ETH_DMAINT_ABNORMAL \
(ETH_DMAINT_TPSI | ETH_DMAINT_TJTI | ETH_DMAINT_ROI | ETH_DMAINT_TUI | \
@ -768,10 +768,11 @@ static uint32_t stm32_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}
@ -780,20 +781,20 @@ static uint32_t stm32_getreg(uint32_t addr)
else
{
/* Did we print "..." for the previous value? */
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
lldbg("[repeats %d more times]\n", count-3);
}
lldbg("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
/* Save the new address, value, and count */
prevaddr = addr;
preval = val;
count = 1;
prevaddr = addr;
preval = val;
count = 1;
}
/* Show the register value read */
@ -1534,7 +1535,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
/* Check if this is an intermediate segment in the frame */
else if (((rxdesc->rdes0 & ETH_RDES0_LS) == 0)&&
else if (((rxdesc->rdes0 & ETH_RDES0_LS) == 0) &&
((rxdesc->rdes0 & ETH_RDES0_FS) == 0))
{
priv->segments++;
@ -1586,14 +1587,14 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
*/
DEBUGASSERT(dev->d_buf == NULL);
dev->d_buf = (uint8_t*)rxcurr->rdes2;
dev->d_buf = (uint8_t *)rxcurr->rdes2;
rxcurr->rdes2 = (uint32_t)buffer;
/* Return success, remebering where we should re-start scanning
* and resetting the segment scanning logic
*/
priv->rxhead = (struct eth_rxdesc_s*)rxdesc->rdes3;
priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3;
stm32_freesegment(priv, rxcurr, priv->segments);
nllvdbg("rxhead: %p d_buf: %p d_len: %d\n",
@ -1614,7 +1615,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
/* Try the next descriptor */
rxdesc = (struct eth_rxdesc_s*)rxdesc->rdes3;
rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3;
}
/* We get here after all of the descriptors have been scanned or when rxdesc points
@ -1744,7 +1745,7 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
*/
if (priv->dev.d_len > 0)
{
{
/* Update the Ethernet header with the correct MAC address */
#ifdef CONFIG_NET_IPv4
@ -1856,7 +1857,7 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
{
/* Yes.. Free the buffer */
stm32_freebuffer(priv, (uint8_t*)txdesc->tdes2);
stm32_freebuffer(priv, (uint8_t *)txdesc->tdes2);
}
/* In any event, make sure that TDES2 is nullified. */
@ -1889,7 +1890,7 @@ static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
/* Try the next descriptor in the TX chain */
txdesc = (struct eth_txdesc_s*)txdesc->tdes3;
txdesc = (struct eth_txdesc_s *)txdesc->tdes3;
}
/* We get here if (1) there are still frames "in-flight". Remember
@ -2702,7 +2703,7 @@ static int stm32_addmac(struct net_driver_s *dev, FAR const uint8_t *mac)
/* Add the MAC address to the hardware multicast hash table */
crc = stm32_calcethcrc( mac, 6 );
crc = stm32_calcethcrc(mac, 6);
hashindex = (crc >> 26) & 0x3F;
@ -2759,7 +2760,7 @@ static int stm32_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
/* Remove the MAC address to the hardware multicast hash table */
crc = stm32_calcethcrc( mac, 6 );
crc = stm32_calcethcrc(mac, 6);
hashindex = (crc >> 26) & 0x3F;
@ -2779,7 +2780,7 @@ static int stm32_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
/* If there is no address registered any more, delete multicast filtering */
if (stm32_getreg(STM32_ETH_MACHTHR ) == 0 &&
if (stm32_getreg(STM32_ETH_MACHTHR) == 0 &&
stm32_getreg(STM32_ETH_MACHTLR) == 0)
{
temp = stm32_getreg(STM32_ETH_MACFFR);
@ -4135,7 +4136,7 @@ int stm32_ethinitialize(int intf)
#ifdef CONFIG_NETDEV_PHY_IOCTL
priv->dev.d_ioctl = stm32_ioctl; /* Support PHY ioctl() calls */
#endif
priv->dev.d_private = (void*)g_stm32ethmac; /* Used to recover private state from dev */
priv->dev.d_private = (void *)g_stm32ethmac; /* Used to recover private state from dev */
/* Create a watchdog for timing polling for and timing of transmisstions */

2
arch/arm/src/stm32/stm32_flash.c
View File

@ -334,7 +334,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
modifyreg32(STM32_FLASH_CR, FLASH_CR_PSIZE_MASK, FLASH_CR_PSIZE_X16);
#endif
for (addr += STM32_FLASH_BASE; count; count-=2, hword++, addr+=2)
for (addr += STM32_FLASH_BASE; count; count -= 2, hword++, addr += 2)
{
/* Write half-word and wait to complete */

21
arch/arm/src/stm32/stm32_i2c.c
View File

@ -1021,7 +1021,7 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
/* Set DUTY and fast speed bits */
ccr |= (I2C_CCR_DUTY|I2C_CCR_FS);
ccr |= (I2C_CCR_DUTY | I2C_CCR_FS);
#else
/* Fast mode speed calculation with Tlow/Thigh = 2 */
@ -1105,7 +1105,7 @@ static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv)
*/
stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET,
I2C_CR1_START|I2C_CR1_STOP|I2C_CR1_PEC, 0);
I2C_CR1_START | I2C_CR1_STOP | I2C_CR1_PEC, 0);
}
/************************************************************************************
@ -1261,11 +1261,11 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
else if ((status & I2C_SR1_ADD10) != 0)
{
/* TODO: Finish 10-bit mode addressing.
*
* For now just clear ISR by writing to DR register. As we don't do
* 10 bit addressing this must be a spurious ISR
*/
/* TODO: Finish 10-bit mode addressing.
*
* For now just clear ISR by writing to DR register. As we don't do
* 10 bit addressing this must be a spurious ISR
*/
stm32_i2c_putreg(priv, STM32_I2C_DR_OFFSET, 0);
}
@ -1384,7 +1384,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX)
if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF|I2C_SR1_RXNE)) != 0)
if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF | I2C_SR1_RXNE)) != 0)
#else
if (priv->dcnt <= 0 && (status & I2C_SR1_BTF) != 0)
#endif
@ -1938,9 +1938,10 @@ static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev,
},
{
.addr = ((struct stm32_i2c_inst_s *)dev)->address,
.flags = ((struct stm32_i2c_inst_s *)dev)->flags | ((buflen>0) ? I2C_M_READ : I2C_M_NORESTART),
.flags = ((struct stm32_i2c_inst_s *)dev)->flags |
((buflen > 0) ? I2C_M_READ : I2C_M_NORESTART),
.buffer = buffer,
.length = (buflen>0) ? buflen : -buflen
.length = (buflen > 0) ? buflen : -buflen
}
};

27
arch/arm/src/stm32/stm32_i2c_alt.c
View File

@ -215,9 +215,9 @@ static const uint16_t I2CEVENT_NONE = 0; /* No events have occ
static const uint16_t I2CEVENT_STATE_ERROR = 1000; /* No correct state detected, diver cannot handle state */
static const uint16_t I2CEVENT_ISR_SHUTDOWN = 1001; /* ISR gets shutdown */
static const uint16_t I2CEVENT_ISR_EMPTY_CALL = 1002; /* ISR gets called but no I2C logic comes into play */
static const uint16_t I2CEVENT_MSG_HANDLING = 1003; /* Message Handling 1/1: advances the msg processing param = msgc*/
static const uint16_t I2CEVENT_MSG_HANDLING = 1003; /* Message Handling 1/1: advances the msg processing param = msgc */
static const uint16_t I2CEVENT_POLL_DEV_NOT_RDY = 1004; /* During polled operation if device is not ready yet */
static const uint16_t I2CEVENT_ISR_CALL = 1111; /* ISR called*/
static const uint16_t I2CEVENT_ISR_CALL = 1111; /* ISR called */
static const uint16_t I2CEVENT_SENDADDR = 5; /* Start/Master bit set and address sent, param = priv->msgv->addr(EV5 in reference manual) */
static const uint16_t I2CEVENT_ADDR_HDL_READ_1 = 51; /* Read of length 1 address handling, param = 0 */
@ -1029,7 +1029,7 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
/* Set DUTY and fast speed bits */
ccr |= (I2C_CCR_DUTY|I2C_CCR_FS);
ccr |= (I2C_CCR_DUTY | I2C_CCR_FS);
#else
/* Fast mode speed calculation with Tlow/Thigh = 2 */
@ -1113,7 +1113,7 @@ static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv)
*/
stm32_i2c_modifyreg(priv, STM32_I2C_CR1_OFFSET,
I2C_CR1_START|I2C_CR1_STOP|I2C_CR1_PEC, 0);
I2C_CR1_START | I2C_CR1_STOP | I2C_CR1_PEC, 0);
}
/************************************************************************************
@ -1428,7 +1428,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* received the address is valid and transmission can continue.
*/
/* Check for NACK after an address*/
/* Check for NACK after an address */
#ifndef CONFIG_I2C_POLLED
/* When polling the i2c ISR it's not possible to determine when
@ -1475,7 +1475,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
}
#endif
/* ACK in read mode, ACK in write mode is handled separately */
/* ACK in read mode, ACK in write mode is handled separately */
else if ((priv->flags & I2C_M_READ) != 0 && (status & I2C_SR1_ADDR) != 0 &&
priv->check_addr_ACK)
@ -1545,8 +1545,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* begin immediately after.
*/
else if ((priv->flags & (I2C_M_READ)) == 0 &&
(status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0)
else if ((priv->flags & (I2C_M_READ)) == 0 &&
(status & (I2C_SR1_ADDR | I2C_SR1_TXE)) != 0)
{
/* The has cleared(ADDR is set, ACK was received after the address)
* or the transmit buffer is empty flag has been set(TxE) then we can
@ -1627,7 +1627,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
{
/* Set condition to get to next message */
priv->dcnt =- 1;
priv->dcnt = -1;
stm32_i2c_traceevent(priv, I2CEVENT_WRITE_NO_RESTART, priv->dcnt);
}
else
@ -1674,7 +1674,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
else if ((priv->flags & (I2C_M_READ)) != 0 && (status & I2C_SR1_RXNE) != 0)
{
/* When read flag is set and the receive buffer is not empty
*(RXNE is set) then the driver can read from the data register.
* (RXNE is set) then the driver can read from the data register.
*/
i2cvdbg("Entering read mode dcnt = %i msgc = %i, status %i\n",
@ -1727,7 +1727,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
{
/* If the shift register is still empty (i.e. BTF is low)
* then do nothing and wait for it to fill in the next ISR.
*(should not happen in ISR mode, but if using polled mode
* (should not happen in ISR mode, but if using polled mode
* this should be able to handle it).
*/
@ -2382,9 +2382,10 @@ static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev,
},
{
.addr = ((struct stm32_i2c_inst_s *)dev)->address,
.flags = ((struct stm32_i2c_inst_s *)dev)->flags | ((buflen>0) ? I2C_M_READ : I2C_M_NORESTART),
.flags = ((struct stm32_i2c_inst_s *)dev)->flags |
((buflen > 0) ? I2C_M_READ : I2C_M_NORESTART),
.buffer = buffer,
.length = (buflen>0) ? buflen : -buflen
.length = (buflen > 0) ? buflen : -buflen
}
};

10
arch/arm/src/stm32/stm32_irq.c
View File

@ -60,9 +60,9 @@
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 |\
NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
NVIC_SYSH_PRIORITY_DEFAULT << 8 |\
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
@ -271,8 +271,8 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
else
{
*regaddr = NVIC_SYSHCON;
if (irq == STM32_IRQ_MEMFAULT)
*regaddr = NVIC_SYSHCON;
if (irq == STM32_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}

31
arch/arm/src/stm32/stm32_iwdg.c
View File

@ -213,10 +213,11 @@ static uint16_t stm32_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}
@ -225,20 +226,20 @@ static uint16_t stm32_getreg(uint32_t addr)
else
{
/* Did we print "..." for the previous value? */
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
lldbg("[repeats %d more times]\n", count-3);
}
lldbg("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
/* Save the new address, value, and count */
prevaddr = addr;
preval = val;
count = 1;
prevaddr = addr;
preval = val;
count = 1;
}
/* Show the register value read */
@ -301,7 +302,7 @@ static inline void stm32_setprescaler(FAR struct stm32_lowerhalf_s *priv)
*/
#ifndef CONFIG_STM32_IWDG_ONETIMESETUP
while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU|IWDG_SR_RVU)) != 0);
while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0);
#endif
/* Set the prescaler */

34
arch/arm/src/stm32/stm32_lowputc.c
View File

@ -232,13 +232,13 @@
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
# define USART_CR1_CLRBITS\
(USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS |\
USART_CR1_PCE |USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME |\
USART_CR1_OVER8 | USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK |\
(USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME | \
USART_CR1_OVER8 | USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK | \
USART_CR1_ALLINTS)
# else
# define USART_CR1_CLRBITS\
(USART_CR1_M | USART_CR1_PCE |USART_CR1_PS | USART_CR1_TE |\
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \
USART_CR1_RE | USART_CR1_ALLINTS)
# endif
@ -254,15 +254,15 @@
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
# define USART_CR2_CLRBITS \
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL |\
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK |\
USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV |\
USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK |\
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
USART_CR2_LINEN | USART_CR2_RXINV | USART_CR2_TXINV | USART_CR2_DATAINV | \
USART_CR2_MSBFIRST | USART_CR2_ABREN | USART_CR2_ABRMOD_MASK | \
USART_CR2_RTOEN | USART_CR2_ADD8_MASK)
# else
# define USART_CR2_CLRBITS \
(USART_CR2_STOP_MASK|USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|\
USART_CR2_LBCL|USART_CR2_LBDIE)
(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | \
USART_CR2_LBCL | USART_CR2_LBDIE)
# endif
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
@ -271,14 +271,14 @@
# if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
# define USART_CR3_CLRBITS \
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL |\
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT |\
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT |\
USART_CR1_OVRDIS | USART_CR1_DDRE | USART_CR1_DEM | USART_CR1_DEP |\
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR1_ONEBIT | \
USART_CR1_OVRDIS | USART_CR1_DDRE | USART_CR1_DEM | USART_CR1_DEP | \
USART_CR1_SCARCNT_MASK | USART_CR1_WUS_MASK | USART_CR1_WUFIE)
# else
# define USART_CR3_CLRBITS \
(USART_CR3_CTSIE|USART_CR3_CTSE|USART_CR3_RTSE|USART_CR3_EIE)
(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE)
# endif
# define USART_CR3_SETBITS 0
@ -555,7 +555,7 @@ void stm32_lowsetup(void)
/* Enable Rx, Tx, and the USART */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
@ -634,7 +634,7 @@ void stm32_lowsetup(void)
/* Enable Rx, Tx, and the USART */
cr |= (USART_CR1_UE|USART_CR1_TE|USART_CR1_RE);
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */

74
arch/arm/src/stm32/stm32_ltdc.c
View File

@ -469,7 +469,7 @@
enum stm32_layer_e
{
LTDC_LAYER_L1 = 0, /* LCD Layer 1*/
LTDC_LAYER_L1 = 0, /* LCD Layer 1 */
LTDC_LAYER_L2, /* LCD Layer 2 */
};
@ -579,7 +579,7 @@ static void stm32_ltdc_lblendmode(FAR struct stm32_layer_s *layer,
#ifdef STM32_LAYER_CLUT_SIZE
static void stm32_ltdc_lclut(FAR struct stm32_layer_s *layer,
FAR const struct fb_cmap_s *cmap);
static void stm32_ltdc_lclutenable(FAR struct stm32_layer_s* layer,
static void stm32_ltdc_lclutenable(FAR struct stm32_layer_s *layer,
bool enable);
#endif
static void stm32_ltdc_linit(int lid);
@ -687,7 +687,8 @@ static const struct fb_vtable_s g_vtable =
.getvideoinfo = stm32_getvideoinfo,
.getplaneinfo = stm32_getplaneinfo
#ifdef STM32_LAYER_CLUT_SIZE
,.getcmap = stm32_getcmap,
,
.getcmap = stm32_getcmap,
.putcmap = stm32_putcmap
#endif
};
@ -744,12 +745,13 @@ static struct stm32_ltdcdev_s g_ltdc =
.nplanes = 1
}
#ifdef STM32_LTDC_L1CMAP
,.clut = &g_clut[LTDC_L1CLUT_OFFSET]
, .clut = &g_clut[LTDC_L1CLUT_OFFSET]
#endif
}
}
#ifdef CONFIG_STM32_LTDC_L2
,.layer[LTDC_LAYER_L2] =
,
.layer[LTDC_LAYER_L2] =
{
.state =
{
@ -769,7 +771,7 @@ static struct stm32_ltdcdev_s g_ltdc =
.nplanes = 1
}
#ifdef STM32_LTDC_L2CMAP
,.clut = &g_clut[LTDC_L2CLUT_OFFSET]
, .clut = &g_clut[LTDC_L2CLUT_OFFSET]
#endif
}
}
@ -782,7 +784,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] =
{
STM32_LTDC_L1PFCR_PF
#ifdef CONFIG_STM32_LTDC_L2
,STM32_LTDC_L2PFCR_PF
, STM32_LTDC_L2PFCR_PF
#endif
};
@ -1297,7 +1299,7 @@ static void stm32_global_configure(void)
/* Enable register reload interrupt only */
stm32_ltdc_irqctrl(LTDC_IER_RRIE,LTDC_IER_TERRIE|LTDC_IER_FUIE|LTDC_IER_LIE);
stm32_ltdc_irqctrl(LTDC_IER_RRIE, LTDC_IER_TERRIE | LTDC_IER_FUIE | LTDC_IER_LIE);
/* Configure line interrupt */
@ -1383,7 +1385,7 @@ static void stm32_lcd_enable(bool enable)
****************************************************************************/
#ifdef STM32_LAYER_CLUT_SIZE
static void stm32_ltdc_lclutenable(FAR struct stm32_layer_s* layer, bool enable)
static void stm32_ltdc_lclutenable(FAR struct stm32_layer_s *layer, bool enable)
{
uint32_t regval;
@ -1879,7 +1881,7 @@ static void stm32_ltdc_lclut(FAR struct stm32_layer_s *layer,
{
/* Update the layer clut entry */
#ifndef CONFIG_FB_TRANSPARENCY
uint8_t *clut888 = (uint8_t*)clut;
uint8_t *clut888 = (uint8_t *)clut;
uint16_t offset = 3 * n;
clut888[offset] = cmap->blue[n];
@ -1978,7 +1980,7 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer,
#if STM32_LTDC_L1_BPP == 8 || STM32_LTDC_L2_BPP == 8
if (priv->pinfo.bpp == 8)
{
uint8_t *dest = (uint8_t*)priv->pinfo.fbmem;
uint8_t *dest = (uint8_t *)priv->pinfo.fbmem;
int i;
gvdbg("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
@ -1996,7 +1998,7 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer,
#if STM32_LTDC_L1_BPP == 16 || STM32_LTDC_L2_BPP == 16
if (priv->pinfo.bpp == 16)
{
uint16_t *dest = (uint16_t*)priv->pinfo.fbmem;
uint16_t *dest = (uint16_t *)priv->pinfo.fbmem;
int i;
gvdbg("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
@ -2014,7 +2016,7 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer,
#if STM32_LTDC_L1_BPP == 24 || STM32_LTDC_L2_BPP == 24
if (priv->pinfo.bpp == 24)
{
uint8_t *dest = (uint8_t*)priv->pinfo.fbmem;
uint8_t *dest = (uint8_t *)priv->pinfo.fbmem;
uint8_t r;
uint8_t g;
uint8_t b;
@ -2041,7 +2043,7 @@ static void stm32_ltdc_lclear(FAR struct stm32_layer_s *layer,
#if STM32_LTDC_L1_BPP == 32 || STM32_LTDC_L2_BPP == 32
if (priv->pinfo.bpp == 32)
{
uint32_t *dest = (uint32_t*)priv->pinfo.fbmem;
uint32_t *dest = (uint32_t *)priv->pinfo.fbmem;
int i;
gvdbg("Clearing display: BPP=%d color=%04x framebuffer=%08x size=%d\n",
@ -2192,9 +2194,9 @@ static int stm32_getvideoinfo(struct fb_vtable_s *vtable,
{
FAR struct ltdc_layer_s *ltdc;
#ifdef CONFIG_STM32_LTDC_L2
ltdc = (FAR struct ltdc_layer_s*)&LAYER_L2;
ltdc = (FAR struct ltdc_layer_s *)&LAYER_L2;
#else
ltdc = (FAR struct ltdc_layer_s*)&LAYER_L1;
ltdc = (FAR struct ltdc_layer_s *)&LAYER_L1;
#endif
return stm32_lgetvideoinfo(ltdc, vinfo);
}
@ -2227,9 +2229,9 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno,
{
FAR struct ltdc_layer_s *ltdc;
#ifdef CONFIG_STM32_LTDC_L2
ltdc = (FAR struct ltdc_layer_s*)&LAYER_L2;
ltdc = (FAR struct ltdc_layer_s *)&LAYER_L2;
#else
ltdc = (FAR struct ltdc_layer_s*)&LAYER_L1;
ltdc = (FAR struct ltdc_layer_s *)&LAYER_L1;
#endif
return stm32_lgetplaneinfo(ltdc, planeno, pinfo);
}
@ -2259,9 +2261,9 @@ static int stm32_getcmap(struct fb_vtable_s *vtable,
struct fb_cmap_s *cmap)
{
#ifdef CONFIG_STM32_LTDC_L2
return stm32_getclut((FAR struct ltdc_layer_s*)&LAYER_L2, cmap);
return stm32_getclut((FAR struct ltdc_layer_s *)&LAYER_L2, cmap);
#else
return stm32_getclut((FAR struct ltdc_layer_s*)&LAYER_L1, cmap);
return stm32_getclut((FAR struct ltdc_layer_s *)&LAYER_L1, cmap);
#endif
}
@ -2285,9 +2287,9 @@ static int stm32_putcmap(struct fb_vtable_s *vtable,
const struct fb_cmap_s *cmap)
{
#ifdef CONFIG_STM32_LTDC_L2
return stm32_setclut((FAR struct ltdc_layer_s*)&LAYER_L2, cmap);
return stm32_setclut((FAR struct ltdc_layer_s *)&LAYER_L2, cmap);
#else
return stm32_setclut((FAR struct ltdc_layer_s*)&LAYER_L1, cmap);
return stm32_setclut((FAR struct ltdc_layer_s *)&LAYER_L1, cmap);
#endif
}
#endif /* STM32_LAYER_CLUT_SIZE */
@ -2446,8 +2448,7 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
{
sem_wait(priv->state.lock);
#ifdef CONFIG_STM32_DMA2D
/*
* Note! We share the same color lookup table with the dma2d driver and
/* Note! We share the same color lookup table with the dma2d driver and
* the getclut implementation works in the same way.
* To prevent redundant code we simply call the getclut function of the
* dma2d interface.
@ -2479,7 +2480,7 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++)
{
# ifndef CONFIG_FB_TRANSPARENCY
uint8_t *clut888 = (uint8_t*)clut;
uint8_t *clut888 = (uint8_t *)clut;
uint16_t offset = 3 * n;
cmap->blue[n] = clut888[offset];
@ -2534,7 +2535,8 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
*
****************************************************************************/
static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid, uint32_t flag)
static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid,
uint32_t flag)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;
@ -2863,10 +2865,10 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode)
/* Disable colorkeying by default */
priv->operation &=~ LTDC_LAYER_ENABLECOLORKEY;
priv->operation &= ~LTDC_LAYER_ENABLECOLORKEY;
if (blendmode & (LTDC_BLEND_ALPHA|LTDC_BLEND_PIXELALPHA|
LTDC_BLEND_ALPHAINV|LTDC_BLEND_PIXELALPHAINV))
if (blendmode & (LTDC_BLEND_ALPHA | LTDC_BLEND_PIXELALPHA |
LTDC_BLEND_ALPHAINV | LTDC_BLEND_PIXELALPHAINV))
{
/* Enable any alpha blending */
@ -2929,8 +2931,8 @@ static int stm32_setblendmode(FAR struct ltdc_layer_s *layer, uint32_t mode)
if (ret == OK)
{
priv->state.blendmode = mode;
priv->operation |= (LTDC_LAYER_SETBLENDMODE|
LTDC_LAYER_SETALPHAVALUE|
priv->operation |= (LTDC_LAYER_SETBLENDMODE |
LTDC_LAYER_SETALPHAVALUE |
LTDC_LAYER_SETCOLORKEY);
}
@ -3214,9 +3216,9 @@ static int stm32_update(FAR struct ltdc_layer_s *layer, uint32_t mode)
* settings restored during the next update (non flip) operation
*/
active->operation |= (LTDC_LAYER_SETBLENDMODE|
LTDC_LAYER_ENABLE|
LTDC_LAYER_SETCOLOR|
active->operation |= (LTDC_LAYER_SETBLENDMODE |
LTDC_LAYER_ENABLE |
LTDC_LAYER_SETCOLOR |
LTDC_LAYER_SETENABLE);
/* Change layer activity */
@ -3543,8 +3545,8 @@ void stm32_ltdcuninitialize(void)
{
/* Disable all ltdc interrupts */
stm32_ltdc_irqctrl(0, LTDC_IER_RRIE|LTDC_IER_TERRIE|
LTDC_IER_FUIE|LTDC_IER_LIE);
stm32_ltdc_irqctrl(0, LTDC_IER_RRIE | LTDC_IER_TERRIE |
LTDC_IER_FUIE | LTDC_IER_LIE);
up_disable_irq(g_interrupt.irq);
irq_detach(g_interrupt.irq);

297
arch/arm/src/stm32/stm32_otgfsdev.c
View File

@ -811,10 +811,11 @@ static uint32_t stm32_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}
@ -823,20 +824,20 @@ static uint32_t stm32_getreg(uint32_t addr)
else
{
/* Did we print "..." for the previous value? */
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
lldbg("[repeats %d more times]\n", count-3);
}
lldbg("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
/* Save the new address, value, and count */
prevaddr = addr;
preval = val;
count = 1;
prevaddr = addr;
preval = val;
count = 1;
}
/* Show the register value read */
@ -1228,10 +1229,10 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
if (privreq->req.len == 0)
{
/* The ZLP flag is set TRUE whenever we want to force the driver to
* send a zero-length-packet on the next pass through the loop (below).
* The flag is cleared whenever a packet is sent in the loop below.
*/
/* The ZLP flag is set TRUE whenever we want to force the driver to
* send a zero-length-packet on the next pass through the loop (below).
* The flag is cleared whenever a packet is sent in the loop below.
*/
privep->zlp = true;
}
@ -1669,7 +1670,7 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
* read request is encountered.
*/
for (;;)
for (; ; )
{
/* Get a reference to the request at the head of the endpoint's request queue */
@ -3127,133 +3128,133 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
if (epphy < STM32_NENDPOINTS)
{
privep = &priv->epout[epphy];
privep = &priv->epout[epphy];
/* Handle the RX event according to the packet status field */
/* Handle the RX event according to the packet status field */
switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
{
/* Global OUT NAK. This indicate that the global OUT NAK bit has taken
* effect.
*
* PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
* Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
switch (regval & OTGFS_GRXSTSD_PKTSTS_MASK)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0);
/* Global OUT NAK. This indicate that the global OUT NAK bit has taken
* effect.
*
* PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
* Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTNAK:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0);
}
break;
/* OUT data packet received.
*
* PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
* EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy);
bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
if (bcnt > 0)
{
stm32_epout_receive(privep, bcnt);
}
}
break;
/* OUT transfer completed. This indicates that an OUT data transfer for
* the specified OUT endpoint has completed. After this entry is popped
* from the receive FIFO, the core asserts a Transfer Completed interrupt
* on the specified OUT endpoint.
*
* PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
* which the data transfer is complete, DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy);
}
break;
/* SETUP transaction completed. This indicates that the Setup stage for
* the specified endpoint has completed and the Data stage has started.
* After this entry is popped from the receive FIFO, the core asserts a
* Setup interrupt on the specified control OUT endpoint (triggers an
* interrupt).
*
* PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
* DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
}
break;
/* SETUP data packet received. This indicates that a SETUP packet for the
* specified endpoint is now available for reading from the receive FIFO.
*
* PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
{
uint16_t datlen;
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy);
/* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
* the last one overwrites the previous setup packets and only that
* last SETUP packet will be processed.
*/
stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
USB_SIZEOF_CTRLREQ);
/* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
* then we need to wait for the completion of the data phase to
* process the setup command. If it is an IN SETUP packet, then
* we must processing the command BEFORE we enter the DATA phase.
*
* If the data associated with the OUT SETUP packet is zero length,
* then, of course, we don't need to wait.
*/
datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{
/* Clear NAKSTS so that we can receive the data */
regval = stm32_getreg(STM32_OTGFS_DOEPCTL0);
regval |= OTGFS_DOEPCTL0_CNAK;
stm32_putreg(regval, STM32_OTGFS_DOEPCTL0);
/* Wait for the data phase. */
priv->ep0state = EP0STATE_SETUP_OUT;
}
else
{
/* We can process the setup data as soon as SETUP done word is
* popped of the RxFIFO.
*/
priv->ep0state = EP0STATE_SETUP_READY;
}
}
break;
default:
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS),
(regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT);
}
break;
}
break;
/* OUT data packet received.
*
* PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
* EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTRECVD:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy);
bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT;
if (bcnt > 0)
{
stm32_epout_receive(privep, bcnt);
}
}
break;
/* OUT transfer completed. This indicates that an OUT data transfer for
* the specified OUT endpoint has completed. After this entry is popped
* from the receive FIFO, the core asserts a Transfer Completed interrupt
* on the specified OUT endpoint.
*
* PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
* which the data transfer is complete, DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_OUTDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy);
}
break;
/* SETUP transaction completed. This indicates that the Setup stage for
* the specified endpoint has completed and the Data stage has started.
* After this entry is popped from the receive FIFO, the core asserts a
* Setup interrupt on the specified control OUT endpoint (triggers an
* interrupt).
*
* PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
* DPID = Don't Care.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
}
break;
/* SETUP data packet received. This indicates that a SETUP packet for the
* specified endpoint is now available for reading from the receive FIFO.
*
* PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
*/
case OTGFS_GRXSTSD_PKTSTS_SETUPRECVD:
{
uint16_t datlen;
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy);
/* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
* the last one overwrites the previous setup packets and only that
* last SETUP packet will be processed.
*/
stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t*)&priv->ctrlreq,
USB_SIZEOF_CTRLREQ);
/* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
* then we need to wait for the completion of the data phase to
* process the setup command. If it is an IN SETUP packet, then
* we must processing the command BEFORE we enter the DATA phase.
*
* If the data associated with the OUT SETUP packet is zero length,
* then, of course, we don't need to wait.
*/
datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{
/* Clear NAKSTS so that we can receive the data */
regval = stm32_getreg(STM32_OTGFS_DOEPCTL0);
regval |= OTGFS_DOEPCTL0_CNAK;
stm32_putreg(regval, STM32_OTGFS_DOEPCTL0);
/* Wait for the data phase. */
priv->ep0state = EP0STATE_SETUP_OUT;
}
else
{
/* We can process the setup data as soon as SETUP done word is
* popped of the RxFIFO.
*/
priv->ep0state = EP0STATE_SETUP_READY;
}
}
break;
default:
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS),
(regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT);
}
break;
}
}
/* Enable the Rx Status Queue Level interrupt */
@ -3474,9 +3475,9 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv)
regval = stm32_getreg(STM32_OTGFS_GOTGINT);
if ((regval & OTGFS_GOTGINT_SEDET) != 0)
{
{
#warning "Missing logic"
}
}
/* Clear OTG interrupt */
@ -3514,7 +3515,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
* events.
*/
for (;;)
for (; ; )
{
/* Get the set of pending, un-masked interrupts */
@ -3572,7 +3573,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
stm32_putreg(OTGFS_GINT_WKUP, STM32_OTGFS_GINTSTS);
}
/* USB suspend interrupt */
/* USB suspend interrupt */
if ((regval & OTGFS_GINT_USBSUSP) != 0)
{
@ -4758,7 +4759,7 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev,
irqrestore(flags);
return in ? &priv->epin[epno].ep : &priv->epout[epno].ep;
}
}
}
/* We should not get here */
}
@ -4840,7 +4841,7 @@ static int stm32_wakeup(struct usbdev_s *dev)
regval = stm32_getreg(STM32_OTGFS_DSTS);
if ((regval & OTGFS_DSTS_SUSPSTS) != 0)
{
/* Re-start the PHY clock and un-gate USB core clock (HCLK) */
/* Re-start the PHY clock and un-gate USB core clock (HCLK) */
#ifdef CONFIG_USBDEV_LOWPOWER
regval = stm32_getreg(STM32_OTGFS_PCGCCTL);

59
arch/arm/src/stm32/stm32_otgfshost.c
View File

@ -73,8 +73,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***************************************************************/
/*
* STM32 USB OTG FS Host Driver Support
/* STM32 USB OTG FS Host Driver Support
*
* Pre-requisites
*
@ -730,14 +729,14 @@ static void stm32_chan_free(FAR struct stm32_usbhost_s *priv, int chidx)
static inline void stm32_chan_freeall(FAR struct stm32_usbhost_s *priv)
{
uint8_t chidx;
uint8_t chidx;
/* Free all host channels */
/* Free all host channels */
for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx ++)
{
stm32_chan_free(priv, chidx);
}
for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx ++)
{
stm32_chan_free(priv, chidx);
}
}
/****************************************************************************
@ -1651,9 +1650,9 @@ static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
return ret;
}
/* Get the elapsed time (in frames) */
/* Get the elapsed time (in frames) */
elapsed = clock_systimer() - start;
elapsed = clock_systimer() - start;
}
while (elapsed < STM32_SETUP_DELAY);
@ -1872,7 +1871,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
if (ret < 0)
{
usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED,ret);
usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED, ret);
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
@ -2117,7 +2116,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_chan_waitsetup(priv, chan);
if (ret < 0)
{
usbhost_trace1(OTGFS_TRACE1_DEVDISCONN,0);
usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0);
return (ssize_t)ret;
}
@ -2130,7 +2129,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Wait for the transfer to complete and get the result */
/* Wait for the transfer to complete and get the result */
ret = stm32_chan_wait(priv, chan);
@ -2138,7 +2137,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
if (ret < 0)
{
usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED,ret);
usbhost_trace1(OTGFS_TRACE1_TRNSFRFAILED, ret);
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
@ -2204,7 +2203,7 @@ static void stm32_out_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK?*/
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2837,7 +2836,7 @@ static void stm32_gint_connected(FAR struct stm32_usbhost_s *priv)
{
/* Yes.. then now we are connected */
usbhost_vtrace1(OTGFS_VTRACE1_CONNECTED,0);
usbhost_vtrace1(OTGFS_VTRACE1_CONNECTED, 0);
priv->connected = true;
priv->change = true;
DEBUGASSERT(priv->smstate == SMSTATE_DETACHED);
@ -2869,16 +2868,16 @@ static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv)
{
/* Yes.. then we no longer connected */
usbhost_vtrace1(OTGFS_VTRACE1_DISCONNECTED,0);
usbhost_vtrace1(OTGFS_VTRACE1_DISCONNECTED, 0);
/* Are we bound to a class driver? */
if ( priv->rhport.hport.devclass)
if (priv->rhport.hport.devclass)
{
/* Yes.. Disconnect the class driver */
CLASS_DISCONNECTED( priv->rhport.hport.devclass);
priv->rhport.hport.devclass = NULL;
CLASS_DISCONNECTED(priv->rhport.hport.devclass);
priv->rhport.hport.devclass = NULL;
}
/* Re-Initialize Host for new Enumeration */
@ -2890,9 +2889,9 @@ static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv)
priv->rhport.hport.speed = USB_SPEED_FULL;
/* Notify any waiters that there is a change in the connection state */
/* Notify any waiters that there is a change in the connection state */
if (priv->pscwait)
if (priv->pscwait)
{
stm32_givesem(&priv->pscsem);
priv->pscwait = false;
@ -3450,7 +3449,7 @@ static int stm32_gint_isr(int irq, FAR void *context)
* little interrupt handling overhead.
*/
for (;;)
for (; ; )
{
/* Get the unmasked bits in the GINT status */
@ -3741,7 +3740,7 @@ static int stm32_wait(FAR struct usbhost_connection_s *conn,
/* Loop until a change in connection state is detected */
flags = irqsave();
for (;;)
for (; ; )
{
/* Is there a change in the connection state of the single root hub
* port?
@ -3835,7 +3834,7 @@ static int stm32_rh_enumerate(FAR struct stm32_usbhost_s *priv,
{
/* No, return an error */
usbhost_trace1(OTGFS_TRACE1_DEVDISCONN,0);
usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0);
return -ENODEV;
}
@ -4333,7 +4332,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
ret = stm32_ctrl_sendsetup(priv, ep0info, req);
if (ret < 0)
{
{
usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret);
continue;
}
@ -4805,7 +4804,8 @@ static void stm32_portreset(FAR struct stm32_usbhost_s *priv)
uint32_t regval;
regval = stm32_getreg(STM32_OTGFS_HPRT);
regval &= ~(OTGFS_HPRT_PENA|OTGFS_HPRT_PCDET|OTGFS_HPRT_PENCHNG|OTGFS_HPRT_POCCHNG);
regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG |
OTGFS_HPRT_POCCHNG);
regval |= OTGFS_HPRT_PRST;
stm32_putreg(STM32_OTGFS_HPRT, regval);
@ -4922,7 +4922,8 @@ static void stm32_vbusdrive(FAR struct stm32_usbhost_s *priv, bool state)
/* Turn on the Host port power. */
regval = stm32_getreg(STM32_OTGFS_HPRT);
regval &= ~(OTGFS_HPRT_PENA|OTGFS_HPRT_PCDET|OTGFS_HPRT_PENCHNG|OTGFS_HPRT_POCCHNG);
regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG |
OTGFS_HPRT_POCCHNG);
if (((regval & OTGFS_HPRT_PPWR) == 0) && state)
{
@ -5132,7 +5133,7 @@ static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv)
* transceiver: "This bit is always 1 with write-only access"
*/
regval = stm32_getreg(STM32_OTGFS_GUSBCFG);;
regval = stm32_getreg(STM32_OTGFS_GUSBCFG);
regval |= OTGFS_GUSBCFG_PHYSEL;
stm32_putreg(STM32_OTGFS_GUSBCFG, regval);

300
arch/arm/src/stm32/stm32_otghsdev.c
View File

@ -811,10 +811,11 @@ static uint32_t stm32_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}
@ -823,20 +824,20 @@ static uint32_t stm32_getreg(uint32_t addr)
else
{
/* Did we print "..." for the previous value? */
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
lldbg("[repeats %d more times]\n", count-3);
}
lldbg("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
/* Save the new address, value, and count */
prevaddr = addr;
preval = val;
count = 1;
prevaddr = addr;
preval = val;
count = 1;
}
/* Show the register value read */
@ -1228,12 +1229,12 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
if (privreq->req.len == 0)
{
/* The ZLP flag is set TRUE whenever we want to force the driver to
* send a zero-length-packet on the next pass through the loop (below).
* The flag is cleared whenever a packet is sent in the loop below.
*/
/* The ZLP flag is set TRUE whenever we want to force the driver to
* send a zero-length-packet on the next pass through the loop (below).
* The flag is cleared whenever a packet is sent in the loop below.
*/
privep->zlp = true;
privep->zlp = true;
}
/* Add one more packet to the TxFIFO. We will wait for the transfer
@ -1669,7 +1670,7 @@ static void stm32_epout_request(FAR struct stm32_usbdev_s *priv,
* read request is encountered.
*/
for (;;)
for (; ; )
{
/* Get a reference to the request at the head of the endpoint's request queue */
@ -3127,133 +3128,133 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
if (epphy < STM32_NENDPOINTS)
{
privep = &priv->epout[epphy];
privep = &priv->epout[epphy];
/* Handle the RX event according to the packet status field */
/* Handle the RX event according to the packet status field */
switch (regval & OTGHS_GRXSTSD_PKTSTS_MASK)
{
/* Global OUT NAK. This indicate that the global OUT NAK bit has taken
* effect.
*
* PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
* Care.
*/
case OTGHS_GRXSTSD_PKTSTS_OUTNAK:
switch (regval & OTGHS_GRXSTSD_PKTSTS_MASK)
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0);
/* Global OUT NAK. This indicate that the global OUT NAK bit has taken
* effect.
*
* PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't
* Care.
*/
case OTGHS_GRXSTSD_PKTSTS_OUTNAK:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0);
}
break;
/* OUT data packet received.
*
* PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
* EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
*/
case OTGHS_GRXSTSD_PKTSTS_OUTRECVD:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy);
bcnt = (regval & OTGHS_GRXSTSD_BCNT_MASK) >> OTGHS_GRXSTSD_BCNT_SHIFT;
if (bcnt > 0)
{
stm32_epout_receive(privep, bcnt);
}
}
break;
/* OUT transfer completed. This indicates that an OUT data transfer for
* the specified OUT endpoint has completed. After this entry is popped
* from the receive FIFO, the core asserts a Transfer Completed interrupt
* on the specified OUT endpoint.
*
* PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
* which the data transfer is complete, DPID = Don't Care.
*/
case OTGHS_GRXSTSD_PKTSTS_OUTDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy);
}
break;
/* SETUP transaction completed. This indicates that the Setup stage for
* the specified endpoint has completed and the Data stage has started.
* After this entry is popped from the receive FIFO, the core asserts a
* Setup interrupt on the specified control OUT endpoint (triggers an
* interrupt).
*
* PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
* DPID = Don't Care.
*/
case OTGHS_GRXSTSD_PKTSTS_SETUPDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
}
break;
/* SETUP data packet received. This indicates that a SETUP packet for the
* specified endpoint is now available for reading from the receive FIFO.
*
* PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
*/
case OTGHS_GRXSTSD_PKTSTS_SETUPRECVD:
{
uint16_t datlen;
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy);
/* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
* the last one overwrites the previous setup packets and only that
* last SETUP packet will be processed.
*/
stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq,
USB_SIZEOF_CTRLREQ);
/* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
* then we need to wait for the completion of the data phase to
* process the setup command. If it is an IN SETUP packet, then
* we must processing the command BEFORE we enter the DATA phase.
*
* If the data associated with the OUT SETUP packet is zero length,
* then, of course, we don't need to wait.
*/
datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{
/* Clear NAKSTS so that we can receive the data */
regval = stm32_getreg(STM32_OTGHS_DOEPCTL0);
regval |= OTGHS_DOEPCTL0_CNAK;
stm32_putreg(regval, STM32_OTGHS_DOEPCTL0);
/* Wait for the data phase. */
priv->ep0state = EP0STATE_SETUP_OUT;
}
else
{
/* We can process the setup data as soon as SETUP done word is
* popped of the RxFIFO.
*/
priv->ep0state = EP0STATE_SETUP_READY;
}
}
break;
default:
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS),
(regval & OTGHS_GRXSTSD_PKTSTS_MASK) >> OTGHS_GRXSTSD_PKTSTS_SHIFT);
}
break;
}
break;
/* OUT data packet received.
*
* PKTSTS = DataOUT, BCNT = size of the received data OUT packet,
* EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
*/
case OTGHS_GRXSTSD_PKTSTS_OUTRECVD:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy);
bcnt = (regval & OTGHS_GRXSTSD_BCNT_MASK) >> OTGHS_GRXSTSD_BCNT_SHIFT;
if (bcnt > 0)
{
stm32_epout_receive(privep, bcnt);
}
}
break;
/* OUT transfer completed. This indicates that an OUT data transfer for
* the specified OUT endpoint has completed. After this entry is popped
* from the receive FIFO, the core asserts a Transfer Completed interrupt
* on the specified OUT endpoint.
*
* PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on
* which the data transfer is complete, DPID = Don't Care.
*/
case OTGHS_GRXSTSD_PKTSTS_OUTDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy);
}
break;
/* SETUP transaction completed. This indicates that the Setup stage for
* the specified endpoint has completed and the Data stage has started.
* After this entry is popped from the receive FIFO, the core asserts a
* Setup interrupt on the specified control OUT endpoint (triggers an
* interrupt).
*
* PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num,
* DPID = Don't Care.
*/
case OTGHS_GRXSTSD_PKTSTS_SETUPDONE:
{
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy);
}
break;
/* SETUP data packet received. This indicates that a SETUP packet for the
* specified endpoint is now available for reading from the receive FIFO.
*
* PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
*/
case OTGHS_GRXSTSD_PKTSTS_SETUPRECVD:
{
uint16_t datlen;
usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy);
/* Read EP0 setup data. NOTE: If multiple SETUP packets are received,
* the last one overwrites the previous setup packets and only that
* last SETUP packet will be processed.
*/
stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t*)&priv->ctrlreq,
USB_SIZEOF_CTRLREQ);
/* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP,
* then we need to wait for the completion of the data phase to
* process the setup command. If it is an IN SETUP packet, then
* we must processing the command BEFORE we enter the DATA phase.
*
* If the data associated with the OUT SETUP packet is zero length,
* then, of course, we don't need to wait.
*/
datlen = GETUINT16(priv->ctrlreq.len);
if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0)
{
/* Clear NAKSTS so that we can receive the data */
regval = stm32_getreg(STM32_OTGHS_DOEPCTL0);
regval |= OTGHS_DOEPCTL0_CNAK;
stm32_putreg(regval, STM32_OTGHS_DOEPCTL0);
/* Wait for the data phase. */
priv->ep0state = EP0STATE_SETUP_OUT;
}
else
{
/* We can process the setup data as soon as SETUP done word is
* popped of the RxFIFO.
*/
priv->ep0state = EP0STATE_SETUP_READY;
}
}
break;
default:
{
usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS),
(regval & OTGHS_GRXSTSD_PKTSTS_MASK) >> OTGHS_GRXSTSD_PKTSTS_SHIFT);
}
break;
}
}
/* Enable the Rx Status Queue Level interrupt */
@ -3474,9 +3475,9 @@ static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv)
regval = stm32_getreg(STM32_OTGHS_GOTGINT);
if ((regval & OTGHS_GOTGINT_SEDET) != 0)
{
{
#warning "Missing logic"
}
}
/* Clear OTG interrupt */
@ -3514,7 +3515,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
* events.
*/
for (;;)
for (; ; )
{
/* Get the set of pending, un-masked interrupts */
@ -3572,7 +3573,7 @@ static int stm32_usbinterrupt(int irq, FAR void *context)
stm32_putreg(OTGHS_GINT_WKUP, STM32_OTGHS_GINTSTS);
}
/* USB suspend interrupt */
/* USB suspend interrupt */
if ((regval & OTGHS_GINT_USBSUSP) != 0)
{
@ -4758,7 +4759,7 @@ static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev,
irqrestore(flags);
return in ? &priv->epin[epno].ep : &priv->epout[epno].ep;
}
}
}
/* We should not get here */
}
@ -4840,7 +4841,7 @@ static int stm32_wakeup(struct usbdev_s *dev)
regval = stm32_getreg(STM32_OTGHS_DSTS);
if ((regval & OTGHS_DSTS_SUSPSTS) != 0)
{
/* Re-start the PHY clock and un-gate USB core clock (HCLK) */
/* Re-start the PHY clock and un-gate USB core clock (HCLK) */
#ifdef CONFIG_USBDEV_LOWPOWER
regval = stm32_getreg(STM32_OTGHS_PCGCCTL);
@ -5657,4 +5658,3 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
}
#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGHSDEV */

57
arch/arm/src/stm32/stm32_otghshost.c
View File

@ -73,8 +73,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***************************************************************/
/*
* STM32 USB OTG HS Host Driver Support
/* STM32 USB OTG HS Host Driver Support
*
* Pre-requisites
*
@ -730,14 +729,14 @@ static void stm32_chan_free(FAR struct stm32_usbhost_s *priv, int chidx)
static inline void stm32_chan_freeall(FAR struct stm32_usbhost_s *priv)
{
uint8_t chidx;
uint8_t chidx;
/* Free all host channels */
/* Free all host channels */
for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx ++)
{
stm32_chan_free(priv, chidx);
}
for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx ++)
{
stm32_chan_free(priv, chidx);
}
}
/****************************************************************************
@ -1651,9 +1650,9 @@ static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
return ret;
}
/* Get the elapsed time (in frames) */
/* Get the elapsed time (in frames) */
elapsed = clock_systimer() - start;
elapsed = clock_systimer() - start;
}
while (elapsed < STM32_SETUP_DELAY);
@ -1872,7 +1871,7 @@ static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
if (ret < 0)
{
usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED,ret);
usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED, ret);
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
@ -2117,7 +2116,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
ret = stm32_chan_waitsetup(priv, chan);
if (ret < 0)
{
usbhost_trace1(OTGHS_TRACE1_DEVDISCONN,0);
usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0);
return (ssize_t)ret;
}
@ -2130,7 +2129,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
return (ssize_t)ret;
}
/* Wait for the transfer to complete and get the result */
/* Wait for the transfer to complete and get the result */
ret = stm32_chan_wait(priv, chan);
@ -2138,7 +2137,7 @@ static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
if (ret < 0)
{
usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED,ret);
usbhost_trace1(OTGHS_TRACE1_TRNSFRFAILED, ret);
/* Check for a special case: If (1) the transfer was NAKed and (2)
* no Tx FIFO empty or Rx FIFO not-empty event occurred, then we
@ -2204,7 +2203,7 @@ static void stm32_out_next(FAR struct stm32_usbhost_s *priv,
int result;
int ret;
/* Is the full transfer complete? Did the last chunk transfer complete OK?*/
/* Is the full transfer complete? Did the last chunk transfer complete OK? */
result = -(int)chan->result;
if (chan->xfrd < chan->buflen && result == OK)
@ -2837,7 +2836,7 @@ static void stm32_gint_connected(FAR struct stm32_usbhost_s *priv)
{
/* Yes.. then now we are connected */
usbhost_vtrace1(OTGHS_VTRACE1_CONNECTED,0);
usbhost_vtrace1(OTGHS_VTRACE1_CONNECTED, 0);
priv->connected = true;
priv->change = true;
DEBUGASSERT(priv->smstate == SMSTATE_DETACHED);
@ -2869,15 +2868,15 @@ static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv)
{
/* Yes.. then we no longer connected */
usbhost_vtrace1(OTGHS_VTRACE1_DISCONNECTED,0);
usbhost_vtrace1(OTGHS_VTRACE1_DISCONNECTED, 0);
/* Are we bound to a class driver? */
if ( priv->rhport.hport.devclass)
if (priv->rhport.hport.devclass)
{
/* Yes.. Disconnect the class driver */
CLASS_DISCONNECTED( priv->rhport.hport.devclass);
CLASS_DISCONNECTED(priv->rhport.hport.devclass);
priv->rhport.hport.devclass = NULL;
}
@ -2890,9 +2889,9 @@ static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv)
priv->rhport.hport.speed = USB_SPEED_FULL;
/* Notify any waiters that there is a change in the connection state */
/* Notify any waiters that there is a change in the connection state */
if (priv->pscwait)
if (priv->pscwait)
{
stm32_givesem(&priv->pscsem);
priv->pscwait = false;
@ -3450,7 +3449,7 @@ static int stm32_gint_isr(int irq, FAR void *context)
* little interrupt handling overhead.
*/
for (;;)
for (; ; )
{
/* Get the unmasked bits in the GINT status */
@ -3741,7 +3740,7 @@ static int stm32_wait(FAR struct usbhost_connection_s *conn,
/* Loop until a change in connection state is detected */
flags = irqsave();
for (;;)
for (; ; )
{
/* Is there a change in the connection state of the single root hub
* port?
@ -3835,7 +3834,7 @@ static int stm32_rh_enumerate(FAR struct stm32_usbhost_s *priv,
{
/* No, return an error */
usbhost_trace1(OTGHS_TRACE1_DEVDISCONN,0);
usbhost_trace1(OTGHS_TRACE1_DEVDISCONN, 0);
return -ENODEV;
}
@ -4333,7 +4332,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
ret = stm32_ctrl_sendsetup(priv, ep0info, req);
if (ret < 0)
{
{
usbhost_trace1(OTGHS_TRACE1_SENDSETUP, -ret);
continue;
}
@ -4805,7 +4804,8 @@ static void stm32_portreset(FAR struct stm32_usbhost_s *priv)
uint32_t regval;
regval = stm32_getreg(STM32_OTGHS_HPRT);
regval &= ~(OTGHS_HPRT_PENA|OTGHS_HPRT_PCDET|OTGHS_HPRT_PENCHNG|OTGHS_HPRT_POCCHNG);
regval &= ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | OTGHS_HPRT_PENCHNG |
OTGHS_HPRT_POCCHNG);
regval |= OTGHS_HPRT_PRST;
stm32_putreg(STM32_OTGHS_HPRT, regval);
@ -4922,7 +4922,8 @@ static void stm32_vbusdrive(FAR struct stm32_usbhost_s *priv, bool state)
/* Turn on the Host port power. */
regval = stm32_getreg(STM32_OTGHS_HPRT);
regval &= ~(OTGHS_HPRT_PENA|OTGHS_HPRT_PCDET|OTGHS_HPRT_PENCHNG|OTGHS_HPRT_POCCHNG);
regval &= ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | OTGHS_HPRT_PENCHNG |
OTGHS_HPRT_POCCHNG);
if (((regval & OTGHS_HPRT_PPWR) == 0) && state)
{
@ -5132,7 +5133,7 @@ static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv)
* transceiver: "This bit is always 1 with write-only access"
*/
regval = stm32_getreg(STM32_OTGHS_GUSBCFG);;
regval = stm32_getreg(STM32_OTGHS_GUSBCFG);
regval |= OTGHS_GUSBCFG_PHYSEL;
stm32_putreg(STM32_OTGHS_GUSBCFG, regval);

2
arch/arm/src/stm32/stm32_procfs_ccm.c
View File

@ -306,7 +306,7 @@ static int ccm_stat(const char *relpath, struct stat *buf)
return -ENOENT;
}
buf->st_mode = S_IFREG|S_IROTH|S_IRGRP|S_IRUSR;
buf->st_mode = S_IFREG | S_IROTH | S_IRGRP | S_IRUSR;
buf->st_size = 0;
buf->st_blksize = 0;
buf->st_blocks = 0;

6
arch/arm/src/stm32/stm32_pwm.c
View File

@ -1308,13 +1308,13 @@ static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
/* Then put the GPIO pin back to the default state */
pincfg = priv->pincfg & (GPIO_PORT_MASK|GPIO_PIN_MASK);
pincfg = priv->pincfg & (GPIO_PORT_MASK | GPIO_PIN_MASK);
#if defined(CONFIG_STM32_STM32F10XX)
pincfg |= (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT);
pincfg |= (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT);
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \
defined(CONFIG_STM32_STM32L15XX)
pincfg |= (GPIO_INPUT|GPIO_FLOAT);
pincfg |= (GPIO_INPUT | GPIO_FLOAT);
#else
# error "Unrecognized STM32 chip"
#endif

26
arch/arm/src/stm32/stm32_qencoder.c
View File

@ -770,11 +770,11 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower)
#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE)
if (priv->config->timid == 1 || priv->config->timid == 8)
{
/* Clear the Repetition Counter value */
{
/* Clear the Repetition Counter value */
stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0);
}
stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0);
}
#endif
/* Generate an update event to reload the Prescaler
@ -807,7 +807,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower)
/* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */
ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK|GTIM_CCMR1_IC1F_MASK);
ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK);
ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT;
ccmr1 |= GTIM_CCMR_ICF_FDTSd46 << GTIM_CCMR1_IC1F_SHIFT;
@ -842,7 +842,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower)
/* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */
ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK|GTIM_CCMR1_IC2F_MASK);
ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK);
ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT;
ccmr1 |= GTIM_CCMR_ICF_FDTSd46 << GTIM_CCMR1_IC2F_SHIFT;
@ -1031,12 +1031,12 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
/* Put the TI1 GPIO pin back to its default state */
pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK|GPIO_PIN_MASK);
pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK);
#if defined(CONFIG_STM32_STM32F10XX)
pincfg |= (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT);
pincfg |= (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT);
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
pincfg |= (GPIO_INPUT|GPIO_FLOAT);
pincfg |= (GPIO_INPUT | GPIO_FLOAT);
#else
# error "Unrecognized STM32 chip"
#endif
@ -1045,12 +1045,12 @@ static int stm32_shutdown(FAR struct qe_lowerhalf_s *lower)
/* Put the TI2 GPIO pin back to its default state */
pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK|GPIO_PIN_MASK);
pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK);
#if defined(CONFIG_STM32_STM32F10XX)
pincfg |= (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT);
pincfg |= (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT);
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
pincfg |= (GPIO_INPUT|GPIO_FLOAT);
pincfg |= (GPIO_INPUT | GPIO_FLOAT);
#else
# error "Unrecognized STM32 chip"
#endif
@ -1099,7 +1099,7 @@ static int stm32_position(FAR struct qe_lowerhalf_s *lower, int32_t *pos)
#else
/* Return the counter value */
*pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET);;
*pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET);
#endif
return OK;
}

4
arch/arm/src/stm32/stm32_rng.c
View File

@ -90,7 +90,7 @@ static const struct file_operations g_rngops =
0, /* seek */
0 /* ioctl */
#ifndef CONFIG_DISABLE_POLL
,0 /* poll */
, 0 /* poll */
#endif
};
@ -193,7 +193,7 @@ static int stm32_interrupt(int irq, void *context)
if (g_rngdev.rd_buflen >= 4)
{
g_rngdev.rd_buflen -= 4;
*(uint32_t*)&g_rngdev.rd_buf[g_rngdev.rd_buflen] = data;
*(uint32_t *)&g_rngdev.rd_buf[g_rngdev.rd_buflen] = data;
}
else
{

34
arch/arm/src/stm32/stm32_rtcc.c
View File

@ -557,7 +557,7 @@ static void rtc_resume(void)
/* Clear the RTC alarm flags */
regval = getreg32(STM32_RTC_ISR);
regval &= ~(RTC_ISR_ALRAF|RTC_ISR_ALRBF);
regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF);
putreg32(regval, STM32_RTC_ISR);
/* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */
@ -688,27 +688,27 @@ int up_rtcinitialize(void)
modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
#if defined(CONFIG_RTC_HSECLOCK)
/* Change to the new clock as the input to the RTC block */
/* Change to the new clock as the input to the RTC block */
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
#elif defined(CONFIG_RTC_LSICLOCK)
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
#elif defined(CONFIG_RTC_LSECLOCK)
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
#endif
putreg32(tr_bkp,STM32_RTC_TR);
putreg32(dr_bkp,STM32_RTC_DR);
putreg32(tr_bkp, STM32_RTC_TR);
putreg32(dr_bkp, STM32_RTC_DR);
/* Remember that the RTC is initialized */
/* Remember that the RTC is initialized */
putreg32(RTC_MAGIC, RTC_MAGIC_REG);
putreg32(RTC_MAGIC, RTC_MAGIC_REG);
/* Enable the RTC Clock by setting the RTCEN bit in the RCC register */
/* Enable the RTC Clock by setting the RTCEN bit in the RCC register */
modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN);
modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN);
}
}
@ -874,13 +874,13 @@ int up_rtc_getdatetime(FAR struct tm *tp)
* register.
*/
tmp = (tr & (RTC_TR_SU_MASK|RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT;
tmp = (tr & (RTC_TR_SU_MASK | RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT;
tp->tm_sec = rtc_bcd2bin(tmp);
tmp = (tr & (RTC_TR_MNU_MASK|RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT;
tmp = (tr & (RTC_TR_MNU_MASK | RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT;
tp->tm_min = rtc_bcd2bin(tmp);
tmp = (tr & (RTC_TR_HU_MASK|RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT;
tmp = (tr & (RTC_TR_HU_MASK | RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT;
tp->tm_hour = rtc_bcd2bin(tmp);
/* Now convert the RTC date to fields in struct tm format:
@ -893,13 +893,13 @@ int up_rtc_getdatetime(FAR struct tm *tp)
* years 2000-2099? I'll assume so.
*/
tmp = (dr & (RTC_DR_DU_MASK|RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT;
tmp = (dr & (RTC_DR_DU_MASK | RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT;
tp->tm_mday = rtc_bcd2bin(tmp);
tmp = (dr & (RTC_DR_MU_MASK|RTC_DR_MT)) >> RTC_DR_MU_SHIFT;
tmp = (dr & (RTC_DR_MU_MASK | RTC_DR_MT)) >> RTC_DR_MU_SHIFT;
tp->tm_mon = rtc_bcd2bin(tmp) - 1;
tmp = (dr & (RTC_DR_YU_MASK|RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT;
tmp = (dr & (RTC_DR_YU_MASK | RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT;
tp->tm_year = rtc_bcd2bin(tmp) + 100;
#if defined(CONFIG_TIME_EXTENDED)

261
arch/arm/src/stm32/stm32_sdio.c
View File

@ -153,13 +153,13 @@
* SDIO_MMCXFR_CLKDIV, and SDIO_SDXFR_CLKDIV.
*/
#define STM32_CLCKCR_INIT (SDIO_INIT_CLKDIV|SDIO_CLKCR_RISINGEDGE|\
#define STM32_CLCKCR_INIT (SDIO_INIT_CLKDIV | SDIO_CLKCR_RISINGEDGE | \
SDIO_CLKCR_WIDBUS_D1)
#define SDIO_CLKCR_MMCXFR (SDIO_MMCXFR_CLKDIV|SDIO_CLKCR_RISINGEDGE|\
#define SDIO_CLKCR_MMCXFR (SDIO_MMCXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \
SDIO_CLKCR_WIDBUS_D1)
#define SDIO_CLCKR_SDXFR (SDIO_SDXFR_CLKDIV|SDIO_CLKCR_RISINGEDGE|\
#define SDIO_CLCKR_SDXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \
SDIO_CLKCR_WIDBUS_D1)
#define SDIO_CLCKR_SDWIDEXFR (SDIO_SDXFR_CLKDIV|SDIO_CLKCR_RISINGEDGE|\
#define SDIO_CLCKR_SDWIDEXFR (SDIO_SDXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \
SDIO_CLKCR_WIDBUS_D4)
/* Timing */
@ -183,21 +183,21 @@
/* STM32 F1 channel configuration register (CCR) settings */
#if defined(CONFIG_STM32_STM32F10XX)
# define SDIO_RXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC)
# define SDIO_TXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR)
# define SDIO_RXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO | DMA_CCR_MSIZE_32BITS | \
DMA_CCR_PSIZE_32BITS | DMA_CCR_MINC)
# define SDIO_TXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO | DMA_CCR_MSIZE_32BITS | \
DMA_CCR_PSIZE_32BITS | DMA_CCR_MINC | DMA_CCR_DIR)
/* STM32 F4 stream configuration register (SCR) settings. */
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_P2M|DMA_SCR_MINC|\
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_32BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
# define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
CONFIG_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \
DMA_SCR_MBURST_INCR4)
# define SDIO_TXDMA32_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_M2P|DMA_SCR_MINC|\
DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_32BITS|\
CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
# define SDIO_TXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \
DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \
CONFIG_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \
DMA_SCR_MBURST_INCR4)
#else
# error "Unknown STM32 DMA"
@ -223,41 +223,41 @@
/* Data transfer interrupt mask bits */
#define SDIO_RECV_MASK (SDIO_MASK_DCRCFAILIE|SDIO_MASK_DTIMEOUTIE|\
SDIO_MASK_DATAENDIE|SDIO_MASK_RXOVERRIE|\
SDIO_MASK_RXFIFOHFIE|SDIO_MASK_STBITERRIE)
#define SDIO_SEND_MASK (SDIO_MASK_DCRCFAILIE|SDIO_MASK_DTIMEOUTIE|\
SDIO_MASK_DATAENDIE|SDIO_MASK_TXUNDERRIE|\
SDIO_MASK_TXFIFOHEIE|SDIO_MASK_STBITERRIE)
#define SDIO_DMARECV_MASK (SDIO_MASK_DCRCFAILIE|SDIO_MASK_DTIMEOUTIE|\
SDIO_MASK_DATAENDIE|SDIO_MASK_RXOVERRIE|\
#define SDIO_RECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \
SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \
SDIO_MASK_RXFIFOHFIE | SDIO_MASK_STBITERRIE)
#define SDIO_SEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \
SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \
SDIO_MASK_TXFIFOHEIE | SDIO_MASK_STBITERRIE)
#define SDIO_DMARECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \
SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \
SDIO_MASK_STBITERRIE)
#define SDIO_DMASEND_MASK (SDIO_MASK_DCRCFAILIE|SDIO_MASK_DTIMEOUTIE|\
SDIO_MASK_DATAENDIE|SDIO_MASK_TXUNDERRIE|\
#define SDIO_DMASEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \
SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \
SDIO_MASK_STBITERRIE)
/* Event waiting interrupt mask bits */
#define SDIO_CMDDONE_STA (SDIO_STA_CMDSENT)
#define SDIO_RESPDONE_STA (SDIO_STA_CTIMEOUT|SDIO_STA_CCRCFAIL|\
#define SDIO_RESPDONE_STA (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL | \
SDIO_STA_CMDREND)
#define SDIO_XFRDONE_STA (0)
#define SDIO_CMDDONE_MASK (SDIO_MASK_CMDSENTIE)
#define SDIO_RESPDONE_MASK (SDIO_MASK_CCRCFAILIE|SDIO_MASK_CTIMEOUTIE|\
#define SDIO_RESPDONE_MASK (SDIO_MASK_CCRCFAILIE | SDIO_MASK_CTIMEOUTIE | \
SDIO_MASK_CMDRENDIE)
#define SDIO_XFRDONE_MASK (0)
#define SDIO_CMDDONE_ICR (SDIO_ICR_CMDSENTC|SDIO_ICR_DBCKENDC)
#define SDIO_RESPDONE_ICR (SDIO_ICR_CTIMEOUTC|SDIO_ICR_CCRCFAILC|\
SDIO_ICR_CMDRENDC|SDIO_ICR_DBCKENDC)
#define SDIO_XFRDONE_ICR (SDIO_ICR_DATAENDC|SDIO_ICR_DCRCFAILC|\
SDIO_ICR_DTIMEOUTC|SDIO_ICR_RXOVERRC|\
SDIO_ICR_TXUNDERRC|SDIO_ICR_STBITERRC|\
#define SDIO_CMDDONE_ICR (SDIO_ICR_CMDSENTC | SDIO_ICR_DBCKENDC)
#define SDIO_RESPDONE_ICR (SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC | \
SDIO_ICR_CMDRENDC | SDIO_ICR_DBCKENDC)
#define SDIO_XFRDONE_ICR (SDIO_ICR_DATAENDC | SDIO_ICR_DCRCFAILC | \
SDIO_ICR_DTIMEOUTC | SDIO_ICR_RXOVERRC | \
SDIO_ICR_TXUNDERRC | SDIO_ICR_STBITERRC | \
SDIO_ICR_DBCKENDC)
#define SDIO_WAITALL_ICR (SDIO_CMDDONE_ICR|SDIO_RESPDONE_ICR|\
SDIO_XFRDONE_ICR|SDIO_ICR_DBCKENDC)
#define SDIO_WAITALL_ICR (SDIO_CMDDONE_ICR | SDIO_RESPDONE_ICR | \
SDIO_XFRDONE_ICR | SDIO_ICR_DBCKENDC)
/* Let's wait until we have both SDIO transfer complete and DMA complete. */
@ -583,14 +583,14 @@ static inline void stm32_setclkcr(uint32_t clkcr)
/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
regval &= ~(SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS|
SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN|
regval &= ~(SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | SDIO_CLKCR_BYPASS |
SDIO_CLKCR_WIDBUS_MASK | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN |
SDIO_CLKCR_CLKEN);
/* Replace with user provided settings */
clkcr &= (SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS|
SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN|
clkcr &= (SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | SDIO_CLKCR_BYPASS |
SDIO_CLKCR_WIDBUS_MASK | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN |
SDIO_CLKCR_CLKEN);
regval |= clkcr;
@ -638,8 +638,8 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
waitmask &= !SDIOWAIT_WRCOMPLETE;
pinset = GPIO_SDIO_D0 & (GPIO_PORT_MASK|GPIO_PIN_MASK);
pinset |= (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI);
pinset = GPIO_SDIO_D0 & (GPIO_PORT_MASK | GPIO_PIN_MASK);
pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI);
/* Arm the SDIO_D Ready and install Isr */
@ -895,7 +895,7 @@ static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg)
* Transfer.
*/
stm32_sample((struct stm32_dev_s*)arg, SAMPLENDX_DMA_CALLBACK);
stm32_sample((struct stm32_dev_s *)arg, SAMPLENDX_DMA_CALLBACK);
/* Get the result of the DMA transfer */
@ -950,10 +950,11 @@ static uint8_t stm32_log2(uint16_t value)
DEBUGASSERT(value > 0);
while (value != 1)
{
value >>= 1;
log2++;
}
{
value >>= 1;
log2++;
}
return log2;
}
@ -979,9 +980,9 @@ static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
*/
regval = getreg32(STM32_SDIO_DCTRL);
regval &= ~(SDIO_DCTRL_DTDIR|SDIO_DCTRL_DTMODE|SDIO_DCTRL_DBLOCKSIZE_MASK);
dctrl &= (SDIO_DCTRL_DTDIR|SDIO_DCTRL_DTMODE|SDIO_DCTRL_DBLOCKSIZE_MASK);
regval |= (dctrl|SDIO_DCTRL_DTEN);
regval &= ~(SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK);
dctrl &= (SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK);
regval |= (dctrl | SDIO_DCTRL_DTEN);
putreg32(regval, STM32_SDIO_DCTRL);
}
@ -1006,8 +1007,8 @@ static void stm32_datadisable(void)
/* Reset DCTRL DTEN, DTDIR, DTMODE, DMAEN, and DBLOCKSIZE fields */
regval = getreg32(STM32_SDIO_DCTRL);
regval &= ~(SDIO_DCTRL_DTEN|SDIO_DCTRL_DTDIR|SDIO_DCTRL_DTMODE|
SDIO_DCTRL_DMAEN|SDIO_DCTRL_DBLOCKSIZE_MASK);
regval &= ~(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE |
SDIO_DCTRL_DMAEN | SDIO_DCTRL_DBLOCKSIZE_MASK);
putreg32(regval, STM32_SDIO_DCTRL);
}
@ -1049,27 +1050,27 @@ static void stm32_sendfifo(struct stm32_dev_s *priv)
}
else
{
/* No.. transfer just the bytes remaining in the user buffer,
* padding with zero as necessary to extend to a full word.
*/
/* No.. transfer just the bytes remaining in the user buffer,
* padding with zero as necessary to extend to a full word.
*/
uint8_t *ptr = (uint8_t *)priv->remaining;
int i;
uint8_t *ptr = (uint8_t *)priv->remaining;
int i;
data.w = 0;
for (i = 0; i < (int)priv->remaining; i++)
{
data.b[i] = *ptr++;
}
data.w = 0;
for (i = 0; i < (int)priv->remaining; i++)
{
data.b[i] = *ptr++;
}
/* Now the transfer is finished */
/* Now the transfer is finished */
priv->remaining = 0;
}
priv->remaining = 0;
}
/* Put the word in the FIFO */
/* Put the word in the FIFO */
putreg32(data.w, STM32_SDIO_FIFO);
putreg32(data.w, STM32_SDIO_FIFO);
}
}
@ -1116,7 +1117,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv)
{
/* Transfer any trailing fractional word */
uint8_t *ptr = (uint8_t*)priv->buffer;
uint8_t *ptr = (uint8_t *)priv->buffer;
int i;
for (i = 0; i < (int)priv->remaining; i++)
@ -1328,30 +1329,30 @@ static int stm32_interrupt(int irq, void *context)
#ifdef CONFIG_SDIO_DMA
if (!priv->dmamode)
#endif
{
/* Is the RX FIFO half full or more? Is so then we must be
* processing a receive transaction.
*/
if ((pending & SDIO_STA_RXFIFOHF) != 0)
{
/* Receive data from the RX FIFO */
stm32_recvfifo(priv);
}
/* Otherwise, Is the transmit FIFO half empty or less? If so we must
* be processing a send transaction. NOTE: We can't be processing
* both!
{
/* Is the RX FIFO half full or more? Is so then we must be
* processing a receive transaction.
*/
else if ((pending & SDIO_STA_TXFIFOHE) != 0)
{
/* Send data via the TX FIFO */
if ((pending & SDIO_STA_RXFIFOHF) != 0)
{
/* Receive data from the RX FIFO */
stm32_sendfifo(priv);
}
}
stm32_recvfifo(priv);
}
/* Otherwise, Is the transmit FIFO half empty or less? If so we must
* be processing a send transaction. NOTE: We can't be processing
* both!
*/
else if ((pending & SDIO_STA_TXFIFOHE) != 0)
{
/* Send data via the TX FIFO */
stm32_sendfifo(priv);
}
}
/* Handle data end events */
@ -1406,7 +1407,7 @@ static int stm32_interrupt(int irq, void *context)
/* Terminate the transfer with an error */
flldbg("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
/* Handle data timeout error */
@ -1416,7 +1417,7 @@ static int stm32_interrupt(int irq, void *context)
/* Terminate the transfer with an error */
flldbg("ERROR: Data timeout, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_TIMEOUT);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT);
}
/* Handle RX FIFO overrun error */
@ -1426,7 +1427,7 @@ static int stm32_interrupt(int irq, void *context)
/* Terminate the transfer with an error */
flldbg("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
/* Handle TX FIFO underrun error */
@ -1436,7 +1437,7 @@ static int stm32_interrupt(int irq, void *context)
/* Terminate the transfer with an error */
flldbg("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
/* Handle start bit error */
@ -1446,8 +1447,8 @@ static int stm32_interrupt(int irq, void *context)
/* Terminate the transfer with an error */
flldbg("ERROR: Start bit, remaining: %d\n", priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE|SDIOWAIT_ERROR);
}
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
}
/* Handle wait events *************************************************/
@ -1465,7 +1466,7 @@ static int stm32_interrupt(int irq, void *context)
{
/* Yes.. wake the thread up */
putreg32(SDIO_RESPDONE_ICR|SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
stm32_endwait(priv, SDIOWAIT_RESPONSEDONE);
}
}
@ -1763,8 +1764,8 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, and CPSMEN bits */
regval = getreg32(STM32_SDIO_CMD);
regval &= ~(SDIO_CMD_CMDINDEX_MASK|SDIO_CMD_WAITRESP_MASK|
SDIO_CMD_WAITINT|SDIO_CMD_WAITPEND|SDIO_CMD_CPSMEN);
regval &= ~(SDIO_CMD_CMDINDEX_MASK | SDIO_CMD_WAITRESP_MASK |
SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND | SDIO_CMD_CPSMEN);
/* Set WAITRESP bits */
@ -1798,7 +1799,7 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
/* Write the SDIO CMD */
putreg32(SDIO_RESPDONE_ICR|SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
putreg32(regval, STM32_SDIO_CMD);
return OK;
}
@ -1841,7 +1842,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
/* Save the destination buffer information for use by the interrupt handler */
priv->buffer = (uint32_t*)buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
#ifdef CONFIG_SDIO_DMA
priv->dmamode = false;
@ -1850,7 +1851,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
/* Then set up the SDIO data path */
dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize|SDIO_DCTRL_DTDIR);
stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize | SDIO_DCTRL_DTDIR);
/* And enable interrupts */
@ -1895,7 +1896,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t*)buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
#ifdef CONFIG_SDIO_DMA
priv->dmamode = false;
@ -1932,7 +1933,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer
static int stm32_cancel(FAR struct sdio_dev_s *dev)
{
struct stm32_dev_s *priv = (struct stm32_dev_s*)dev;
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
/* Disable all transfer- and event- related interrupts */
@ -2137,7 +2138,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
/* Clear all pending message completion events and return the R1/R6 response */
putreg32(SDIO_RESPDONE_ICR|SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
*rshort = getreg32(STM32_SDIO_RESP1);
return ret;
}
@ -2184,7 +2185,7 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo
/* Return the long response */
putreg32(SDIO_RESPDONE_ICR|SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
if (rlong)
{
rlong[0] = getreg32(STM32_SDIO_RESP1);
@ -2200,14 +2201,14 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
uint32_t regval;
int ret = OK;
/* R3 OCR (48-bit)
* 47 0 Start bit
* 46 0 Transmission bit (0=from card)
* 45:40 bit5 - bit0 Reserved
* 39:8 bit31 - bit0 32-bit OCR register
* 7:1 bit6 - bit0 Reserved
* 0 1 End bit
*/
/* R3 OCR (48-bit)
* 47 0 Start bit
* 46 0 Transmission bit (0=from card)
* 45:40 bit5 - bit0 Reserved
* 39:8 bit31 - bit0 32-bit OCR register
* 7:1 bit6 - bit0 Reserved
* 0 1 End bit
*/
/* Check that this is the correct response to this command */
@ -2233,7 +2234,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
}
}
putreg32(SDIO_RESPDONE_ICR|SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
if (rshort)
{
*rshort = getreg32(STM32_SDIO_RESP1);
@ -2245,7 +2246,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r
static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl)
{
putreg32(SDIO_RESPDONE_ICR|SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDIO_ICR);
return -ENOSYS;
}
@ -2276,7 +2277,7 @@ static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t
static void stm32_waitenable(FAR struct sdio_dev_s *dev,
sdio_eventset_t eventset)
{
struct stm32_dev_s *priv = (struct stm32_dev_s*)dev;
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
uint32_t waitmask;
DEBUGASSERT(priv != NULL);
@ -2316,7 +2317,7 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev,
/* Enable event-related interrupts */
putreg32(SDIO_WAITALL_ICR, STM32_SDIO_ICR);
}
}
stm32_configwaitints(priv, waitmask, eventset, 0);
}
@ -2345,7 +2346,7 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev,
static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
uint32_t timeout)
{
struct stm32_dev_s *priv = (struct stm32_dev_s*)dev;
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
sdio_eventset_t wkupevent = 0;
irqstate_t flags;
int ret;
@ -2370,10 +2371,10 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
if (!timeout)
{
/* Then just tell the caller that we already timed out */
/* Then just tell the caller that we already timed out */
wkupevent = SDIOWAIT_TIMEOUT;
goto errout;
wkupevent = SDIOWAIT_TIMEOUT;
goto errout;
}
/* Start the watchdog timer */
@ -2383,8 +2384,8 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
1, (uint32_t)priv);
if (ret != OK)
{
fdbg("ERROR: wd_start failed: %d\n", ret);
}
fdbg("ERROR: wd_start failed: %d\n", ret);
}
}
#if defined(CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE)
@ -2408,7 +2409,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
* may have already occurred before this function was called!
*/
for (;;)
for (; ; )
{
/* Wait for an event in event set to occur. If this the event has already
* occurred, then the semaphore will already have been incremented and
@ -2468,7 +2469,7 @@ errout:
static void stm32_callbackenable(FAR struct sdio_dev_s *dev,
sdio_eventset_t eventset)
{
struct stm32_dev_s *priv = (struct stm32_dev_s*)dev;
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
fvdbg("eventset: %02x\n", eventset);
DEBUGASSERT(priv != NULL);
@ -2502,7 +2503,7 @@ static void stm32_callbackenable(FAR struct sdio_dev_s *dev,
static int stm32_registercallback(FAR struct sdio_dev_s *dev,
worker_t callback, void *arg)
{
struct stm32_dev_s *priv = (struct stm32_dev_s*)dev;
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
/* Disable callbacks and register this callback and is argument */
@ -2620,14 +2621,14 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
/* Save the destination buffer information for use by the interrupt handler */
priv->buffer = (uint32_t*)buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = buflen;
priv->dmamode = true;
/* Then set up the SDIO data path */
dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize|SDIO_DCTRL_DTDIR);
stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize | SDIO_DCTRL_DTDIR);
/* Configure the RX DMA */
@ -2689,7 +2690,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t*)buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = buflen;
priv->dmamode = true;
@ -2737,7 +2738,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
static void stm32_callback(void *arg)
{
struct stm32_dev_s *priv = (struct stm32_dev_s*)arg;
struct stm32_dev_s *priv = (struct stm32_dev_s *)arg;
/* Is a callback registered? */
@ -2754,8 +2755,8 @@ static void stm32_callback(void *arg)
/* Media is present. Is the media inserted event enabled? */
if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0)
{
/* No... return without performing the callback */
{
/* No... return without performing the callback */
return;
}

90
arch/arm/src/stm32/stm32_serial.c
View File

@ -311,7 +311,7 @@ struct up_dev_s
const unsigned int rxdma_channel; /* DMA channel assigned */
#endif
int (* const vector)(int irq, void *context); /* Interrupt handler */
int (*const vector)(int irq, void *context); /* Interrupt handler */
/* RX DMA state */
@ -1197,31 +1197,31 @@ static void up_set_format(struct uart_dev_s *dev)
* = 2 * usartdiv8
*/
/* Use oversamply by 8 only if the divisor is small. But what is small? */
/* Use oversamply by 8 only if the divisor is small. But what is small? */
cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
if (usartdiv8 > 100)
{
/* Use usartdiv16 */
cr1 = up_serialin(priv, STM32_USART_CR1_OFFSET);
if (usartdiv8 > 100)
{
/* Use usartdiv16 */
brr = (usartdiv8 + 1) >> 1;
brr = (usartdiv8 + 1) >> 1;
/* Clear oversampling by 8 to enable oversampling by 16 */
/* Clear oversampling by 8 to enable oversampling by 16 */
cr1 &= ~USART_CR1_OVER8;
}
else
{
DEBUGASSERT(usartdiv8 >= 8);
cr1 &= ~USART_CR1_OVER8;
}
else
{
DEBUGASSERT(usartdiv8 >= 8);
/* Perform mysterious operations on bits 0-3 */
/* Perform mysterious operations on bits 0-3 */
brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1));
brr = ((usartdiv8 & 0xfff0) | ((usartdiv8 & 0x000f) >> 1));
/* Set oversampling by 8 */
/* Set oversampling by 8 */
cr1 |= USART_CR1_OVER8;
}
cr1 |= USART_CR1_OVER8;
}
up_serialout(priv, STM32_USART_CR1_OFFSET, cr1);
up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
@ -1255,16 +1255,16 @@ static void up_set_format(struct uart_dev_s *dev)
usartdiv32 = priv->apbclock / (priv->baud >> 1);
/* The mantissa part is then */
/* The mantissa part is then */
mantissa = usartdiv32 >> 5;
brr = mantissa << USART_BRR_MANT_SHIFT;
mantissa = usartdiv32 >> 5;
brr = mantissa << USART_BRR_MANT_SHIFT;
/* The fractional remainder (with rounding) */
/* The fractional remainder (with rounding) */
fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1;
brr |= fraction << USART_BRR_FRAC_SHIFT;
up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
fraction = (usartdiv32 - (mantissa << 5) + 1) >> 1;
brr |= fraction << USART_BRR_FRAC_SHIFT;
up_serialout(priv, STM32_USART_BRR_OFFSET, brr);
#endif
/* Configure parity mode */
@ -1313,7 +1313,7 @@ static void up_set_format(struct uart_dev_s *dev)
/* Configure hardware flow control */
regval = up_serialin(priv, STM32_USART_CR3_OFFSET);
regval &= ~(USART_CR3_CTSE|USART_CR3_RTSE);
regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE);
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN)
if (priv->iflow && (priv->rts_gpio != 0))
@ -1466,7 +1466,7 @@ static int up_setup(struct uart_dev_s *dev)
config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT;
#endif
stm32_configgpio(config);
}
}
#endif
#ifdef HAVE_RS485
@ -1733,11 +1733,11 @@ static int up_attach(struct uart_dev_s *dev)
ret = irq_attach(priv->irq, priv->vector);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the USART
*/
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the USART
*/
up_enable_irq(priv->irq);
up_enable_irq(priv->irq);
}
return ret;
}
@ -1836,17 +1836,17 @@ static int up_interrupt_common(struct up_dev_s *priv)
if ((priv->sr & USART_SR_RXNE) != 0 && (priv->ie & USART_CR1_RXNEIE) != 0)
{
/* Received data ready... process incoming bytes. NOTE the check for
* RXNEIE: We cannot call uart_recvchards of RX interrupts are disabled.
*/
/* Received data ready... process incoming bytes. NOTE the check for
* RXNEIE: We cannot call uart_recvchards of RX interrupts are disabled.
*/
uart_recvchars(&priv->dev);
handled = true;
uart_recvchars(&priv->dev);
handled = true;
}
/* We may still have to read from the DR register to clear any pending
* error conditions.
*/
/* We may still have to read from the DR register to clear any pending
* error conditions.
*/
else if ((priv->sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0)
{
@ -1874,10 +1874,10 @@ static int up_interrupt_common(struct up_dev_s *priv)
if ((priv->sr & USART_SR_TXE) != 0 && (priv->ie & USART_CR1_TXEIE) != 0)
{
/* Transmit data register empty ... process outgoing bytes */
/* Transmit data register empty ... process outgoing bytes */
uart_xmitchars(&priv->dev);
handled = true;
uart_xmitchars(&priv->dev);
handled = true;
}
}
@ -1962,7 +1962,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef CONFIG_SERIAL_TERMIOS
case TCGETS:
{
struct termios *termiosp = (struct termios*)arg;
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
@ -1994,7 +1994,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
case TCSETS:
{
struct termios *termiosp = (struct termios*)arg;
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
@ -2215,7 +2215,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
static bool up_rxflowcontrol(struct uart_dev_s *dev,
unsigned int nbuffered, bool upper)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
#if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \
defined(CONFIG_STM32_FLOWCONTROL_BROKEN)

34
arch/arm/src/stm32/stm32_spi.c
View File

@ -804,7 +804,7 @@ static void spi_dmarxsetup(FAR struct stm32_spidev_s *priv, FAR void *rxbuffer,
rxbuffer = rxdummy;
priv->rxccr = SPI_RXDMA8NULL_CONFIG;
}
}
}
/* Configure the RX DMA */
@ -1016,7 +1016,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
setbits = SPI_CR1_FPCLCKd4; /* 001: fPCLK/4 */
actual = priv->spiclock >> 2;
}
}
else if (frequency >= priv->spiclock >> 3)
{
/* Between fPCLCK/4 and fPCLCK/8, pick the slower */
@ -1115,7 +1115,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
{
case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */
setbits = 0;
clrbits = SPI_CR1_CPOL|SPI_CR1_CPHA;
clrbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
break;
case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */
@ -1129,7 +1129,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
break;
case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */
setbits = SPI_CR1_CPOL|SPI_CR1_CPHA;
setbits = SPI_CR1_CPOL | SPI_CR1_CPHA;
clrbits = 0;
break;
@ -1189,11 +1189,11 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
case 8:
setbits = 0;
clrbits = SPI_CR1_DFF|SPI_CR1_LSBFIRST;
clrbits = SPI_CR1_DFF | SPI_CR1_LSBFIRST;
break;
case -16:
setbits = SPI_CR1_DFF|SPI_CR1_LSBFIRST;
setbits = SPI_CR1_DFF | SPI_CR1_LSBFIRST;
clrbits = 0;
break;
@ -1295,8 +1295,8 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t*)txbuffer;;
uint16_t *dest = (uint16_t*)rxbuffer;
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *)rxbuffer;
uint16_t word;
while (nwords-- > 0)
@ -1308,9 +1308,9 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
word = *src++;
}
else
{
{
word = 0xffff;
}
}
/* Exchange one word */
@ -1328,8 +1328,8 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t*)txbuffer;;
uint8_t *dest = (uint8_t*)rxbuffer;
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *)rxbuffer;
uint8_t word;
while (nwords-- > 0)
@ -1341,9 +1341,9 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
word = *src++;
}
else
{
{
word = 0xff;
}
}
/* Exchange one word */
@ -1503,9 +1503,9 @@ static void spi_portinitialize(FAR struct stm32_spidev_s *priv)
* Two lines full duplex: BIDIMODE=0 BIDIOIE=(Don't care) and RXONLY=0
*/
clrbits = SPI_CR1_CPHA|SPI_CR1_CPOL|SPI_CR1_BR_MASK|SPI_CR1_LSBFIRST|
SPI_CR1_RXONLY|SPI_CR1_DFF|SPI_CR1_BIDIOE|SPI_CR1_BIDIMODE;
setbits = SPI_CR1_MSTR|SPI_CR1_SSI|SPI_CR1_SSM;
clrbits = SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_BR_MASK | SPI_CR1_LSBFIRST |
SPI_CR1_RXONLY | SPI_CR1_DFF | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE;
setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM;
spi_modifycr1(priv, setbits, clrbits);
#ifndef CONFIG_SPI_OWNBUS

4
arch/arm/src/stm32/stm32_start.c
View File

@ -67,7 +67,7 @@ static inline void stm32_fpuconfig(void);
#endif
#ifdef CONFIG_STACK_COLORATION
static void go_os_start(void *pv, unsigned int nbytes)
__attribute__ ((naked,no_instrument_function,noreturn));
__attribute__ ((naked, no_instrument_function, noreturn));
#endif
/****************************************************************************
@ -322,6 +322,6 @@ void __start(void)
/* Shoulnd't get here */
for (;;);
for (; ; );
#endif
}

9
arch/arm/src/stm32/stm32_timerisr.c
View File

@ -108,10 +108,10 @@
int up_timerisr(int irq, uint32_t *regs)
{
/* Process timer interrupt */
/* Process timer interrupt */
sched_process_timer();
return 0;
sched_process_timer();
return 0;
}
/****************************************************************************
@ -156,7 +156,8 @@ void up_timer_initialize(void)
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */

44
arch/arm/src/stm32/stm32_usbdev.c
View File

@ -796,7 +796,7 @@ static void stm32_checksetup(void)
static inline void stm32_seteptxcount(uint8_t epno, uint16_t count)
{
volatile uint32_t *epaddr = (uint32_t*)STM32_USB_COUNT_TX(epno);
volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_TX(epno);
*epaddr = count;
}
@ -806,7 +806,7 @@ static inline void stm32_seteptxcount(uint8_t epno, uint16_t count)
static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr)
{
volatile uint32_t *txaddr = (uint32_t*)STM32_USB_ADDR_TX(epno);
volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno);
*txaddr = addr;
}
@ -816,7 +816,7 @@ static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr)
static inline uint16_t stm32_geteptxaddr(uint8_t epno)
{
volatile uint32_t *txaddr = (uint32_t*)STM32_USB_ADDR_TX(epno);
volatile uint32_t *txaddr = (uint32_t *)STM32_USB_ADDR_TX(epno);
return (uint16_t)*txaddr;
}
@ -826,7 +826,7 @@ static inline uint16_t stm32_geteptxaddr(uint8_t epno)
static void stm32_seteprxcount(uint8_t epno, uint16_t count)
{
volatile uint32_t *epaddr = (uint32_t*)STM32_USB_COUNT_RX(epno);
volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno);
uint32_t rxcount = 0;
uint16_t nblocks;
@ -873,7 +873,7 @@ static void stm32_seteprxcount(uint8_t epno, uint16_t count)
static inline uint16_t stm32_geteprxcount(uint8_t epno)
{
volatile uint32_t *epaddr = (uint32_t*)STM32_USB_COUNT_RX(epno);
volatile uint32_t *epaddr = (uint32_t *)STM32_USB_COUNT_RX(epno);
return (*epaddr) & USB_COUNT_RX_MASK;
}
@ -883,7 +883,7 @@ static inline uint16_t stm32_geteprxcount(uint8_t epno)
static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr)
{
volatile uint32_t *rxaddr = (uint32_t*)STM32_USB_ADDR_RX(epno);
volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno);
*rxaddr = addr;
}
@ -893,7 +893,7 @@ static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr)
static inline uint16_t stm32_geteprxaddr(uint8_t epno)
{
volatile uint32_t *rxaddr = (uint32_t*)STM32_USB_ADDR_RX(epno);
volatile uint32_t *rxaddr = (uint32_t *)STM32_USB_ADDR_RX(epno);
return (uint16_t)*rxaddr;
}
@ -1138,7 +1138,7 @@ static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes
/* Copy loop. Source=user buffer, Dest=packet memory */
dest = (uint16_t*)(STM32_USBRAM_BASE + ((uint32_t)pma << 1));
dest = (uint16_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1));
for (i = nwords; i != 0; i--)
{
/* Read two bytes and pack into on 16-bit word */
@ -1168,12 +1168,12 @@ stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes)
/* Copy loop. Source=packet memory, Dest=user buffer */
src = (uint32_t*)(STM32_USBRAM_BASE + ((uint32_t)pma << 1));
src = (uint32_t *)(STM32_USBRAM_BASE + ((uint32_t)pma << 1));
for (i = nwords; i != 0; i--)
{
/* Copy 16-bits from packet memory to user buffer. */
*(uint16_t*)buffer = *src++;
*(uint16_t *)buffer = *src++;
/* Source address increments by 1*sizeof(uint32_t) = 4; Dest address
* increments by 2*sizeof(uint8_t) = 2.
@ -1709,7 +1709,7 @@ static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value)
/* Set the device address and enable function */
stm32_putreg(value|USB_DADDR_EF, STM32_USB_DADDR);
stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR);
}
/****************************************************************************
@ -1755,9 +1755,12 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv)
if (priv->ep0state != EP0STATE_SETUP_READY)
{
/* Not the data phase */
/* Get a 32-bit PMA address and use that to get the 8-byte setup request */
/* Get a 32-bit PMA address and use that to get the 8-byte setup
* request
*/
stm32_copyfrompma((uint8_t*)&priv->ctrl, stm32_geteprxaddr(EP0), USB_SIZEOF_CTRLREQ);
stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0),
USB_SIZEOF_CTRLREQ);
/* And extract the little-endian 16-bit values to host order */
@ -2506,7 +2509,7 @@ static int stm32_lpinterrupt(int irq, void *context)
* interrupts.
*/
stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM|USB_CNTR_WKUPM);
stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM);
stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR);
}
@ -2589,7 +2592,7 @@ static void stm32_suspend(struct stm32_usbdev_s *priv)
* interrupt. Clear any pending WKUP interrupt.
*/
stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM|USB_CNTR_SUSPM);
stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM);
stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR);
/* Set the FSUSP bit in the CNTR register. This activates suspend mode
@ -2698,7 +2701,7 @@ static void stm32_esofpoll(struct stm32_usbdev_s *priv)
* the WKUP interrupt. Clear any pending WKUP interrupt.
*/
stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM|USB_CNTR_SUSPM);
stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM);
stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR);
}
break;
@ -2994,7 +2997,7 @@ static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep)
static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req)
{
struct stm32_req_s *privreq = (struct stm32_req_s*)req;
struct stm32_req_s *privreq = (struct stm32_req_s *)req;
#ifdef CONFIG_DEBUG
if (!ep || !req)
@ -3454,7 +3457,7 @@ static int stm32_wakeup(struct usbdev_s *dev)
* pending ESOF interrupt.
*/
stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM|USB_CNTR_SUSPM);
stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM);
stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR);
irqrestore(flags);
return OK;
@ -3686,7 +3689,7 @@ static void stm32_hwshutdown(struct stm32_usbdev_s *priv)
/* Power down the USB controller */
stm32_putreg(USB_CNTR_FRES|USB_CNTR_PDWN, STM32_USB_CNTR);
stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR);
}
/****************************************************************************
@ -3881,7 +3884,8 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
stm32_usbpullup(&priv->usbdev, true);
priv->usbdev.speed = USB_SPEED_FULL;
}
}
return ret;
}

10
arch/arm/src/stm32/stm32_userspace.c
View File

@ -87,8 +87,8 @@ void stm32_userspace(void)
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
dest = (uint8_t*)USERSPACE->us_bssstart;
end = (uint8_t*)USERSPACE->us_bssend;
dest = (uint8_t *)USERSPACE->us_bssstart;
end = (uint8_t *)USERSPACE->us_bssend;
while (dest != end)
{
@ -101,9 +101,9 @@ void stm32_userspace(void)
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
USERSPACE->us_datastart <= USERSPACE->us_dataend);
src = (uint8_t*)USERSPACE->us_datasource;
dest = (uint8_t*)USERSPACE->us_datastart;
end = (uint8_t*)USERSPACE->us_dataend;
src = (uint8_t *)USERSPACE->us_datasource;
dest = (uint8_t *)USERSPACE->us_datastart;
end = (uint8_t *)USERSPACE->us_dataend;
while (dest != end)
{

29
arch/arm/src/stm32/stm32_wwdg.c
View File

@ -197,10 +197,11 @@ static uint16_t stm32_getreg(uint32_t addr)
{
if (count == 0xffffffff || ++count > 3)
{
if (count == 4)
{
lldbg("...\n");
}
if (count == 4)
{
lldbg("...\n");
}
return val;
}
}
@ -209,20 +210,20 @@ static uint16_t stm32_getreg(uint32_t addr)
else
{
/* Did we print "..." for the previous value? */
/* Did we print "..." for the previous value? */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
if (count > 3)
{
/* Yes.. then show how many times the value repeated */
lldbg("[repeats %d more times]\n", count-3);
}
lldbg("[repeats %d more times]\n", count-3);
}
/* Save the new address, value, and count */
/* Save the new address, value, and count */
prevaddr = addr;
preval = val;
count = 1;
prevaddr = addr;
preval = val;
count = 1;
}
/* Show the register value read */

12
arch/arm/src/stm32/stm32f10xxx_dma.c
View File

@ -502,10 +502,12 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
*/
regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
regval &= ~(DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
ccr &= (DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
DMA_CCR_DIR);
ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
DMA_CCR_DIR);
regval |= ccr;
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
}
@ -556,7 +558,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback,
* Interrupt Enable bit (TCIE) is set.
*/
ccr |= (half ? (DMA_CCR_HTIE|DMA_CCR_TEIE) : (DMA_CCR_TCIE|DMA_CCR_TEIE));
ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : (DMA_CCR_TCIE | DMA_CCR_TEIE));
}
else
{

124
arch/arm/src/stm32/stm32f10xxx_rcc.c
View File

@ -71,7 +71,7 @@ static inline void rcc_reset(void)
putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
putreg32(RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
@ -80,12 +80,12 @@ static inline void rcc_reset(void)
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
regval &= ~(RCC_CFGR_SW_MASK|RCC_CFGR_HPRE_MASK|RCC_CFGR_PPRE1_MASK|
RCC_CFGR_PPRE2_MASK|RCC_CFGR_ADCPRE_MASK|RCC_CFGR_MCO_MASK);
regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
RCC_CFGR_PPRE2_MASK | RCC_CFGR_ADCPRE_MASK | RCC_CFGR_MCO_MASK);
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */
regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */
@ -93,9 +93,9 @@ static inline void rcc_reset(void)
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK
#ifndef CONFIG_STM32_VALUELINE
|RCC_CFGR_USBPRE
| RCC_CFGR_USBPRE
#endif
);
putreg32(regval, STM32_RCC_CFGR);
@ -129,7 +129,7 @@ static inline void rcc_enableahb(void)
/* Always enable FLITF clock and SRAM clock */
regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN;
regval = RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN;
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
@ -403,25 +403,25 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
regval |= (RCC_APB2ENR_AFIOEN
#if STM32_NGPIO > 0
|RCC_APB2ENR_IOPAEN
| RCC_APB2ENR_IOPAEN
#endif
#if STM32_NGPIO > 16
|RCC_APB2ENR_IOPBEN
| RCC_APB2ENR_IOPBEN
#endif
#if STM32_NGPIO > 32
|RCC_APB2ENR_IOPCEN
| RCC_APB2ENR_IOPCEN
#endif
#if STM32_NGPIO > 48
|RCC_APB2ENR_IOPDEN
| RCC_APB2ENR_IOPDEN
#endif
#if STM32_NGPIO > 64
|RCC_APB2ENR_IOPEEN
| RCC_APB2ENR_IOPEEN
#endif
#if STM32_NGPIO > 80
|RCC_APB2ENR_IOPFEN
| RCC_APB2ENR_IOPFEN
#endif
#if STM32_NGPIO > 96
|RCC_APB2ENR_IOPGEN
| RCC_APB2ENR_IOPGEN
#endif
);
@ -531,7 +531,7 @@ static void stm32_stdclockconfig(void)
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set up PLL input scaling (with source = PLL2) */
@ -675,92 +675,92 @@ static void stm32_stdclockconfig(void)
# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
# endif
/* Set the HSE prescaler */
/* Set the HSE prescaler */
regval = STM32_CFGR2_PREDIV1;
putreg32(regval, STM32_RCC_CFGR2);
regval = STM32_CFGR2_PREDIV1;
putreg32(regval, STM32_RCC_CFGR2);
# endif
#endif
/* Value-line devices don't implement flash prefetch/waitstates */
/* Value-line devices don't implement flash prefetch/waitstates */
#ifndef CONFIG_STM32_VALUELINE
/* Enable FLASH prefetch buffer and 2 wait states */
/* Enable FLASH prefetch buffer and 2 wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
#endif
/* Set the HCLK source/divider */
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK2 divider */
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
/* If we are using the PLL, configure and start it */
/* If we are using the PLL, configure and start it */
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* Set the PLL divider and multiplier */
/* Set the PLL divider and multiplier */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC|STM32_CFGR_PLLXTPRE|STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
/* Enable the PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
#endif
/* Select the system clock source (probably the PLL) */
/* Select the system clock source (probably the PLL) */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until the selected source is used as the system clock source */
/* Wait until the selected source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();
stm32_rcc_enablelsi();
#endif
#if defined(CONFIG_RTC_LSECLOCK)
/* Low speed external clock source LSE */
/* Low speed external clock source LSE */
stm32_rcc_enablelse();
stm32_rcc_enablelse();
#endif
}
#endif

22
arch/arm/src/stm32/stm32f20xxx_dma.c
View File

@ -679,7 +679,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
*/
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
regval &= ~(DMA_SCR_PL_MASK|DMA_SCR_CHSEL_MASK);
regval &= ~(DMA_SCR_PL_MASK | DMA_SCR_CHSEL_MASK);
regval |= scr & DMA_SCR_PL_MASK;
regval |= (uint32_t)dmast->channel << DMA_SCR_CHSEL_SHIFT;
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
@ -721,16 +721,16 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
*/
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_DBM|DMA_SCR_CIRC|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
regval &= ~(DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | DMA_SCR_MINC |
DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | DMA_SCR_PINCOS |
DMA_SCR_CIRC | DMA_SCR_DBM | DMA_SCR_CT |
DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK);
scr &= (DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | DMA_SCR_MINC |
DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | DMA_SCR_PINCOS |
DMA_SCR_DBM | DMA_SCR_CIRC |
DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK);
regval |= scr;
dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0;
dmast->nonstop = (scr & (DMA_SCR_DBM | DMA_SCR_CIRC)) != 0;
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
}
@ -775,7 +775,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
* Interrupt Enable bit (TCIE) is set.
*/
scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE));
scr |= (half ? (DMA_SCR_HTIE | DMA_SCR_TEIE) : (DMA_SCR_TCIE | DMA_SCR_TEIE));
}
else
{

26
arch/arm/src/stm32/stm32f20xxx_rcc.c
View File

@ -88,7 +88,7 @@ static inline void rcc_reset(void)
/* Reset HSEON, CSSON and PLLON bits */
regval = getreg32(STM32_RCC_CR);
regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
/* Reset PLLCFGR register to reset default */
@ -124,33 +124,33 @@ static inline void rcc_enableahb1(void)
regval = getreg32(STM32_RCC_AHB1ENR);
/* Enable GPIOA, GPIOB, .... GPIOI*/
/* Enable GPIOA, GPIOB, .... GPIOI */
#if STM32_NGPIO > 0
regval |= (RCC_AHB1ENR_GPIOAEN
#if STM32_NGPIO > 16
|RCC_AHB1ENR_GPIOBEN
| RCC_AHB1ENR_GPIOBEN
#endif
#if STM32_NGPIO > 32
|RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIOCEN
#endif
#if STM32_NGPIO > 48
|RCC_AHB1ENR_GPIODEN
| RCC_AHB1ENR_GPIODEN
#endif
#if STM32_NGPIO > 64
|RCC_AHB1ENR_GPIOEEN
| RCC_AHB1ENR_GPIOEEN
#endif
#if STM32_NGPIO > 80
|RCC_AHB1ENR_GPIOFEN
| RCC_AHB1ENR_GPIOFEN
#endif
#if STM32_NGPIO > 96
|RCC_AHB1ENR_GPIOGEN
| RCC_AHB1ENR_GPIOGEN
#endif
#if STM32_NGPIO > 112
|RCC_AHB1ENR_GPIOHEN
| RCC_AHB1ENR_GPIOHEN
#endif
#if STM32_NGPIO > 128
|RCC_AHB1ENR_GPIOIEN
| RCC_AHB1ENR_GPIOIEN
#endif
);
#endif
@ -182,7 +182,7 @@ static inline void rcc_enableahb1(void)
#ifdef CONFIG_STM32_ETHMAC
/* Ethernet MAC clocking */
regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|RCC_AHB1ENR_ETHMACRXEN);
regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN);
#ifdef CONFIG_STM32_ETH_PTP
/* Precision Time Protocol (PTP) */
@ -195,7 +195,7 @@ static inline void rcc_enableahb1(void)
#ifdef CONFIG_STM32_OTGHS
/* USB OTG HS */
regval |= (RCC_AHB1ENR_OTGHSEN|RCC_AHB1ENR_OTGHSULPIEN);
regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN);
#endif
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
@ -624,7 +624,7 @@ static void stm32_stdclockconfig(void)
/* Set the PLL dividers and multipliers to configure the main PLL */
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
putreg32(regval, STM32_RCC_PLLCFG);

41
arch/arm/src/stm32/stm32f30xxx_i2c.c
View File

@ -894,9 +894,9 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET);
if ((sr & I2C_INT_TIMEOUT) != 0)
{
return;
}
{
return;
}
/* Calculate the elapsed time */
@ -924,7 +924,7 @@ static inline void stm32_i2c_sem_waitstop(FAR struct stm32_i2c_priv_s *priv)
static inline void stm32_i2c_sem_post(FAR struct i2c_dev_s *dev)
{
sem_post( &((struct stm32_i2c_inst_s *)dev)->priv->sem_excl );
sem_post(&((struct stm32_i2c_inst_s *)dev)->priv->sem_excl);
}
/************************************************************************************
@ -1138,10 +1138,10 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
}
uint32_t timingr =
(presc << I2C_TIMINGR_PRESC_SHIFT)|
(s_time << I2C_TIMINGR_SCLDEL_SHIFT)|
(h_time << I2C_TIMINGR_SDADEL_SHIFT)|
(scl_h_period << I2C_TIMINGR_SCLH_SHIFT)|
(presc << I2C_TIMINGR_PRESC_SHIFT) |
(s_time << I2C_TIMINGR_SCLDEL_SHIFT) |
(h_time << I2C_TIMINGR_SDADEL_SHIFT) |
(scl_h_period << I2C_TIMINGR_SCLH_SHIFT) |
(scl_l_period << I2C_TIMINGR_SCLL_SHIFT);
stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr);
@ -1233,7 +1233,7 @@ static inline void stm32_i2c_clrstart(FAR struct stm32_i2c_priv_s *priv)
/* TODO check PEC (32 bit separate reg) */
stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET,
I2C_CR2_START|I2C_CR2_STOP, 0);
I2C_CR2_START | I2C_CR2_STOP, 0);
}
/************************************************************************************
@ -1397,7 +1397,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
stm32_i2c_traceevent(priv, I2CEVENT_REITBUFEN, 0);
stm32_i2c_enableinterrupts(priv);
}
else if ((priv->dcnt == 0) && (priv->msgc==0))
else if ((priv->dcnt == 0) && (priv->msgc == 0))
{
stm32_i2c_traceevent(priv, I2CEVENT_DISITBUFEN, 0);
stm32_i2c_disableinterrupts(priv);
@ -1459,7 +1459,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* and wake it up.
*/
sem_post( &priv->sem_isr );
sem_post(&priv->sem_isr);
priv->intstate = INTSTATE_DONE;
}
#else
@ -1494,7 +1494,7 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
* and wake it up.
*/
sem_post( &priv->sem_isr );
sem_post(&priv->sem_isr);
priv->intstate = INTSTATE_DONE;
}
#else
@ -1937,9 +1937,10 @@ static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev,
},
{
.addr = ((struct stm32_i2c_inst_s *)dev)->address,
.flags = ((struct stm32_i2c_inst_s *)dev)->flags | ((buflen>0) ? I2C_M_READ : I2C_M_NORESTART),
.flags = ((struct stm32_i2c_inst_s *)dev)->flags |
((buflen > 0) ? I2C_M_READ : I2C_M_NORESTART),
.buffer = buffer,
.length = (buflen>0) ? buflen : -buflen
.length = (buflen > 0) ? buflen : -buflen
}
};
@ -1988,7 +1989,7 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port)
#if STM32_PCLK1_FREQUENCY < 2000000
# warning STM32_I2C_INIT: Peripheral clock must be at least 2 MHz to support 100 kHz operation.
return NULL;
return NULL;
#endif
/* Get I2C private structure */
@ -2016,7 +2017,7 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port)
/* Allocate instance */
if (!(inst = kmm_malloc( sizeof(struct stm32_i2c_inst_s))))
if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s))))
{
return NULL;
}
@ -2037,8 +2038,8 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port)
if ((volatile int)priv->refs++ == 0)
{
stm32_i2c_sem_init( (struct i2c_dev_s *)inst );
stm32_i2c_init( priv );
stm32_i2c_sem_init((struct i2c_dev_s *)inst);
stm32_i2c_init(priv);
}
irqrestore(irqs);
@ -2079,11 +2080,11 @@ int up_i2cuninitialize(FAR struct i2c_dev_s * dev)
/* Disable power and other HW resource (GPIO's) */
stm32_i2c_deinit( ((struct stm32_i2c_inst_s *)dev)->priv );
stm32_i2c_deinit(((struct stm32_i2c_inst_s *)dev)->priv);
/* Release unused resources */
stm32_i2c_sem_destroy( (struct i2c_dev_s *)dev );
stm32_i2c_sem_destroy((struct i2c_dev_s *)dev);
kmm_free(dev);
return OK;

118
arch/arm/src/stm32/stm32f30xxx_rcc.c
View File

@ -93,7 +93,7 @@ static inline void rcc_reset(void)
putreg32(0, STM32_RCC_CFGR2); /* Reset fCK source for all U[S]ARTs to PCLK */
regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */
regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */
@ -578,98 +578,98 @@ static void stm32_stdclockconfig(void)
# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
# endif
/* Set the HSE prescaler */
/* Set the HSE prescaler */
regval = STM32_CFGR2_PREDIV1;
putreg32(regval, STM32_RCC_CFGR2);
regval = STM32_CFGR2_PREDIV1;
putreg32(regval, STM32_RCC_CFGR2);
# endif
#endif
#ifndef CONFIG_STM32_VALUELINE
/* Value-line devices don't implement flash prefetch/waitstates */
/* Enable FLASH prefetch buffer and 2 wait states */
/* Value-line devices don't implement flash prefetch/waitstates */
/* Enable FLASH prefetch buffer and 2 wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
#endif
/* Set the HCLK source/divider */
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK2 divider */
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* If we are using the PLL, configure and start it */
/* Set the PLL divider and multiplier */
/* If we are using the PLL, configure and start it */
/* Set the PLL divider and multiplier */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
/* Enable the PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
#endif
/* Select the system clock source (probably the PLL) */
/* Select the system clock source (probably the PLL) */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until the selected source is used as the system clock source */
/* Wait until the selected source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
/*
* TODO: There is another case where the LSI needs to
* be enabled: if the MCO pin selects LSI as source.
*/
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
* be enabled: if the MCO pin selects LSI as source.
*/
stm32_rcc_enablelsi();
stm32_rcc_enablelsi();
#endif
#if defined(CONFIG_RTC_LSECLOCK)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO pin selects LSE as source.
*
* TODO: There is another case where the LSE needs to
* be enabled: if USARTx selects LSE as source.
*/
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO pin selects LSE as source.
*
* TODO: There is another case where the LSE needs to
* be enabled: if USARTx selects LSE as source.
*/
stm32_rcc_enablelse();
stm32_rcc_enablelse();
#endif
}
#endif

122
arch/arm/src/stm32/stm32f37xxx_rcc.c
View File

@ -92,7 +92,7 @@ static inline void rcc_reset(void)
putreg32(0, STM32_RCC_CFGR2); /* Reset fCK source for all U[S]ARTs to PCLK */
regval = getreg32(STM32_RCC_CR); /* Reset HSEON, CSSON and PLLON bits */
regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */
@ -473,97 +473,97 @@ static void stm32_stdclockconfig(void)
# error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
# endif
/* Set the HSE prescaler */
/* Set the HSE prescaler */
regval = STM32_CFGR2_PREDIV1;
putreg32(regval, STM32_RCC_CFGR2);
regval = STM32_CFGR2_PREDIV1;
putreg32(regval, STM32_RCC_CFGR2);
# endif
/* Enable FLASH prefetch buffer and 2 wait states */
/* Enable FLASH prefetch buffer and 2 wait states */
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2|FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY_MASK;
regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
putreg32(regval, STM32_FLASH_ACR);
/* Set the HCLK source/divider */
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK2 divider */
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* If we are using the PLL, configure and start it */
/* Set the PLL divider and multiplier */
/* If we are using the PLL, configure and start it */
/* Set the PLL divider and multiplier */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
putreg32(regval, STM32_RCC_CFGR);
/* Enable the PLL */
/* Enable the PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
#endif
/* Select the system clock source (probably the PLL) */
/* Select the system clock source (probably the PLL) */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= STM32_SYSCLK_SW;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until the selected source is used as the system clock source */
/* Wait until the selected source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
* be enabled: if the MCO pin selects LSI as source.
*/
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
* be enabled: if the MCO pin selects LSI as source.
*/
stm32_rcc_enablelsi();
stm32_rcc_enablelsi();
#endif
#if defined(CONFIG_RTC_LSECLOCK)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO pin selects LSE as source.
*
* TODO: There is another case where the LSE needs to
* be enabled: if USART1-2-3 selects LSE as source.
*
* TODO: There is another case where the LSE needs to
* be enabled: if CEC selects LSE as source.
*/
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO pin selects LSE as source.
*
* TODO: There is another case where the LSE needs to
* be enabled: if USART1-2-3 selects LSE as source.
*
* TODO: There is another case where the LSE needs to
* be enabled: if CEC selects LSE as source.
*/
stm32_rcc_enablelse();
stm32_rcc_enablelse();
#endif
}
#endif

22
arch/arm/src/stm32/stm32f40xxx_dma.c
View File

@ -682,7 +682,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
*/
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
regval &= ~(DMA_SCR_PL_MASK|DMA_SCR_CHSEL_MASK);
regval &= ~(DMA_SCR_PL_MASK | DMA_SCR_CHSEL_MASK);
regval |= scr & DMA_SCR_PL_MASK;
regval |= (uint32_t)dmast->channel << DMA_SCR_CHSEL_SHIFT;
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
@ -724,14 +724,14 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
*/
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
DMA_SCR_DBM|DMA_SCR_CIRC|
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
regval &= ~(DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | DMA_SCR_MINC |
DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | DMA_SCR_PINCOS |
DMA_SCR_CIRC | DMA_SCR_DBM | DMA_SCR_CT |
DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK);
scr &= (DMA_SCR_PFCTRL | DMA_SCR_DIR_MASK | DMA_SCR_PINC | DMA_SCR_MINC |
DMA_SCR_PSIZE_MASK | DMA_SCR_MSIZE_MASK | DMA_SCR_PINCOS |
DMA_SCR_DBM | DMA_SCR_CIRC |
DMA_SCR_PBURST_MASK | DMA_SCR_MBURST_MASK);
regval |= scr;
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
}
@ -773,7 +773,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
* interrupt at the halfway point.
*/
if ((scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) == 0)
if ((scr & (DMA_SCR_DBM | DMA_SCR_CIRC)) == 0)
{
/* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
* set and an interrupt is generated if the Half-Transfer Interrupt Enable
@ -782,7 +782,7 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
* Interrupt Enable bit (TCIE) is set.
*/
scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE));
scr |= (half ? (DMA_SCR_HTIE | DMA_SCR_TEIE) : (DMA_SCR_TCIE | DMA_SCR_TEIE));
}
else
{

28
arch/arm/src/stm32/stm32f40xxx_rcc.c
View File

@ -96,7 +96,7 @@ static inline void rcc_reset(void)
/* Reset HSION, HSEON, CSSON and PLLON bits */
regval = getreg32(STM32_RCC_CR);
regval &= ~(RCC_CR_HSION|RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
/* Reset PLLCFGR register to reset default */
@ -132,33 +132,33 @@ static inline void rcc_enableahb1(void)
regval = getreg32(STM32_RCC_AHB1ENR);
/* Enable GPIOA, GPIOB, .... GPIOI*/
/* Enable GPIOA, GPIOB, .... GPIOI */
#if STM32_NGPIO > 0
regval |= (RCC_AHB1ENR_GPIOAEN
#if STM32_NGPIO > 16
|RCC_AHB1ENR_GPIOBEN
| RCC_AHB1ENR_GPIOBEN
#endif
#if STM32_NGPIO > 32
|RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIOCEN
#endif
#if STM32_NGPIO > 48
|RCC_AHB1ENR_GPIODEN
| RCC_AHB1ENR_GPIODEN
#endif
#if STM32_NGPIO > 64
|RCC_AHB1ENR_GPIOEEN
| RCC_AHB1ENR_GPIOEEN
#endif
#if STM32_NGPIO > 80
|RCC_AHB1ENR_GPIOFEN
| RCC_AHB1ENR_GPIOFEN
#endif
#if STM32_NGPIO > 96
|RCC_AHB1ENR_GPIOGEN
| RCC_AHB1ENR_GPIOGEN
#endif
#if STM32_NGPIO > 112
|RCC_AHB1ENR_GPIOHEN
| RCC_AHB1ENR_GPIOHEN
#endif
#if STM32_NGPIO > 128
|RCC_AHB1ENR_GPIOIEN
| RCC_AHB1ENR_GPIOIEN
#endif
);
#endif
@ -196,7 +196,7 @@ static inline void rcc_enableahb1(void)
#ifdef CONFIG_STM32_ETHMAC
/* Ethernet MAC clocking */
regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|RCC_AHB1ENR_ETHMACRXEN);
regval | = (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN);
#ifdef CONFIG_STM32_ETH_PTP
/* Precision Time Protocol (PTP) */
@ -705,10 +705,10 @@ static void stm32_stdclockconfig(void)
/* Set the PLL dividers and multipliers to configure the main PLL */
#ifdef STM32_BOARD_USEHSI
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
#else /* if STM32_BOARD_USEHSE */
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
#endif
putreg32(regval, STM32_RCC_PLLCFG);
@ -806,7 +806,7 @@ static inline void rcc_itm_syslog(void)
{
/* Enable SWO output */
modifyreg32(STM32_DBGMCU_CR, DBGMCU_CR_TRACEMODE_MASK, DBGMCU_CR_ASYNCH|\
modifyreg32(STM32_DBGMCU_CR, DBGMCU_CR_TRACEMODE_MASK, DBGMCU_CR_ASYNCH |
DBGMCU_CR_TRACEIOEN);
itm_syslog_initialize();

26
arch/arm/src/stm32/stm32f42xxx_rcc.c
View File

@ -93,7 +93,7 @@ static inline void rcc_reset(void)
/* Reset HSION, HSEON, CSSON and PLLON bits */
regval = getreg32(STM32_RCC_CR);
regval &= ~(RCC_CR_HSION|RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
/* Reset PLLCFGR register to reset default */
@ -129,33 +129,33 @@ static inline void rcc_enableahb1(void)
regval = getreg32(STM32_RCC_AHB1ENR);
/* Enable GPIOA, GPIOB, .... GPIOI*/
/* Enable GPIOA, GPIOB, .... GPIOI */
#if STM32_NGPIO > 0
regval |= (RCC_AHB1ENR_GPIOAEN
#if STM32_NGPIO > 16
|RCC_AHB1ENR_GPIOBEN
| RCC_AHB1ENR_GPIOBEN
#endif
#if STM32_NGPIO > 32
|RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIOCEN
#endif
#if STM32_NGPIO > 48
|RCC_AHB1ENR_GPIODEN
| RCC_AHB1ENR_GPIODEN
#endif
#if STM32_NGPIO > 64
|RCC_AHB1ENR_GPIOEEN
| RCC_AHB1ENR_GPIOEEN
#endif
#if STM32_NGPIO > 80
|RCC_AHB1ENR_GPIOFEN
| RCC_AHB1ENR_GPIOFEN
#endif
#if STM32_NGPIO > 96
|RCC_AHB1ENR_GPIOGEN
| RCC_AHB1ENR_GPIOGEN
#endif
#if STM32_NGPIO > 112
|RCC_AHB1ENR_GPIOHEN
| RCC_AHB1ENR_GPIOHEN
#endif
#if STM32_NGPIO > 128
|RCC_AHB1ENR_GPIOIEN
| RCC_AHB1ENR_GPIOIEN
#endif
);
#endif
@ -193,7 +193,7 @@ static inline void rcc_enableahb1(void)
#ifdef CONFIG_STM32_ETHMAC
/* Ethernet MAC clocking */
regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|RCC_AHB1ENR_ETHMACRXEN);
regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | RCC_AHB1ENR_ETHMACRXEN);
#ifdef CONFIG_STM32_ETH_PTP
/* Precision Time Protocol (PTP) */
@ -703,10 +703,10 @@ static void stm32_stdclockconfig(void)
/* Set the PLL dividers and multipliers to configure the main PLL */
#ifdef STM32_BOARD_USEHSI
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
#else /* if STM32_BOARD_USEHSE */
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
#endif
putreg32(regval, STM32_RCC_PLLCFG);

22
arch/arm/src/stm32/stm32f44xxx_rcc.c
View File

@ -93,7 +93,7 @@ static inline void rcc_reset(void)
/* Reset HSION, HSEON, CSSON and PLLON bits */
regval = getreg32(STM32_RCC_CR);
regval &= ~(RCC_CR_HSION|RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
/* Reset PLLCFGR register to reset default */
@ -129,30 +129,30 @@ static inline void rcc_enableahb1(void)
regval = getreg32(STM32_RCC_AHB1ENR);
/* Enable GPIOA, GPIOB, .... GPIOI*/
/* Enable GPIOA, GPIOB, .... GPIOI */
#if STM32_NGPIO > 0
regval |= (RCC_AHB1ENR_GPIOAEN
#if STM32_NGPIO > 16
|RCC_AHB1ENR_GPIOBEN
| RCC_AHB1ENR_GPIOBEN
#endif
#if STM32_NGPIO > 32
|RCC_AHB1ENR_GPIOCEN
| RCC_AHB1ENR_GPIOCEN
#endif
#if STM32_NGPIO > 48
|RCC_AHB1ENR_GPIODEN
| RCC_AHB1ENR_GPIODEN
#endif
#if STM32_NGPIO > 64
|RCC_AHB1ENR_GPIOEEN
| RCC_AHB1ENR_GPIOEEN
#endif
#if STM32_NGPIO > 80
|RCC_AHB1ENR_GPIOFEN
| RCC_AHB1ENR_GPIOFEN
#endif
#if STM32_NGPIO > 96
|RCC_AHB1ENR_GPIOGEN
| RCC_AHB1ENR_GPIOGEN
#endif
#if STM32_NGPIO > 112
|RCC_AHB1ENR_GPIOHEN
| RCC_AHB1ENR_GPIOHEN
#endif
);
#endif
@ -635,10 +635,10 @@ static void stm32_stdclockconfig(void)
/* Set the PLL dividers and multipliers to configure the main PLL */
#ifdef STM32_BOARD_USEHSI
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR);
#else /* if STM32_BOARD_USEHSE */
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR);
#endif
putreg32(regval, STM32_RCC_PLLCFG);

8
arch/arm/src/stm32/stm32l15xxx_rcc.c
View File

@ -51,7 +51,7 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* HSE divisor to yield ~1MHz RTC clock (valid for HSE = 8MHz)*/
/* HSE divisor to yield ~1MHz RTC clock (valid for HSE = 8MHz) */
#define HSE_DIVISOR RCC_CR_RTCPRE_HSEd8
@ -573,7 +573,7 @@ static void stm32_stdclockconfig(void)
regval |= HSE_DIVISOR;
putreg32(regval, STM32_RCC_CR);
/* Restore the previous state of the DBP bit */
/* Restore the previous state of the DBP bit */
putreg32(regval, STM32_PWR_CR);
@ -711,8 +711,8 @@ static void stm32_stdclockconfig(void)
#if defined(CONFIG_STM32_IWDG) || \
defined(CONFIG_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
/* Low speed internal clock source LSI */
/*
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
* be enabled: if the MCO pin selects LSI as source.
*/