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STM32: Correct some spacing issues

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This commit is contained in:
Gregory Nutt 2015-10-07 13:45:15 -06:00
parent b6638315a4
commit 53f6fd6e66
43 changed files with 1209 additions and 1184 deletions
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1
arch/arm/src/stm32/stm32_adc.c
View File

@ -1562,6 +1562,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
#if ADC_MAX_SAMPLES == 1
/* Select on first indexed channel for backward compatibility. */
adc_set_ch_idx(dev, 0);
#else
adc_set_ch(dev, 0);

12
arch/arm/src/stm32/stm32_bbsram.c
View File

@ -119,10 +119,14 @@ struct stm32_bbsram_s
static int stm32_bbsram_open(FAR struct file *filep);
static int stm32_bbsram_close(FAR struct file *filep);
static off_t stm32_bbsram_seek(FAR struct file *filep, off_t offset, int whence);
static ssize_t stm32_bbsram_read(FAR struct file *, FAR char *, size_t);
static ssize_t stm32_bbsram_write(FAR struct file *, FAR const char *, size_t);
static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
static off_t stm32_bbsram_seek(FAR struct file *filep, off_t offset,
int whence);
static ssize_t stm32_bbsram_read(FAR struct file *filep, FAR char *buffer,
size_t len);
static ssize_t stm32_bbsram_write(FAR struct file *filep,
FAR const char *buffer, size_t len);
static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
unsigned long arg);
#ifndef CONFIG_DISABLE_POLL
static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds,
bool setup);

1
arch/arm/src/stm32/stm32_can.c
View File

@ -253,6 +253,7 @@ static uint32_t can_vgetreg(uint32_t addr)
{
lldbg("...\n");
}
return val;
}
}

2
arch/arm/src/stm32/stm32_dma2d.c
View File

@ -2173,7 +2173,7 @@ int up_dma2dinitialize(void)
/* Enable dma2d transfer and clut loading interrupts only */
stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE, DMA2D_CR_TEIE |
DMA2D_CR_TWIE|DMA2D_CR_CAEIE||DMA2D_CR_CEIE);
DMA2D_CR_TWIE | DMA2D_CR_CAEIE | DMA2D_CR_CEIE);
#else
/* Enable dma transfer interrupt only */

1
arch/arm/src/stm32/stm32_eth.c
View File

@ -772,6 +772,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
lldbg("...\n");
}
return val;
}
}

3
arch/arm/src/stm32/stm32_i2c.c
View File

@ -1938,7 +1938,8 @@ static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev,
},
{
.addr = ((struct stm32_i2c_inst_s *)dev)->address,
.flags = ((struct stm32_i2c_inst_s *)dev)->flags | ((buflen>0) ? I2C_M_READ : I2C_M_NORESTART),
.flags = ((struct stm32_i2c_inst_s *)dev)->flags |
((buflen > 0) ? I2C_M_READ : I2C_M_NORESTART),
.buffer = buffer,
.length = (buflen > 0) ? buflen : -buflen
}

3
arch/arm/src/stm32/stm32_i2c_alt.c
View File

@ -2382,7 +2382,8 @@ static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev,
},
{
.addr = ((struct stm32_i2c_inst_s *)dev)->address,
.flags = ((struct stm32_i2c_inst_s *)dev)->flags | ((buflen>0) ? I2C_M_READ : I2C_M_NORESTART),
.flags = ((struct stm32_i2c_inst_s *)dev)->flags |
((buflen > 0) ? I2C_M_READ : I2C_M_NORESTART),
.buffer = buffer,
.length = (buflen > 0) ? buflen : -buflen
}

1
arch/arm/src/stm32/stm32_iwdg.c
View File

@ -217,6 +217,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
lldbg("...\n");
}
return val;
}
}

12
arch/arm/src/stm32/stm32_ltdc.c
View File

@ -687,7 +687,8 @@ static const struct fb_vtable_s g_vtable =
.getvideoinfo = stm32_getvideoinfo,
.getplaneinfo = stm32_getplaneinfo
#ifdef STM32_LAYER_CLUT_SIZE
,.getcmap = stm32_getcmap,
,
.getcmap = stm32_getcmap,
.putcmap = stm32_putcmap
#endif
};
@ -749,7 +750,8 @@ static struct stm32_ltdcdev_s g_ltdc =
}
}
#ifdef CONFIG_STM32_LTDC_L2
,.layer[LTDC_LAYER_L2] =
,
.layer[LTDC_LAYER_L2] =
{
.state =
{
@ -2446,8 +2448,7 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
{
sem_wait(priv->state.lock);
#ifdef CONFIG_STM32_DMA2D
/*
* Note! We share the same color lookup table with the dma2d driver and
/* Note! We share the same color lookup table with the dma2d driver and
* the getclut implementation works in the same way.
* To prevent redundant code we simply call the getclut function of the
* dma2d interface.
@ -2534,7 +2535,8 @@ static int stm32_getclut(struct ltdc_layer_s *layer,
*
****************************************************************************/
static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid, uint32_t flag)
static int stm32_getlid(FAR struct ltdc_layer_s *layer, int *lid,
uint32_t flag)
{
FAR struct stm32_layer_s *priv = (FAR struct stm32_layer_s *)layer;

1
arch/arm/src/stm32/stm32_otgfsdev.c
View File

@ -815,6 +815,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
lldbg("...\n");
}
return val;
}
}

11
arch/arm/src/stm32/stm32_otgfshost.c
View File

@ -73,8 +73,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***************************************************************/
/*
* STM32 USB OTG FS Host Driver Support
/* STM32 USB OTG FS Host Driver Support
*
* Pre-requisites
*
@ -4805,7 +4804,8 @@ static void stm32_portreset(FAR struct stm32_usbhost_s *priv)
uint32_t regval;
regval = stm32_getreg(STM32_OTGFS_HPRT);
regval &= ~(OTGFS_HPRT_PENA|OTGFS_HPRT_PCDET|OTGFS_HPRT_PENCHNG|OTGFS_HPRT_POCCHNG);
regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG |
OTGFS_HPRT_POCCHNG);
regval |= OTGFS_HPRT_PRST;
stm32_putreg(STM32_OTGFS_HPRT, regval);
@ -4922,7 +4922,8 @@ static void stm32_vbusdrive(FAR struct stm32_usbhost_s *priv, bool state)
/* Turn on the Host port power. */
regval = stm32_getreg(STM32_OTGFS_HPRT);
regval &= ~(OTGFS_HPRT_PENA|OTGFS_HPRT_PCDET|OTGFS_HPRT_PENCHNG|OTGFS_HPRT_POCCHNG);
regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG |
OTGFS_HPRT_POCCHNG);
if (((regval & OTGFS_HPRT_PPWR) == 0) && state)
{
@ -5132,7 +5133,7 @@ static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv)
* transceiver: "This bit is always 1 with write-only access"
*/
regval = stm32_getreg(STM32_OTGFS_GUSBCFG);;
regval = stm32_getreg(STM32_OTGFS_GUSBCFG);
regval |= OTGFS_GUSBCFG_PHYSEL;
stm32_putreg(STM32_OTGFS_GUSBCFG, regval);

2
arch/arm/src/stm32/stm32_otghsdev.c
View File

@ -815,6 +815,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
lldbg("...\n");
}
return val;
}
}
@ -5657,4 +5658,3 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
}
#endif /* CONFIG_USBDEV && CONFIG_STM32_OTGHSDEV */

11
arch/arm/src/stm32/stm32_otghshost.c
View File

@ -73,8 +73,7 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ***************************************************************/
/*
* STM32 USB OTG HS Host Driver Support
/* STM32 USB OTG HS Host Driver Support
*
* Pre-requisites
*
@ -4805,7 +4804,8 @@ static void stm32_portreset(FAR struct stm32_usbhost_s *priv)
uint32_t regval;
regval = stm32_getreg(STM32_OTGHS_HPRT);
regval &= ~(OTGHS_HPRT_PENA|OTGHS_HPRT_PCDET|OTGHS_HPRT_PENCHNG|OTGHS_HPRT_POCCHNG);
regval &= ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | OTGHS_HPRT_PENCHNG |
OTGHS_HPRT_POCCHNG);
regval |= OTGHS_HPRT_PRST;
stm32_putreg(STM32_OTGHS_HPRT, regval);
@ -4922,7 +4922,8 @@ static void stm32_vbusdrive(FAR struct stm32_usbhost_s *priv, bool state)
/* Turn on the Host port power. */
regval = stm32_getreg(STM32_OTGHS_HPRT);
regval &= ~(OTGHS_HPRT_PENA|OTGHS_HPRT_PCDET|OTGHS_HPRT_PENCHNG|OTGHS_HPRT_POCCHNG);
regval &= ~(OTGHS_HPRT_PENA | OTGHS_HPRT_PCDET | OTGHS_HPRT_PENCHNG |
OTGHS_HPRT_POCCHNG);
if (((regval & OTGHS_HPRT_PPWR) == 0) && state)
{
@ -5132,7 +5133,7 @@ static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv)
* transceiver: "This bit is always 1 with write-only access"
*/
regval = stm32_getreg(STM32_OTGHS_GUSBCFG);;
regval = stm32_getreg(STM32_OTGHS_GUSBCFG);
regval |= OTGHS_GUSBCFG_PHYSEL;
stm32_putreg(STM32_OTGHS_GUSBCFG, regval);

2
arch/arm/src/stm32/stm32_qencoder.c
View File

@ -1099,7 +1099,7 @@ static int stm32_position(FAR struct qe_lowerhalf_s *lower, int32_t *pos)
#else
/* Return the counter value */
*pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET);;
*pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET);
#endif
return OK;
}

1
arch/arm/src/stm32/stm32_sdio.c
View File

@ -954,6 +954,7 @@ static uint8_t stm32_log2(uint16_t value)
value >>= 1;
log2++;
}
return log2;
}

4
arch/arm/src/stm32/stm32_spi.c
View File

@ -1295,7 +1295,7 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t*)txbuffer;;
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *)rxbuffer;
uint16_t word;
@ -1328,7 +1328,7 @@ static void spi_exchange_nodma(FAR struct spi_dev_s *dev, FAR const void *txbuff
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t*)txbuffer;;
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *)rxbuffer;
uint8_t word;

3
arch/arm/src/stm32/stm32_timerisr.c
View File

@ -156,7 +156,8 @@ void up_timer_initialize(void)
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */

8
arch/arm/src/stm32/stm32_usbdev.c
View File

@ -1755,9 +1755,12 @@ static void stm32_ep0setup(struct stm32_usbdev_s *priv)
if (priv->ep0state != EP0STATE_SETUP_READY)
{
/* Not the data phase */
/* Get a 32-bit PMA address and use that to get the 8-byte setup request */
/* Get a 32-bit PMA address and use that to get the 8-byte setup
* request
*/
stm32_copyfrompma((uint8_t*)&priv->ctrl, stm32_geteprxaddr(EP0), USB_SIZEOF_CTRLREQ);
stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0),
USB_SIZEOF_CTRLREQ);
/* And extract the little-endian 16-bit values to host order */
@ -3882,6 +3885,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
stm32_usbpullup(&priv->usbdev, true);
priv->usbdev.speed = USB_SPEED_FULL;
}
return ret;
}

1
arch/arm/src/stm32/stm32_wwdg.c
View File

@ -201,6 +201,7 @@ static uint16_t stm32_getreg(uint32_t addr)
{
lldbg("...\n");
}
return val;
}
}

10
arch/arm/src/stm32/stm32f10xxx_dma.c
View File

@ -502,10 +502,12 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
*/
regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
regval &= ~(DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
ccr &= (DMA_CCR_MEM2MEM|DMA_CCR_PL_MASK|DMA_CCR_MSIZE_MASK|DMA_CCR_PSIZE_MASK|
DMA_CCR_MINC|DMA_CCR_PINC|DMA_CCR_CIRC|DMA_CCR_DIR);
regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
DMA_CCR_DIR);
ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
DMA_CCR_DIR);
regval |= ccr;
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
}

3
arch/arm/src/stm32/stm32f30xxx_i2c.c
View File

@ -1937,7 +1937,8 @@ static int stm32_i2c_writeread(FAR struct i2c_dev_s *dev,
},
{
.addr = ((struct stm32_i2c_inst_s *)dev)->address,
.flags = ((struct stm32_i2c_inst_s *)dev)->flags | ((buflen>0) ? I2C_M_READ : I2C_M_NORESTART),
.flags = ((struct stm32_i2c_inst_s *)dev)->flags |
((buflen > 0) ? I2C_M_READ : I2C_M_NORESTART),
.buffer = buffer,
.length = (buflen > 0) ? buflen : -buflen
}

4
arch/arm/src/stm32/stm32f30xxx_rcc.c
View File

@ -650,8 +650,8 @@ static void stm32_stdclockconfig(void)
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
/*
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
* be enabled: if the MCO pin selects LSI as source.
*/

2
arch/arm/src/stm32/stm32f40xxx_rcc.c
View File

@ -806,7 +806,7 @@ static inline void rcc_itm_syslog(void)
{
/* Enable SWO output */
modifyreg32(STM32_DBGMCU_CR, DBGMCU_CR_TRACEMODE_MASK, DBGMCU_CR_ASYNCH|\
modifyreg32(STM32_DBGMCU_CR, DBGMCU_CR_TRACEMODE_MASK, DBGMCU_CR_ASYNCH |
DBGMCU_CR_TRACEIOEN);
itm_syslog_initialize();

4
arch/arm/src/stm32/stm32l15xxx_rcc.c
View File

@ -711,8 +711,8 @@ static void stm32_stdclockconfig(void)
#if defined(CONFIG_STM32_IWDG) || \
defined(CONFIG_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK)
/* Low speed internal clock source LSI */
/*
/* Low speed internal clock source LSI
*
* TODO: There is another case where the LSI needs to
* be enabled: if the MCO pin selects LSI as source.
*/