From 53fef8d9c4457f3b4099997d4cbf894bbdb7146c Mon Sep 17 00:00:00 2001 From: Huang Qi Date: Wed, 6 Apr 2022 17:07:14 +0800 Subject: [PATCH] arch/risc-v: Replace riscv_fault with riscv_exception Remove riscv_fault since its code is duplicated with riscv_exception, and there are textual excpetion reason in riscv_exception. Signed-off-by: Huang Qi --- arch/risc-v/src/c906/Make.defs | 2 +- arch/risc-v/src/c906/c906_irq_dispatch.c | 2 +- arch/risc-v/src/common/riscv_fault.c | 115 ------------------ arch/risc-v/src/common/riscv_internal.h | 1 - arch/risc-v/src/k210/Make.defs | 2 +- arch/risc-v/src/k210/k210_irq_dispatch.c | 2 +- arch/risc-v/src/mpfs/Make.defs | 2 +- arch/risc-v/src/mpfs/mpfs_irq_dispatch.c | 2 +- arch/risc-v/src/qemu-rv/Make.defs | 2 +- .../risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c | 2 +- 10 files changed, 8 insertions(+), 124 deletions(-) delete mode 100644 arch/risc-v/src/common/riscv_fault.c diff --git a/arch/risc-v/src/c906/Make.defs b/arch/risc-v/src/c906/Make.defs index 6406e8c822..402de9aa87 100644 --- a/arch/risc-v/src/c906/Make.defs +++ b/arch/risc-v/src/c906/Make.defs @@ -27,7 +27,7 @@ CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S # Specify C code within the common directory to be included CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c +CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_exception.c CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c diff --git a/arch/risc-v/src/c906/c906_irq_dispatch.c b/arch/risc-v/src/c906/c906_irq_dispatch.c index 0e2879ae1a..9e125a40b3 100644 --- a/arch/risc-v/src/c906/c906_irq_dispatch.c +++ b/arch/risc-v/src/c906/c906_irq_dispatch.c @@ -58,7 +58,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) if (vector < RISCV_IRQ_ECALLU) { - riscv_fault(irq, regs); + riscv_exception(irq, regs); } /* Firstly, check if the irq is machine external interrupt */ diff --git a/arch/risc-v/src/common/riscv_fault.c b/arch/risc-v/src/common/riscv_fault.c deleted file mode 100644 index 86afecd9ec..0000000000 --- a/arch/risc-v/src/common/riscv_fault.c +++ /dev/null @@ -1,115 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/common/riscv_fault.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include - -#include "sched/sched.h" -#include "irq/irq.h" -#include "riscv_internal.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: riscv_fault - * - * Description: - * This is Fault exception handler. - * - ****************************************************************************/ - -void riscv_fault(int irq, uintptr_t *regs) -{ - CURRENT_REGS = regs; - - _alert("EPC: %" PRIxREG "\n", - CURRENT_REGS[REG_EPC]); - - _alert("Fault IRQ=%d\n", irq); - - /* Dump register info */ - - _alert("A0: %" PRIxREG " A1: %" PRIxREG " A2: %" PRIxREG - " A3: %" PRIxREG "\n", - CURRENT_REGS[REG_A0], CURRENT_REGS[REG_A1], - CURRENT_REGS[REG_A2], CURRENT_REGS[REG_A3]); - - _alert("A4: %" PRIxREG " A5: %" PRIxREG " A6: %" PRIxREG - " A7: %" PRIxREG "\n", - CURRENT_REGS[REG_A4], CURRENT_REGS[REG_A5], - CURRENT_REGS[REG_A6], CURRENT_REGS[REG_A7]); - - _alert("T0: %" PRIxREG " T1: %" PRIxREG " T2: %" PRIxREG - " T3: %" PRIxREG "\n", - CURRENT_REGS[REG_T0], CURRENT_REGS[REG_T1], - CURRENT_REGS[REG_T2], CURRENT_REGS[REG_T3]); - - _alert("T4: %" PRIxREG " T5: %" PRIxREG - " T6: %" PRIxREG "\n", - CURRENT_REGS[REG_T4], CURRENT_REGS[REG_T5], - CURRENT_REGS[REG_T6]); - - _alert("S0: %" PRIxREG " S1: %" PRIxREG " S2: %" PRIxREG - " S3: %" PRIxREG "\n", - CURRENT_REGS[REG_S0], CURRENT_REGS[REG_S1], - CURRENT_REGS[REG_S2], CURRENT_REGS[REG_S3]); - - _alert("S4: %" PRIxREG " S5: %" PRIxREG " S6: %" PRIxREG - " S7: %" PRIxREG "\n", - CURRENT_REGS[REG_S4], CURRENT_REGS[REG_S5], - CURRENT_REGS[REG_S6], CURRENT_REGS[REG_S7]); - - _alert("S8: %" PRIxREG " S9: %" PRIxREG " S10: %" PRIxREG - " S11: %" PRIxREG "\n", - CURRENT_REGS[REG_S8], CURRENT_REGS[REG_S9], - CURRENT_REGS[REG_S10], CURRENT_REGS[REG_S11]); - -#ifdef RISCV_SAVE_GP - _alert("GP: %" PRIxREG " SP: %" PRIxREG " FP: %" PRIxREG - " TP: %" PRIxREG "RA: %" PRIxREG "\n", - CURRENT_REGS[REG_GP], CURRENT_REGS[REG_SP], - CURRENT_REGS[REG_FP], CURRENT_REGS[REG_TP], - CURRENT_REGS[REG_RA]); -#else - _alert("SP: %" PRIxREG " FP: %" PRIxREG " TP: %" PRIxREG - " RA: %" PRIxREG "\n", - CURRENT_REGS[REG_SP], CURRENT_REGS[REG_FP], - CURRENT_REGS[REG_TP], CURRENT_REGS[REG_RA]); -#endif - - up_irq_save(); -} diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h index 1a2c8693e2..6c0be35fc1 100644 --- a/arch/risc-v/src/common/riscv_internal.h +++ b/arch/risc-v/src/common/riscv_internal.h @@ -286,7 +286,6 @@ void riscv_netinitialize(void); /* Exception Handler ********************************************************/ uintptr_t *riscv_doirq(int irq, uintptr_t *regs); -void riscv_fault(int irq, uintptr_t *regs); void riscv_exception(uintptr_t mcause, uintptr_t *regs); /* Debug ********************************************************************/ diff --git a/arch/risc-v/src/k210/Make.defs b/arch/risc-v/src/k210/Make.defs index df638976bf..09da054cd8 100644 --- a/arch/risc-v/src/k210/Make.defs +++ b/arch/risc-v/src/k210/Make.defs @@ -27,7 +27,7 @@ CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S # Specify C code within the common directory to be included CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c +CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_exception.c CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c diff --git a/arch/risc-v/src/k210/k210_irq_dispatch.c b/arch/risc-v/src/k210/k210_irq_dispatch.c index 4115c43996..b5b5db5668 100644 --- a/arch/risc-v/src/k210/k210_irq_dispatch.c +++ b/arch/risc-v/src/k210/k210_irq_dispatch.c @@ -58,7 +58,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) if (vector < RISCV_IRQ_ECALLU) { - riscv_fault(irq, regs); + riscv_exception(irq, regs); } /* Firstly, check if the irq is machine external interrupt */ diff --git a/arch/risc-v/src/mpfs/Make.defs b/arch/risc-v/src/mpfs/Make.defs index f519149bb1..f2f4b331ea 100755 --- a/arch/risc-v/src/mpfs/Make.defs +++ b/arch/risc-v/src/mpfs/Make.defs @@ -24,7 +24,7 @@ CMN_ASRCS += mpfs_head.S riscv_vectors.S riscv_exception_common.S riscv_testset. # Specify C code within the common directory to be included CMN_CSRCS += riscv_initialize.c riscv_swint.c -CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_fault.c +CMN_CSRCS += riscv_createstack.c riscv_exit.c riscv_exception.c CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c diff --git a/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c b/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c index 01e471c0b7..67337de92b 100755 --- a/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c +++ b/arch/risc-v/src/mpfs/mpfs_irq_dispatch.c @@ -61,7 +61,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) vector == RISCV_IRQ_STOREPF || vector == RISCV_IRQ_RESERVED) { - riscv_fault(irq, regs); + riscv_exception(irq, regs); } if ((vector & RISCV_IRQ_BIT) != 0) diff --git a/arch/risc-v/src/qemu-rv/Make.defs b/arch/risc-v/src/qemu-rv/Make.defs index 3d2e6dbaa7..cd95137dc4 100644 --- a/arch/risc-v/src/qemu-rv/Make.defs +++ b/arch/risc-v/src/qemu-rv/Make.defs @@ -34,7 +34,7 @@ CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c CMN_CSRCS += riscv_idle.c riscv_tcbinfo.c riscv_cpuidlestack.c -CMN_CSRCS += riscv_fault.c riscv_getnewintctx.c riscv_doirq.c +CMN_CSRCS += riscv_exception.c riscv_getnewintctx.c riscv_doirq.c CMN_CSRCS += riscv_cpuindex.c ifeq ($(CONFIG_SMP), y) diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c index 129aad2812..645789c964 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c @@ -61,7 +61,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) if (vector < RISCV_IRQ_ECALLM) { - riscv_fault(irq, regs); + riscv_exception(irq, regs); } /* Firstly, check if the irq is machine external interrupt */