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A few more Cortex-A5 and SAMA5 files

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This commit is contained in:
Gregory Nutt 2013-07-21 12:52:38 -06:00
parent 66259bfc53
commit 543b5b7e03
16 changed files with 1837 additions and 235 deletions
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7
ChangeLog
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@ -5143,4 +5143,9 @@
create the Cortex-A5 support (2013-7-19).
* arch/arm/src/armv7-a/arm_cache.S: Cortex-A5 cache operations
(2013-7-20).
* /arch/arm/src/armv7-a/arm_fpuconfig.S and fpu.h: A few more files for
the ARMv7-A/Cortex-A5 port (2013-7-21).
* arm/src/sama5/sam_boot.c, sam_clockconfig.h, sam_lowputc.h: A few
more files for the SAMA5D3 port (2013-7-21).
* configs/sama5d3x-ek/src/sam_autoleds.c: A few more files for the port
to the SAMA5D3x-EK board (2013-7-21).

16
arch/arm/include/sama5/chip.h
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@ -92,13 +92,21 @@
*/
#if defined(CONFIG_ARCH_CHIP_ATSAMA5D31)
# define ATSAMA5D3 1 /* SAMA5D3 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D33)
# define ATSAMA5D3 1 /* SAMA5D3 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D34)
# define ATSAMA5D3 1 /* SAMA5D3 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
#elif defined(CONFIG_ARCH_CHIP_ATSAMA5D35)
# define ATSAMA5D3 1 /* SAMA5D3 family */
# define ATSAMA5D3 1 /* SAMA5D3 family */
# define SAM_ISRAM0_SIZE (64*1024) /* 128KB of SRAM in two banks */
# define SAM_ISRAM1_SIZE (64*1024)
#else
# error Unrecognized SAMAD5 chip
#endif

4
arch/arm/src/arm/pg_macros.h
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@ -80,7 +80,7 @@
/* Virtual base of the address of the L2 page tables need to recalculates
* using this new virtual base address of the L2 page table.
*/
*/
# undef PGTABLE_L2_FINE_VBASE
# define PGTABLE_L2_FINE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_FINE_OFFSET)
@ -369,7 +369,7 @@
* Description:
* Write several, contiguous L2 page table entries. npages entries will be
* written. This macro is used when CONFIG_PAGING is enable. This case,
* it is used asfollows:
* it is used as follows:
*
* ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table
* ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address

27
arch/arm/src/armv7-a/arm.h
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@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/armv7-a/arm.h
* Non-CP15 Registers
*
@ -7,10 +7,11 @@
*
* References:
*
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1, Copyright © 2010
* ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition", Copyright ©
* 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM DDI 0406C.b (ID072512)
* "Cortex-A5™ MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright © 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM® Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright © 1996-1998, 2000, 2004-2012 ARM. All rights reserved.
* ARM DDI 0406C.b (ID072512)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -39,20 +40,20 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_A_CPSR_H
#define __ARCH_ARM_SRC_ARMV7_A_CPSR_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* ARMv7-A **************************************************************************/
/* ARMv7-A ******************************************************************/
/* PSR bits */
@ -86,9 +87,9 @@
#define PSR_Z_BIT (1 << 30) /* Bit 30: Zero condition flag */
#define PSR_N_BIT (1 << 31) /* Bit 31: Negative condition flag */
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__

98
arch/arm/src/armv7-a/arm_fpuconfig.S Normal file
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@ -0,0 +1,98 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_fpuconfig.S
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "cp15.h"
.file "arm_fpuconfig.S"
/****************************************************************************
* Preprocessor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.globl arm_fpuconfig
/****************************************************************************
* Assembly Macros
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
.text
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: sam_fpuconfig
*
* Description:
* Configure the FPU. Enables access to CP10 and CP11
*
****************************************************************************/
.globl arm_fpuconfig
.type arm_fpuconfig, %function
arm_fpuconfig:
/* Enable access to CP10 and CP11 in CP15.CACR */
mrc CP15_CPACR(r0)
orr r0, r0, #0xf00000
mcr CP15_CPACR(r0)
/* Enable access to CP10 and CP11 in CP15.NSACR */
/* REVISIT: Do we need to do this? */
/* Set FPEXC.EN (B30) */
fmrx r0, fpexc
orr r0, r0, #0x40000000
fmxr fpexc, r0
bx lr
.size arm_fpuconfig, . - arm_fpuconfig
.end

28
arch/arm/src/armv7-a/arm_head.S
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@ -343,17 +343,20 @@ __start:
/* Invalidate caches and TLBs.
*
* NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not
* support a CP15 operation to invalidate the entire data cache. ...
* In normal usage the only time the entire data cache has to be
* invalidated is on reset."
* NOTE: "The ARMv7 Virtual Memory System Architecture (VMSA) does not
* support a CP15 operation to invalidate the entire data cache. ...
* In normal usage the only time the entire data cache has to be
* invalidated is on reset."
*
* REVISIT: This could be an issue if NuttX is every started in a
* context where the DCache could be dirty.
* The instruction cache is virtually indexed and physically tagged but
* the data cache is physically indexed and physically tagged. So it
* should not be an issue if the system comes up with a dirty Dcache;
* the ICache, however, must be invalidated.
*/
mov r0, #0
mcr CP15_ICIALLUIS(r0) /* Invalidate entire instruction cache Inner Shareable */
mcr CP15_TLBIALLIS(r0) /* Invalidate entire Unified TLB Inner Shareable */
/* Load the page table address.
*
@ -392,10 +395,15 @@ __start:
ldr lr, .LCvstart /* Abs. virtual address */
/* Configure the domain access register (see mmu.h) */
/* Configure the domain access register (see mmu.h).
*
* Domains 0: Accesses are not checked
* Domains 1: Accesses are not checked
* Domains 2: Accesses checked against permissions in the TLB
*/
mov r0, #0x1f /* Domains 0, 1 = client */
mcr CP15_DACR(r0) /* Load domain access register */
mov r0, #(DACR_MANAGER(0) | DACR_MANAGER(1) | DACR_CLIENT(2))
mcr CP15_DACR(r0) /* Set domain access register */
/* Configure the system control register (see sctrl.h) */
@ -668,7 +676,7 @@ __start:
/* Finally branch to the OS entry point */
mov lr, #0
mov lr, #0
b os_start
/* Text-section constants:

90
arch/arm/src/armv7-a/fpu.h Normal file
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@ -0,0 +1,90 @@
/****************************************************************************
* arch/arm/src/armv7-a/fpu.h
* Non-CP15 Registers
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_ARMV7_A_CPSR_H
#define __ARCH_ARM_SRC_ARMV7_A_CPSR_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
#endif /* __ASSEMBLY__ */
/****************************************************************************
* Public Variables
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: arm_fpuconfig
*
* Description:
* Configure the FPU. Enables access to CP10 and CP11
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
void arm_fpuconfig(void);
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_ARMV7_A_CPSR_H */

911
arch/arm/src/armv7-a/mmu.h
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File diff suppressed because it is too large Load Diff

4
arch/arm/src/sama5/Make.defs
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@ -35,7 +35,7 @@
HEAD_ASRC = arm_head.S
CMN_ASRCS = arm_vectors.S arm_vectortab.S arm_cache.S
CMN_ASRCS = arm_vectors.S arm_vectortab.S arm_cache.S arm_fpuconfig.S
CMN_ASRCS += arm_fullcontextrestore.S arm_saveusercontext.S
CMN_ASRCS += arm_vectoraddrexcptn.S arm_vfork.S
@ -61,4 +61,4 @@ endif
CHIP_ASRCS =
CHIP_CSRCS =
CHIP_CSRCS = sam_boot.c

155
arch/arm/src/sama5/chip/sama5d3x_memorymap.h
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@ -41,7 +41,7 @@
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include <arch/sama5/chip.h>
/************************************************************************************
* Pre-processor Definitions
@ -64,8 +64,9 @@
#define SAM_BOOTMEM_PSECTION 0x00000000 /* 0x00000000-0x000fffff: Boot memory */
#define SAM_ROM_PSECTION 0x00100000 /* 0x00100000-0x001fffff: ROM */
#define SAM_NFCSRAM_PSECTION 0x00200000 /* 0x00200000-0x002fffff: NFC SRAM */
#define SAM_SRAM0_PSECTION 0x00300000 /* 0x00300000-0x0030ffff: SRAM0 */
#define SAM_SRAM1_PSECTION 0x00310000 /* 0x00310000-0x003fffff: SRAM1 */
#define SAM_ISRAM_PSECTION 0x00300000 /* 0x00300000-0x0030ffff: SRAM */
# define SAM_ISRAM0_PADDR 0x00300000 /* 0x00300000-0x0030ffff: SRAM0 */
# define SAM_ISRAM1_PADDR 0x00310000 /* 0x00310000-0x003fffff: SRAM1 */
#define SAM_SMD_PSECTION 0x00400000 /* 0x00400000-0x004fffff: SMD */
#define SAM_UDPHSRAM_PSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */
#define SAM_UHPOHCI_PSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */
@ -154,7 +155,8 @@
#define SAM_BOOTMEM_SIZE (1*1024*1024) /* 0x00000000-0x000fffff: Boot memory */
#define SAM_ROM_SIZE (1*1024*1024) /* 0x00100000-0x001fffff: ROM */
#define SAM_NFCSRAM_SIZE (1*1024*1024) /* 0x00200000-0x002fffff: NFC SRAM */
#define SAM_SRAM_SIZE (1*1024*1024) /* 0x00300000-0x0030ffff: SRAM0 and SRAM1 */
/* 0x00300000-0x003fffff: SRAM0 and SRAM1 */
#define SAM_ISRAM_SIZE (64*1024 + SAM_ISRAM1_SIZE)
#define SAM_SMD_SIZE (1*1024*1024) /* 0x00400000-0x004fffff: SMD */
#define SAM_UDPHSRAM_SIZE (1*1024*1024) /* 0x00500000-0x005fffff: UDPH SRAM */
#define SAM_UHPOHCI_SIZE (1*1024*1024) /* 0x00600000-0x006fffff: UHP OHCI */
@ -180,7 +182,7 @@
#define SAM_BOOTMEM_NSECTIONS _NSECTIONS(SAM_BOOTMEM_SIZE)
#define SAM_ROM_NSECTIONS _NSECTIONS(SAM_ROM_SIZE)
#define SAM_NFCSRAM_NSECTIONS _NSECTIONS(SAM_NFCSRAM_SIZE)
#define SAM_SRAM_NSECTION S _NSECTIONS(SAM_SRAM_SIZE)
#define SAM_ISRAM_NSECTIONS _NSECTIONS(SAM_ISRAM_SIZE)
#define SAM_SMD_NSECTIONS _NSECTIONS(SAM_SMD_SIZE)
#define SAM_UDPHSRAM_NSECTIONS _NSECTIONS(SAM_UDPHSRAM_SIZE)
#define SAM_UHPOHCI_NSECTIONS _NSECTIONS(SAM_UHPOHCI_SIZE)
@ -204,7 +206,7 @@
#define SAM_BOOTMEM_MMUFLAGS MMU_ROMFLAGS
#define SAM_ROM_MMUFLAGS MMU_ROMFLAGS
#define SAM_NFCSRAM_MMUFLAGS MMU_IOFLAGS
#define SAM_SRAM_MMUFLAGS MMU_MEMFLAGS
#define SAM_ISRAM_MMUFLAGS MMU_MEMFLAGS
#define SAM_SMD_MMUFLAGS MMU_MEMFLAGS
#define SAM_UDPHSRAM_MMUFLAGS MMU_IOFLAGS
#define SAM_UHPOHCI_MMUFLAGS MMU_IOFLAGS
@ -242,9 +244,9 @@
# define SAM_BOOTMEM_VSECTION 0x00000000 /* 0x00000000-0x000fffff: Boot memory */
# define SAM_ROM_VSECTION 0x00100000 /* 0x00100000-0x001fffff: ROM */
# define SAM_NFCSRAM_VSECTION 0x00200000 /* 0x00200000-0x002fffff: NFC SRAM */
# define SAM_SRAM_VSECTION 0x00300000 /* 0x00300000-0x0030ffff: SRAM0 */
# define SAM_SRAM0_VADDR 0x00300000 /* 0x00300000-0x0030ffff: SRAM0 */
# define SAM_SRAM1_VADDR 0x00310000 /* 0x00310000-0x003fffff: SRAM1 */
# define SAM_ISRAM_VSECTION 0x00300000 /* 0x00300000-0x0030ffff: SRAM */
# define SAM_ISRAM0_VADDR 0x00300000 /* 0x00300000-0x0030ffff: SRAM0 */
# define SAM_ISRAM1_VADDR 0x00310000 /* 0x00310000-0x003fffff: SRAM1 */
# define SAM_SMD_VSECTION 0x00400000 /* 0x00400000-0x004fffff: SMD */
# define SAM_UDPHSRAM_VSECTION 0x00500000 /* 0x00500000-0x005fffff: UDPH SRAM */
# define SAM_UHPOHCI_VSECTION 0x00600000 /* 0x00600000-0x006fffff: UHP OHCI */
@ -278,7 +280,7 @@
#elif defined(CONFIG_BOOT_RUNFROMEXTSRAM)
# define NUTTX_START_VADDR CONFIG_SAMA5_SRAM_VBASE
#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */
# define NUTTX_START_VADDR SAM_SRAM_VSECTION
# define NUTTX_START_VADDR SAM_ISRAM_VSECTION
#endif
/* Determine the address of the MMU page table. We will try to place that page
@ -308,63 +310,53 @@
# ifdef CONFIG_ARCH_ROMPGTABLE
# error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined"
# endif
/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory
* map probably do not apply because paging logic will probably partition
* the SRAM section differently. In particular, if the page table is located
* at the end of SRAM, then the virtual page table address defined below
* will probably be in error. In that case PGTABLE_BASE_VADDR is defined
* in the file mmu.h
*
* We must declare the page table in ISRAM0 or 1. We decide depending upon
* where the vector table was place.
*/
# ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
/* In this case, table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if ISRAM1
* is not available in this architecture)
*
* If CONFIG_PAGING is defined, then mmu.h assign the virtual address
* of the page table.
*/
# if SAM_ISRAM1_SIZE > 0
# define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE)
# ifndef CONFIG_PAGING
# define PGTABLE_BASE_VADDR (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE)
# endif
# else
# define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE)
# ifndef CONFIG_PAGING
# define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE)
# endif
# endif
# define PGTABLE_IN_HIGHSRAM 1
# else
/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory
* map probably do not apply because paging logic will probably partition
* the SRAM section differently. In particular, if the page table is located
* at the end of SRAM, then the virtual page table address defined below
* will probably be in error.
*
* We work around this header file interdependency by (1) insisting that
* pg_macros.h be included AFTER this header file, then (2) allowing the
* pg_macros.h header file to redefine PGTABLE_BASE_VADDR.
*/
/* Otherwise, ISRAM1 (or ISRAM0 if ISRAM1 is not available in this
* architecture) will be mapped so that the end of the SRAM region will
* provide memory for the vectors. The page table will then be places at
* the first 16Kb of ISRAM0.
*/
# if defined(CONFIG_PAGING) && defined(__ARCH_ARM_SRC_ARM_PG_MACROS_H)
# error "pg_macros.h must be included AFTER this header file"
# endif
/* We must declare the page table in ISRAM0 or 1. We decide depending upon
* where the vector table was place.
*/
# ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
/* In this case, ISRAM0 will be shadowed at address 0x0000:0000. The page
* table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if this is a ISRAM1 is
* not available in this architecture)
*/
# ifdef HAVE_INTSRAM1
# define PGTABLE_BASE_PADDR (SAM_INTSRAM1_PADDR+SAM_INTSRAM1_SIZE-PGTABLE_SIZE)
# define PGTABLE_BASE_VADDR (SAM_INTSRAM1_VADDR+SAM_INTSRAM1_SIZE-PGTABLE_SIZE)
# else
# define PGTABLE_BASE_PADDR (SAM_INTSRAM0_PADDR+SAM_INTSRAM0_SIZE-PGTABLE_SIZE)
# define PGTABLE_BASE_VADDR (SAM_INTSRAM0_VADDR+SAM_INTSRAM0_SIZE-PGTABLE_SIZE)
# endif
# define PGTABLE_IN_HIGHSRAM 1
/* If CONFIG_PAGING is defined, insist that pg_macros.h assign the virtual
* address of the page table.
*/
# ifdef CONFIG_PAGING
# undef PGTABLE_BASE_VADDR
# endif
# else
/* Otherwise, ISRAM1 (or ISRAM0 for the is ISRAM1 is not available in this
* architecture) will be mapped so that the end of the SRAM region will
* provide memory for the vectors. The page table will then be places at
* the first 16Kb of ISRAM0 (which will be in the shadow memory region).
*/
# define PGTABLE_BASE_PADDR SAM_SHADOWSPACE_PSECTION
# define PGTABLE_BASE_VADDR SAM_SHADOWSPACE_VSECTION
# define PGTABLE_IN_LOWSRAM 1
# define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR
# ifndef CONFIG_PAGING
# define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR
# endif
# define PGTABLE_IN_LOWSRAM 1
# endif
#endif
@ -374,17 +366,12 @@
* portion of this table is not accessible in the virtual address space (for
* normal operation). We will reuse this memory for coarse page tables as follows:
*
* NOTE: If CONFIG_PAGING is defined, pg_macros.h will re-assign the virtual
* address of the page table.
* NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual address
* of the page table.
*/
#define PGTABLE_L2_COARSE_OFFSET ((((SAM_LAST_PSECTION >> 20) + 255) & ~255) << 2)
#define PGTABLE_L2_COARSE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_COARSE_OFFSET)
#define PGTABLE_L2_COARSE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_COARSE_OFFSET)
#define PGTABLE_L2_FINE_OFFSET ((((SAM_LAST_PSECTION >> 20) + 1023) & ~1023) << 2)
#define PGTABLE_L2_FINE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_FINE_OFFSET)
#define PGTABLE_L2_FINE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_FINE_OFFSET)
#define PGTABLE_L2_PBASE (PGTABLE_BASE_PADDR+0x00000800)
#define PGTABLE_L2_VBASE (PGTABLE_BASE_VADDR+0x00000800)
/* Page table end addresses: */
@ -393,13 +380,9 @@
/* Page table sizes */
#define PGTABLE_L2_COARSE_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_COARSE_VBASE)
#define PGTABLE_COARSE_TABLE_SIZE (4*256)
#define PGTABLE_NCOARSE_TABLES (PGTABLE_L2_COARSE_ALLOC / PGTABLE_COARSE_TABLE_SIZE)
#define PGTABLE_L2_FINE_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_FINE_VBASE)
#define PGTABLE_FINE_TABLE_SIZE (4*1024)
#define PGTABLE_NFINE_TABLES (PGTABLE_L2_FINE_ALLOC / PGTABLE_FINE_TABLE_SIZE)
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_VBASE)
#define PGTABLE_L2_SIZE (4*256)
#define PGTABLE_L2_NENTRIES (PGTABLE_L2_ALLOC / PGTABLE_L2_SIZE)
/* Determine the base address of the vector table:
*
@ -410,17 +393,17 @@
#define VECTOR_TABLE_SIZE 0x00010000
#ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
# define SAM_VECTOR_PADDR SAM_INTSRAM0_PADDR
# define SAM_VECTOR_VSRAM SAM_INTSRAM0_VADDR
# define SAM_VECTOR_PADDR SAM_ISRAM0_PADDR
# define SAM_VECTOR_VSRAM SAM_ISRAM0_VADDR
# define SAM_VECTOR_VADDR 0x00000000
# define SAM_VECTOR_VCOARSE 0x00000000
#else /* Vectors located at 0xffff:0000 -- this probably does not work */
# ifdef HAVE_INTSRAM1
# define SAM_VECTOR_PADDR (SAM_INTSRAM1_PADDR+SAM_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_VSRAM (SAM_INTSRAM1_VADDR+SAM_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
# ifdef HAVE_ISRAM1
# define SAM_VECTOR_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_VSRAM (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-VECTOR_TABLE_SIZE)
# else
# define SAM_VECTOR_PADDR (SAM_INTSRAM0_PADDR+SAM_INTSRAM0_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_VSRAM (SAM_INTSRAM0_VADDR+SAM_INTSRAM0_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
# define SAM_VECTOR_VSRAM (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-VECTOR_TABLE_SIZE)
# endif
# define SAM_VECTOR_VADDR 0xffff0000
# define SAM_VECTOR_VCOARSE 0xfff00000

420
arch/arm/src/sama5/sam_boot.c Normal file
View File

@ -0,0 +1,420 @@
/************************************************************************************
* arch/arm/src/sama5/sam_boot.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#ifdef CONFIG_PAGING
# include <nuttx/page.h>
#endif
#include <arch/board/board.h>
#include "chip.h"
#include "arm.h"
#include "mmu.h"
#include "fpu.h"
#include "up_internal.h"
#include "up_arch.h"
#include "sam_clockconfig.h"
#include "sam_lowputc.h"
/************************************************************************************
* Private Types
************************************************************************************/
/************************************************************************************
* Private Types
************************************************************************************/
struct section_mapping_s
{
uint32_t physbase; /* Physical address of the region to be mapped */
uint32_t virtbase; /* Virtual address of the region to be mapped */
uint32_t mmuflags; /* MMU settings for the region (e.g., cache-able) */
uint32_t nsections; /* Number of mappings in the region */
};
/************************************************************************************
* Public Variables
************************************************************************************/
extern uint32_t _vector_start; /* Beginning of vector block */
extern uint32_t _vector_end; /* End+1 of vector block */
/************************************************************************************
* Private Variables
************************************************************************************/
/* This table describes how to map a set of 1Mb pages to space the physical address
* space of the SAMA5.
*/
#ifndef CONFIG_ARCH_ROMPGTABLE
static const struct section_mapping_s section_mapping[] =
{
/* SAMA5 Internal Memories */
#ifndef CONFIG_ARCH_LOWVECTORS
{ SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION,
SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS},
#endif
{ SAM_ROM_PSECTION, SAM_ROM_VSECTION,
SAM_ROM_MMUFLAGS, SAM_ROM_NSECTIONS},
{ SAM_NFCSRAM_PSECTION, SAM_NFCSRAM_VSECTION,
SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS},
#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */
{ SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION,
SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS},
#endif
{ SAM_SMD_PSECTION, SAM_SMD_VSECTION,
SAM_SMD_MMUFLAGS, SAM_SMD_NSECTIONS},
{ SAM_UDPHSRAM_PSECTION, SAM_UDPHSRAM_VSECTION,
SAM_UDPHSRAM_MMUFLAGS, SAM_UDPHSRAM_NSECTIONS},
{ SAM_UHPOHCI_PSECTION, SAM_UHPOHCI_VSECTION,
SAM_UHPOHCI_MMUFLAGS, SAM_UHPOHCI_NSECTIONS},
{ SAM_UHPEHCI_PSECTION, SAM_UHPEHCI_VSECTION,
SAM_UHPEHCI_MMUFLAGS, SAM_UHPEHCI_NSECTIONS},
{ SAM_AXIMATRIX_PSECTION, SAM_AXIMATRIX_VSECTION,
SAM_AXIMATRIX_MMUFLAGS, SAM_AXIMATRIX_NSECTIONS},
{ SAM_DAP_PSECTION, SAM_DAP_VSECTION,
SAM_DAP_MMUFLAGS, SAM_DAP_NSECTIONS},
/* SAMA5 External Memories */
#ifdef CONFIG_SAMA5_EBISC0
{ SAM_EBICS0_PSECTION, SAM_EBICS0_VSECTION,
SAM_EBICS0_MMUFLAGS, SAM_EBICS0_NSECTIONS},
#endif
#ifdef CONFIG_SAMA5_DDRCS
{ SAM_DDRCS_PSECTION, SAM_DDRCS_VSECTION,
SAM_DDRCS_MMUFLAGS, SAM_DDRCS_NSECTIONS},
#endif
#ifdef CONFIG_SAMA5_EBISC1
{ SAM_EBICS1_PSECTION, SAM_EBICS1_VSECTION,
SAM_EBICS1_MMUFLAGS, SAM_EBICS1_NSECTIONS},
#endif
#ifdef CONFIG_SAMA5_EBISC2
{ SAM_EBICS2_PSECTION, SAM_EBICS2_VSECTION,
SAM_EBICS2_MMUFLAGS, SAM_EBICS2_NSECTIONS},
#endif
#ifdef CONFIG_SAMA5_EBISC3
{ SAM_EBICS3_PSECTION, SAM_EBICS3_VSECTION,
SAM_EBICS3_MMUFLAGS, SAM_EBICS3_NSECTIONS},
#endif
#ifdef CONFIG_SAMA5_NFCCR
{ SAM_NFCCR_PSECTION, SAM_NFCCR_VSECTION,
SAM_NFCCR_MMUFLAGS, SAM_NFCCR_NSECTIONS},
#endif
/* SAMA5 Internal Peripherals */
{ SAM_PERIPHA_PSECTION, SAM_PERIPHA_VSECTION,
SAM_PERIPHA_MMUFLAGS, SAM_PERIPHA_NSECTIONS},
{ SAM_PERIPHB_PSECTION, SAM_PERIPHB_VSECTION,
SAM_PERIPHB_MMUFLAGS, SAM_PERIPHB_NSECTIONS},
{ SAM_SYSC_PSECTION, SAM_SYSC_VSECTION,
SAM_SYSC_MMUFLAGS, SAM_SYSC_NSECTIONS},
};
#define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s))
#endif
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: sam_setlevel1entry
************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
static inline void sam_setlevel1entry(uint32_t paddr, uint32_t vaddr,
uint32_t mmuflags)
{
uint32_t *pgtable = (uint32_t*)PGTABLE_BASE_VADDR;
uint32_t index = vaddr >> 20;
/* Save the page table entry */
pgtable[index] = (paddr | mmuflags);
}
#endif
/************************************************************************************
* Name: sam_setlevel2coarseentry
************************************************************************************/
static inline void sam_setlevel2coarseentry(uint32_t ctabvaddr, uint32_t paddr,
uint32_t vaddr, uint32_t mmuflags)
{
uint32_t *ctable = (uint32_t*)ctabvaddr;
uint32_t index;
/* The table divides a 1Mb address space up into 256 entries, each
* corresponding to 4Kb of address space. The page table index is
* related to the offset from the beginning of 1Mb region.
*/
index = (vaddr & 0x000ff000) >> 12;
/* Save the table entry */
ctable[index] = (paddr | mmuflags);
}
/************************************************************************************
* Name: sam_setupmappings
************************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
static void sam_setupmappings(void)
{
int i, j;
for (i = 0; i < NMAPPINGS; i++)
{
uint32_t sect_paddr = section_mapping[i].physbase;
uint32_t sect_vaddr = section_mapping[i].virtbase;
uint32_t mmuflags = section_mapping[i].mmuflags;
for (j = 0; j < section_mapping[i].nsections; j++)
{
sam_setlevel1entry(sect_paddr, sect_vaddr, mmuflags);
sect_paddr += SECTION_SIZE;
sect_vaddr += SECTION_SIZE;
}
}
}
#endif
/************************************************************************************
* Name: sam_vectorpermissions
*
* Description:
* Set permissions on the vector mapping.
*
************************************************************************************/
#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING)
static void sam_vectorpermissions(uint32_t mmuflags)
{
/* The PTE for the beginning of ISRAM is at the base of the L2 page table */
uint32_t *ptr = (uint32_t*)PG_L2_VECT_VADDR;
uint32_t pte;
/* The pte might be zero the first time this function is called. */
pte = *ptr;
if (pte == 0)
{
pte = PG_VECT_PBASE;
}
else
{
pte &= PG_L1_PADDRMASK;
}
/* Update the MMU flags and save */
*ptr = pte | mmuflags;
/* Invalid the TLB for this address */
tlb_invalidate_single(PG_L2_VECT_VADDR);
}
#endif
/************************************************************************************
* Name: sam_vectormapping
*
* Description:
* Setup a special mapping for the interrupt vectors when (1) the interrupt
* vectors are not positioned in ROM, and when (2) the interrupt vectors are
* located at the high address, 0xffff0000. When the interrupt vectors are located
* in ROM, we just have to assume that they were set up correctly; When vectors
* are located in low memory, 0x00000000, the shadow memory region will be mapped
* to support them.
*
************************************************************************************/
#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_ARCH_LOWVECTORS)
static void sam_vectormapping(void)
{
uint32_t vector_paddr = SAM_VECTOR_PADDR;
uint32_t vector_vaddr = SAM_VECTOR_VADDR;
uint32_t end_paddr = vector_paddr + VECTOR_TABLE_SIZE;
/* We want to keep our interrupt vectors and interrupt-related logic in zero-wait
* state internal RAM (IRAM). The DM320 has 16Kb of IRAM positioned at physical
* address 0x0000:0000; we need to map this to 0xffff:0000.
*/
while (vector_paddr < end_paddr)
{
sam_setlevel2coarseentry(PGTABLE_L2_VBASE, vector_paddr,
vector_vaddr, MMU_L2_VECTORFLAGS);
vector_paddr += 4096;
vector_vaddr += 4096;
}
/* Now set the level 1 descriptor to refer to the level 2 page table. */
sam_setlevel1entry(PGTABLE_L2_PBASE, SAM_VECTOR_VCOARSE,
MMU_L1_VECTORFLAGS);
}
#endif
/************************************************************************************
* Name: sam_copyvectorblock
*
* Description:
* Copy the interrupt block to its final destination.
*
************************************************************************************/
static void sam_copyvectorblock(void)
{
uint32_t *src;
uint32_t *end;
uint32_t *dest;
/* If we are using vectors in low memory but RAM in that area has been marked
* read only, then temparily mark the mapping write-able (non-buffered).
*/
#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING)
sam_vectorpermissions(MMU_L2_VECTRWFLAGS);
#endif
/* Copy the vectors into ISRAM at the address that will be mapped to the vector
* address:
*
* SAM_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
* SAM_VECTOR_VSRAM - Virtual address of vector table in SRAM
* SAM_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
*/
src = (uint32_t*)&_vector_start;
end = (uint32_t*)&_vector_end;
dest = (uint32_t*)SAM_VECTOR_VSRAM;
while (src < end)
{
*dest++ = *src++;
}
/* Make the vectors read-only, cacheable again */
#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING)
sam_vectorpermissions(MMU_L2_VECTROFLAGS);
#endif
}
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: up_boot
*
* Description:
* Complete boot operations started in arm_head.S
*
************************************************************************************/
void up_boot(void)
{
/* __start provided the basic MMU mappings for SRAM. Now provide mappings for all
* IO regions (Including the vector region).
*/
#ifndef CONFIG_ARCH_ROMPGTABLE
sam_setupmappings();
/* Provide a special mapping for the IRAM interrupt vector positioned in high
* memory.
*/
#ifndef CONFIG_ARCH_LOWVECTORS
sam_vectormapping();
#endif
#endif /* CONFIG_ARCH_ROMPGTABLE */
/* Setup up vector block. _vector_start and _vector_end are exported from
* arm_vector.S
*/
sam_copyvectorblock();
/* Initialize clocking to settings provided by board-specific logic */
sam_clockconfig();
/* Initialize the FPU */
#ifdef CONFIG_ARCH_FPU
arm_fpuconfig();
#endif
/* Perform common, low-level chip initialization (might do nothing) */
sam_lowsetup();
/* Perform early serial initialization if we are going to use the serial driver */
#ifdef USE_EARLYSERIALINIT
sam_earlyserialinit();
#endif
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_NUTTX_KERNEL
sam_userspace();
#endif
/* Perform board-specific initialization */
sam_boardinitialize();
}

94
arch/arm/src/sama5/sam_clockconfig.h Normal file
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@ -0,0 +1,94 @@
/************************************************************************************
* arch/arm/src/sama5/sam_clockconfig.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_SAMA5_SAM_CLOCKCONFIG_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: sam_clockconfig
*
* Description:
* Called to initialize the SAM3/4. This does whatever setup is needed to put the
* SoC in a usable state. This includes the initialization of clocking using the
* settings in board.h.
*
************************************************************************************/
void sam_clockconfig(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_CLOCKCONFIG_H */

102
arch/arm/src/sama5/sam_lowputc.h Normal file
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@ -0,0 +1,102 @@
/************************************************************************************
* arch/arm/src/sama5/sam_lowputc.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_SAM_LOWPUTC_H
#define __ARCH_ARM_SRC_SAMA5_SAM_LOWPUTC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "up_internal.h"
#include "chip.h"
/************************************************************************************
* Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
/************************************************************************************
* Name: sam_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level initialization
* including setup of the console UART. This UART done early so that the serial
* console is available for debugging very early in the boot sequence.
*
************************************************************************************/
void sam_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAMA5_SAM_LOWPUTC_H */

5
configs/sama5d3x-ek/README.txt
View File

@ -48,11 +48,10 @@ Development Environment
GNU Toolchain Options
^^^^^^^^^^^^^^^^^^^^^
The NuttX make system has been modified to support the several different
toolchain options.
The NuttX make system will support the several different toolchain options.
All testing has been conducted using the AtmelStudio GCC toolchain. To use
the CodeSourcery, devkitARM or Raisonance GNU toolchain, you simply need to
the CodeSourcery, devkitARM or other GNU toolchain, you simply need to add
add one of the following configuration options to your .config (or defconfig)
file:

4
configs/sama5d3x-ek/ostest/setenv.sh
View File

@ -50,12 +50,12 @@ fi
# This is the Cygwin path to the location where I installed the Atmel GCC
# toolchain under Windows. You will also have to edit this if you install
# this toolchain in any other location
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin"
export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin"
# This is the Cygwin path to the location where I installed the CodeSourcery
# toolchain under windows. You will also have to edit this if you install
# the CodeSourcery toolchain in any other location
export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
# These are the Cygwin paths to the locations where I installed the Atollic
# toolchain under windows. You will also have to edit this if you install

107
configs/sama5d3x-ek/src/sam_autoleds.c Normal file
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@ -0,0 +1,107 @@
/****************************************************************************
* configs/sama5d3x-ek/src/sam_autoleds.c
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include <debug.h>
#include <arch/board/board.h>
#include "sama5d3x-ek.h"
#ifdef CONFIG_ARCH_LEDS
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* CONFIG_DEBUG_LEDS enables debug output from this file (needs CONFIG_DEBUG
* with CONFIG_DEBUG_VERBOSE too)
*/
#ifdef CONFIG_DEBUG_LEDS
# define leddbg lldbg
# define ledvdbg llvdbg
#else
# define leddbg(x...)
# define ledvdbg(x...)
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_ledinit
****************************************************************************/
void up_ledinit(void)
{
# warning Missing logic
}
/****************************************************************************
* Name: up_ledon
****************************************************************************/
void up_ledon(int led)
{
# warning Missing logic
}
/****************************************************************************
* Name: up_ledoff
****************************************************************************/
void up_ledoff(int led)
{
# warning Missing logic
}
#endif /* CONFIG_ARCH_LEDS */