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Merge branch 'master' of bitbucket.org:pnb990/nuttx-kernel-arch

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This commit is contained in:
pnb 2015-12-22 16:32:19 +01:00
commit 54b275ec09
4 changed files with 313 additions and 251 deletions
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39
arch/arm/src/stm32/Kconfig
View File

@ -1433,6 +1433,7 @@ config STM32_STM32F407
select STM32_HAVE_UART5 select STM32_HAVE_UART5
select STM32_HAVE_USART6 select STM32_HAVE_USART6
select STM32_HAVE_TIM1 select STM32_HAVE_TIM1
select STM32_HAVE_TIM2
select STM32_HAVE_TIM5 select STM32_HAVE_TIM5
select STM32_HAVE_TIM6 select STM32_HAVE_TIM6
select STM32_HAVE_TIM7 select STM32_HAVE_TIM7
@ -1603,6 +1604,10 @@ config STM32_HAVE_TIM1
bool bool
default n default n
config STM32_HAVE_TIM2
bool
default n
config STM32_HAVE_TIM3 config STM32_HAVE_TIM3
bool bool
default n default n
@ -5121,17 +5126,7 @@ config STM32_TIM14_DAC2
endchoice endchoice
config STM32_TIM1_CAP config STM32_TIM1_CAP
bool "TIM1 Capture bool "TIM1 Capture"
default n
depends on STM32_HAVE_TIM1
---help---
Reserve timer 1 for use by Capture
Timer devices may be used for different purposes. One special purpose is
to capture input.
config STM32_TIM1_CAP
bool "TIM1 Capture
default n default n
depends on STM32_HAVE_TIM1 depends on STM32_HAVE_TIM1
---help--- ---help---
@ -5141,7 +5136,7 @@ config STM32_TIM1_CAP
to capture input. to capture input.
config STM32_TIM2_CAP config STM32_TIM2_CAP
bool "TIM2 Capture bool "TIM2 Capture"
default n default n
depends on STM32_HAVE_TIM2 depends on STM32_HAVE_TIM2
---help--- ---help---
@ -5151,7 +5146,7 @@ config STM32_TIM2_CAP
to capture input. to capture input.
config STM32_TIM3_CAP config STM32_TIM3_CAP
bool "TIM3 Capture bool "TIM3 Capture"
default n default n
depends on STM32_HAVE_TIM3 depends on STM32_HAVE_TIM3
---help--- ---help---
@ -5161,7 +5156,7 @@ config STM32_TIM3_CAP
to capture input. to capture input.
config STM32_TIM4_CAP config STM32_TIM4_CAP
bool "TIM4 Capture bool "TIM4 Capture"
default n default n
depends on STM32_HAVE_TIM4 depends on STM32_HAVE_TIM4
---help--- ---help---
@ -5171,7 +5166,7 @@ config STM32_TIM4_CAP
to capture input. to capture input.
config STM32_TIM5_CAP config STM32_TIM5_CAP
bool "TIM5 Capture bool "TIM5 Capture"
default n default n
depends on STM32_HAVE_TIM5 depends on STM32_HAVE_TIM5
---help--- ---help---
@ -5181,7 +5176,7 @@ config STM32_TIM5_CAP
to capture input. to capture input.
config STM32_TIM8_CAP config STM32_TIM8_CAP
bool "TIM8 Capture bool "TIM8 Capture"
default n default n
depends on STM32_HAVE_TIM8 depends on STM32_HAVE_TIM8
---help--- ---help---
@ -5191,7 +5186,7 @@ config STM32_TIM8_CAP
to capture input. to capture input.
config STM32_TIM9_CAP config STM32_TIM9_CAP
bool "TIM9 Capture bool "TIM9 Capture"
default n default n
depends on STM32_HAVE_TIM9 depends on STM32_HAVE_TIM9
---help--- ---help---
@ -5201,7 +5196,7 @@ config STM32_TIM9_CAP
to capture input. to capture input.
config STM32_TIM10_CAP config STM32_TIM10_CAP
bool "TIM10 Capture bool "TIM10 Capture"
default n default n
depends on STM32_HAVE_TIM10 depends on STM32_HAVE_TIM10
---help--- ---help---
@ -5211,7 +5206,7 @@ config STM32_TIM10_CAP
to capture input. to capture input.
config STM32_TIM11_CAP config STM32_TIM11_CAP
bool "TIM11 Capture bool "TIM11 Capture"
default n default n
depends on STM32_HAVE_TIM11 depends on STM32_HAVE_TIM11
---help--- ---help---
@ -5221,7 +5216,7 @@ config STM32_TIM11_CAP
to capture input. to capture input.
config STM32_TIM12_CAP config STM32_TIM12_CAP
bool "TIM12 Capture bool "TIM12 Capture"
default n default n
depends on STM32_HAVE_TIM12 depends on STM32_HAVE_TIM12
---help--- ---help---
@ -5231,7 +5226,7 @@ config STM32_TIM12_CAP
to capture input. to capture input.
config STM32_TIM13_CAP config STM32_TIM13_CAP
bool "TIM13 Capture bool "TIM13 Capture"
default n default n
depends on STM32_HAVE_TIM13 depends on STM32_HAVE_TIM13
---help--- ---help---
@ -5241,7 +5236,7 @@ config STM32_TIM13_CAP
to capture input. to capture input.
config STM32_TIM14_CAP config STM32_TIM14_CAP
bool "TIM14 Capture bool "TIM14 Capture"
default n default n
depends on STM32_HAVE_TIM14 depends on STM32_HAVE_TIM14
---help--- ---help---

2
arch/arm/src/stm32/Make.defs
View File

@ -112,6 +112,7 @@ CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c
CHIP_CSRCS += stm32_dma.c stm32_lowputc.c stm32_serial.c stm32_spi.c CHIP_CSRCS += stm32_dma.c stm32_lowputc.c stm32_serial.c stm32_spi.c
CHIP_CSRCS += stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c stm32_uid.c CHIP_CSRCS += stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c stm32_uid.c
CHIP_CSRCS += stm32_capture.c
ifeq ($(CONFIG_TIMER),y) ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32_tim_lowerhalf.c CHIP_CSRCS += stm32_tim_lowerhalf.c
@ -230,6 +231,7 @@ ifeq ($(CONFIG_QENCODER),y)
CHIP_CSRCS += stm32_qencoder.c CHIP_CSRCS += stm32_qencoder.c
endif endif
ifeq ($(CONFIG_CAN),y) ifeq ($(CONFIG_CAN),y)
CHIP_CSRCS += stm32_can.c CHIP_CSRCS += stm32_can.c
endif endif

479
arch/arm/src/stm32/stm32_capture.c
View File

@ -87,7 +87,14 @@
#endif #endif
#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM1_CAP) #if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM1_CAP)
#define HAVE_ADANCED_TIM 1 #define USE_ADVENCED_TIM 1
#endif
#if defined(GPIO_TIM1_EXT_CLK_IN) || defined(GPIO_TIM2_EXT_CLK_IN) || \
defined(GPIO_TIM3_EXT_CLK_IN) || defined(GPIO_TIM4_EXT_CLK_IN) || \
defined(GPIO_TIM5_EXT_CLK_IN) || defined(GPIO_TIM8_EXT_CLK_IN) || \
defined(GPIO_TIM9_EXT_CLK_IN) || defined(GPIO_TIM12_EXT_CLK_IN)
# define USE_EXT_CLOCK 1
#endif #endif
/* This module then only compiles if there are enabled timers that are not intended for /* This module then only compiles if there are enabled timers that are not intended for
@ -110,8 +117,11 @@ struct stm32_cap_priv_s
{ {
const struct stm32_cap_ops_s *ops; const struct stm32_cap_ops_s *ops;
const uint32_t base; /* TIMn base address */ const uint32_t base; /* TIMn base address */
#ifdef USE_EXT_CLOCK
const uint32_t gpio_clk; /* TIMn base address */
#endif
const int irq; /* irq vector */ const int irq; /* irq vector */
#define HAVE_ADANCED_TIM 1 #ifdef USE_ADVENCED_TIM
const int irq_of; /* irq timer overflow is deferent in advanced timer */ const int irq_of; /* irq timer overflow is deferent in advanced timer */
#endif #endif
}; };
@ -122,7 +132,7 @@ struct stm32_cap_priv_s
/* Get a 16-bit register value by offset */ /* Get a 16-bit register value by offset */
static inline uint16_t stm32_getreg16(FAR struct stm32_cap_priv_s *priv, static inline uint16_t stm32_getreg16(FAR const struct stm32_cap_priv_s *priv,
uint8_t offset) uint8_t offset)
{ {
return getreg16(priv->base + offset); return getreg16(priv->base + offset);
@ -130,7 +140,7 @@ static inline uint16_t stm32_getreg16(FAR struct stm32_cap_priv_s *priv,
/* Put a 16-bit register value by offset */ /* Put a 16-bit register value by offset */
static inline void stm32_putreg16(FAR struct stm32_cap_priv_s *priv, uint8_t offset, static inline void stm32_putreg16(FAR const struct stm32_cap_priv_s *priv, uint8_t offset,
uint16_t value) uint16_t value)
{ {
putreg16(value, priv->base + offset); putreg16(value, priv->base + offset);
@ -138,7 +148,7 @@ static inline void stm32_putreg16(FAR struct stm32_cap_priv_s *priv, uint8_t off
/* Modify a 16-bit register value by offset */ /* Modify a 16-bit register value by offset */
static inline void stm32_modifyreg16(FAR struct stm32_cap_priv_s *priv, static inline void stm32_modifyreg16(FAR const struct stm32_cap_priv_s *priv,
uint8_t offset, uint16_t clearbits, uint8_t offset, uint16_t clearbits,
uint16_t setbits) uint16_t setbits)
{ {
@ -149,7 +159,7 @@ static inline void stm32_modifyreg16(FAR struct stm32_cap_priv_s *priv,
* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
*/ */
static inline uint32_t stm32_getreg32(FAR struct stm32_cap_priv_s *priv, static inline uint32_t stm32_getreg32(FAR const struct stm32_cap_priv_s *priv,
uint8_t offset) uint8_t offset)
{ {
return getreg32(priv->base + offset); return getreg32(priv->base + offset);
@ -159,7 +169,7 @@ static inline uint32_t stm32_getreg32(FAR struct stm32_cap_priv_s *priv,
* 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5.
*/ */
static inline void stm32_putreg32(FAR struct stm32_cap_priv_s *priv, uint8_t offset, static inline void stm32_putreg32(FAR const struct stm32_cap_priv_s *priv, uint8_t offset,
uint32_t value) uint32_t value)
{ {
putreg32(value, priv->base + offset); putreg32(value, priv->base + offset);
@ -169,8 +179,8 @@ static inline void stm32_putreg32(FAR struct stm32_cap_priv_s *priv, uint8_t off
/************************************************************************************ /************************************************************************************
* gpio Functions * gpio Functions
************************************************************************************/ ************************************************************************************/
#define GPIO_CLK -1
static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int channel) static inline uint32_t stm32_cap_gpio(FAR const struct stm32_cap_priv_s *priv, int channel)
{ {
switch(priv->base) switch(priv->base)
@ -179,6 +189,9 @@ static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int cha
case STM32_TIM1_BASE: case STM32_TIM1_BASE:
switch (channel) switch (channel)
{ {
#ifdef GPIO_TIM1_EXT_CLK_IN
case GPIO_CLK: return GPIO_TIM1_EXT_CLK_IN;
#endif
#if defined(GPIO_TIM1_CH1IN) #if defined(GPIO_TIM1_CH1IN)
case 0: return GPIO_TIM1_CH1IN; case 0: return GPIO_TIM1_CH1IN;
#endif #endif
@ -198,6 +211,9 @@ static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int cha
case STM32_TIM2_BASE: case STM32_TIM2_BASE:
switch (channel) switch (channel)
{ {
#ifdef GPIO_TIM2_EXT_CLK_IN
case GPIO_CLK: return GPIO_TIM2_EXT_CLK_IN;
#endif
#if defined(GPIO_TIM2_CH1IN) #if defined(GPIO_TIM2_CH1IN)
case 0: return GPIO_TIM2_CH1IN; case 0: return GPIO_TIM2_CH1IN;
#endif #endif
@ -217,6 +233,9 @@ static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int cha
case STM32_TIM3_BASE: case STM32_TIM3_BASE:
switch (channel) switch (channel)
{ {
#ifdef GPIO_TIM3_EXT_CLK_IN
case GPIO_CLK: return GPIO_TIM3_EXT_CLK_IN;
#endif
#if defined(GPIO_TIM3_CH1IN) #if defined(GPIO_TIM3_CH1IN)
case 0: return GPIO_TIM3_CH1IN; case 0: return GPIO_TIM3_CH1IN;
#endif #endif
@ -236,6 +255,9 @@ static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int cha
case STM32_TIM4_BASE: case STM32_TIM4_BASE:
switch (channel) switch (channel)
{ {
#ifdef GPIO_TIM4_EXT_CLK_IN
case GPIO_CLK: return GPIO_TIM4_EXT_CLK_IN;
#endif
#if defined(GPIO_TIM4_CH1IN) #if defined(GPIO_TIM4_CH1IN)
case 0: return GPIO_TIM4_CH1IN; case 0: return GPIO_TIM4_CH1IN;
#endif #endif
@ -255,6 +277,9 @@ static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int cha
case STM32_TIM5_BASE: case STM32_TIM5_BASE:
switch (channel) switch (channel)
{ {
#ifdef GPIO_TIM5_EXT_CLK_IN
case GPIO_CLK: return GPIO_TIM5_EXT_CLK_IN;
#endif
#if defined(GPIO_TIM5_CH1IN) #if defined(GPIO_TIM5_CH1IN)
case 0: return GPIO_TIM5_CH1IN; case 0: return GPIO_TIM5_CH1IN;
#endif #endif
@ -275,6 +300,9 @@ static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int cha
case STM32_TIM8_BASE: case STM32_TIM8_BASE:
switch (channel) switch (channel)
{ {
#ifdef GPIO_TIM8_EXT_CLK_IN
case GPIO_CLK: return GPIO_TIM8_EXT_CLK_IN;
#endif
#if defined(GPIO_TIM8_CH1IN) #if defined(GPIO_TIM8_CH1IN)
case 0: return GPIO_TIM8_CH1OUIN ; case 0: return GPIO_TIM8_CH1OUIN ;
#endif #endif
@ -291,16 +319,110 @@ static inline uint32_t stm32_cap_gpio(FAR struct stm32_cap_priv_s *priv, int cha
break; break;
#endif #endif
} }
return gpio; return 0;
}
static inline int stm32_cap_set_rcc(FAR const struct stm32_cap_priv_s *priv,
bool on)
{
uint32_t offset = 0;
uint32_t mask = 0;
switch (priv->base)
{
#ifdef CONFIG_STM32_TIM1_CAP
case 1:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM1EN;
break;
#endif
#ifdef CONFIG_STM32_TIM2_CAP
case 2:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM2EN;
break;
#endif
#ifdef CONFIG_STM32_TIM3_CAP
case 3:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM3EN;
break;
#endif
#ifdef CONFIG_STM32_TIM4_CAP
case 4:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM4EN;
break;
#endif
#ifdef CONFIG_STM32_TIM5_CAP
case 5:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB1ENR_TIM5EN;
break;
#endif
/* TIM6 and TIM7 cannot be used in cap */
#ifdef CONFIG_STM32_TIM8_CAP
case 8:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM8EN;
break;
#endif
#ifdef CONFIG_STM32_TIM9_CAP
case 9:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM9EN;
break;
#endif
#ifdef CONFIG_STM32_TIM10_CAP
case 10:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM10EN;
break;
#endif
#ifdef CONFIG_STM32_TIM11_CAP
case 11:
offset = STM32_RCC_APB2ENR;
mask = RCC_APB2ENR_TIM11EN;
break;
#endif
#ifdef CONFIG_STM32_TIM12_CAP
case 12:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB2ENR_TIM12EN;
break;
#endif
#ifdef CONFIG_STM32_TIM13_CAP
case 13:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB2ENR_TIM13EN;
break;
#endif
#ifdef CONFIG_STM32_TIM14_CAP
case 14:
offset = STM32_RCC_APB1ENR;
mask = RCC_APB2ENR_TIM14EN;
break;
#endif
}
if ( mask == 0 )
return ERROR;
if ( on )
modifyreg32(offset, 0, mask);
else
modifyreg32(offset, mask, 0);
return OK;
} }
/************************************************************************************ /************************************************************************************
* Basic Functions * Basic Functions
************************************************************************************/ ************************************************************************************/
static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src_t clk_src, static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t clk,
uint32_t prescaler) uint32_t prescaler,uint32_t max)
{ {
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint16_t regval = 0; uint16_t regval = 0;
if (prescaler == 0) if (prescaler == 0)
@ -321,14 +443,14 @@ static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src
prescaler = 0xffff; prescaler = 0xffff;
switch(clk_src) switch(clk)
{ {
case STM32_CAP_CLK_INT: case STM32_CAP_CLK_INT:
regval = GTIM_SMCR_DISAB; regval = GTIM_SMCR_DISAB;
break; break;
case STM32_CAP_CLK_EXT: case STM32_CAP_CLK_EXT:
regval = GTIM_SMCR_EXTCLK1 regval = GTIM_SMCR_EXTCLK1;
break; break;
/* TODO: Add other case */ /* TODO: Add other case */
@ -340,7 +462,7 @@ static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src
stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, GTIM_SMCR_SMS_MASK, regval ); stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, GTIM_SMCR_SMS_MASK, regval );
// Set Maximum // Set Maximum
stm32_putreg32(priv, STM32_BTIM_ARR_OFFSET, period); stm32_putreg32(priv, STM32_BTIM_ARR_OFFSET, max);
// Set prescaler // Set prescaler
stm32_putreg16(priv, STM32_BTIM_PSC_OFFSET, prescaler); stm32_putreg16(priv, STM32_BTIM_PSC_OFFSET, prescaler);
@ -351,7 +473,7 @@ static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src
//enable timer //enable timer
stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET,0,BTIM_CR1_CEN); stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET,0,BTIM_CR1_CEN);
#ifdef HAVE_ADANCED_TIM #ifdef USE_ADVENCED_TIM
/* Advanced registers require Main Output Enable */ /* Advanced registers require Main Output Enable */
if ((priv->base == STM32_TIM1_BASE) || (priv->base == STM32_TIM8_BASE)) if ((priv->base == STM32_TIM1_BASE) || (priv->base == STM32_TIM8_BASE))
{ {
@ -362,18 +484,18 @@ static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src
return prescaler; return prescaler;
} }
static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler); static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler)
{ {
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
int irq; int irq;
#ifdef HAVE_ADANCED_TIM #ifdef USE_ADVENCED_TIM
int irq_of; int irq_of;
#endif #endif
ASSERT(dev); ASSERT(dev);
irq = priv->irq; irq = priv->irq;
#ifdef HAVE_ADANCED_TIM #ifdef USE_ADVENCED_TIM
irq_of = priv->irq_of; irq_of = priv->irq_of;
#endif #endif
@ -383,7 +505,7 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler);
{ {
up_disable_irq(irq); up_disable_irq(irq);
irq_detach(irq); irq_detach(irq);
#ifdef HAVE_ADANCED_TIM #ifdef USE_ADVENCED_TIM
if (priv->irq_of) if (priv->irq_of)
{ {
up_disable_irq(irq_of); up_disable_irq(irq_of);
@ -398,7 +520,7 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler);
irq_attach(irq, handler); irq_attach(irq, handler);
up_enable_irq(irq); up_enable_irq(irq);
#ifdef HAVE_ADANCED_TIM #ifdef USE_ADVENCED_TIM
if (priv->irq_of) if (priv->irq_of)
{ {
irq_attach(priv->irq_of, handler); irq_attach(priv->irq_of, handler);
@ -411,7 +533,7 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler);
up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT); up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT);
# ifdef HAVE_ADANCED_TIM # ifdef USE_ADVENCED_TIM
if (priv->irq_of) if (priv->irq_of)
{ {
up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT); up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT);
@ -427,20 +549,20 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler);
static void stm32_cap_enableint(FAR struct stm32_cap_dev_s *dev, static void stm32_cap_enableint(FAR struct stm32_cap_dev_s *dev,
stm32_cap_flags_t src, bool on) stm32_cap_flags_t src, bool on)
{ {
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint16_t mask; uint16_t mask = 0;
ASSERT(dev); ASSERT(dev);
if (src & STM32_TIM_FLAG_IRQ_OVERFLOW) if (src & STM32_CAP_FLAG_IRG_COUNTER)
regval |= ATIM_DIER_UIE; mask |= ATIM_DIER_UIE;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_1) if (src & STM32_CAP_FLAG_IRQ_CH_1)
regval |= ATIM_DIER_CC1IE; mask |= ATIM_DIER_CC1IE;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_2) if (src & STM32_CAP_FLAG_IRQ_CH_2)
regval |= ATIM_DIER_CC1IE; mask |= ATIM_DIER_CC1IE;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_3) if (src & STM32_CAP_FLAG_IRQ_CH_3)
regval |= ATIM_DIER_CC1IE; mask |= ATIM_DIER_CC1IE;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_4) if (src & STM32_CAP_FLAG_IRQ_CH_4)
regval |= ATIM_DIER_CC1IE; mask |= ATIM_DIER_CC1IE;
/* Not IRQ on channel overflow */ /* Not IRQ on channel overflow */
@ -451,66 +573,66 @@ static void stm32_cap_enableint(FAR struct stm32_cap_dev_s *dev,
} }
static void stm32_cap_ackflags(FAR struct stm32_cap_dev_s *dev, int src) static void stm32_cap_ackflags(FAR struct stm32_cap_dev_s *dev, int flags)
{ {
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint16_t mask = 0; uint16_t mask = 0;
if (src & STM32_TIM_FLAG_IRQ_OVERFLOW) if (flags & STM32_CAP_FLAG_IRG_COUNTER)
regval |= ATIM_SR_UIF; mask |= ATIM_SR_UIF;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_1) if (flags & STM32_CAP_FLAG_IRQ_CH_1)
regval |= ATIM_SR_CC1IF; mask |= ATIM_SR_CC1IF;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_2) if (flags & STM32_CAP_FLAG_IRQ_CH_2)
regval |= ATIM_SR_CC2IF; mask |= ATIM_SR_CC2IF;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_3) if (flags & STM32_CAP_FLAG_IRQ_CH_3)
regval |= ATIM_SR_CC3IF; mask |= ATIM_SR_CC3IF;
if (src & STM32_TIM_FLAG_IRQ_CAPTURE_4) if (flags & STM32_CAP_FLAG_IRQ_CH_4)
regval |= ATIM_SR_CC4IF; mask |= ATIM_SR_CC4IF;
if (src & STM32_TIM_FLAG_OF_CAPTURE_1) if (flags & STM32_CAP_FLAG_OF_CH_1)
regval |= ATIM_SR_CC1OF; mask |= ATIM_SR_CC1OF;
if (src & STM32_TIM_FLAG_OF_CAPTURE_2) if (flags & STM32_CAP_FLAG_OF_CH_2)
regval |= ATIM_SR_CC2OF; mask |= ATIM_SR_CC2OF;
if (src & STM32_TIM_FLAG_OF_CAPTURE_3) if (flags & STM32_CAP_FLAG_OF_CH_3)
regval |= ATIM_SR_CC3OF; mask |= ATIM_SR_CC3OF;
if (src & STM32_TIM_FLAG_OF_CAPTURE_4) if (flags & STM32_CAP_FLAG_OF_CH_4)
regval |= ATIM_SR_CC4OF; mask |= ATIM_SR_CC4OF;
stm32_putreg16(priv, STM32_BTIM_SR_OFFSET, ~mask); stm32_putreg16(priv, STM32_BTIM_SR_OFFSET, ~mask);
} }
static stm32_cap_flags_t stm32_cap_getint(FAR struct stm32_cap_dev_s *dev) static stm32_cap_flags_t stm32_cap_getflags(FAR struct stm32_cap_dev_s *dev)
{ {
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
uint16_t regval = 0; uint16_t regval = 0;
stm32_cap_flags_t src = 0; stm32_cap_flags_t flags = 0;
regval = stm32_getreg16(priv, STM32_BTIM_SR_OFFSET); regval = stm32_getreg16(priv, STM32_BTIM_SR_OFFSET);
if (regval & ATIM_SR_UIF) if (regval & ATIM_SR_UIF)
src |= STM32_TIM_FLAG_IRQ_OVERFLOW; flags |= STM32_CAP_FLAG_IRG_COUNTER;
if (regval & ATIM_SR_CC1IF) if (regval & ATIM_SR_CC1IF)
src |= STM32_TIM_FLAG_IRQ_CAPTURE_1; flags |= STM32_CAP_FLAG_IRQ_CH_1;
if (regval & ATIM_SR_CC2IF) if (regval & ATIM_SR_CC2IF)
src |= STM32_TIM_FLAG_IRQ_CAPTURE_2; flags |= STM32_CAP_FLAG_IRQ_CH_2;
if (regval & ATIM_SR_CC3IF) if (regval & ATIM_SR_CC3IF)
src |= STM32_TIM_FLAG_IRQ_CAPTURE_3; flags |= STM32_CAP_FLAG_IRQ_CH_3;
if (regval & ATIM_SR_CC4IF) if (regval & ATIM_SR_CC4IF)
src |= STM32_TIM_FLAG_IRQ_CAPTURE_4; flags |= STM32_CAP_FLAG_IRQ_CH_4;
if (regval & ATIM_SR_CC1OF) if (regval & ATIM_SR_CC1OF)
src |= STM32_TIM_FLAG_OF_CAPTURE_1; flags |= STM32_CAP_FLAG_OF_CH_1;
if (regval & ATIM_SR_CC2OF) if (regval & ATIM_SR_CC2OF)
src |= STM32_TIM_FLAG_OF_CAPTURE_2; flags |= STM32_CAP_FLAG_OF_CH_2;
if (regval & ATIM_SR_CC3OF) if (regval & ATIM_SR_CC3OF)
src |= STM32_TIM_FLAG_OF_CAPTURE_3; flags |= STM32_CAP_FLAG_OF_CH_3;
if (regval & ATIM_SR_CC4OF) if (regval & ATIM_SR_CC4OF)
src |= STM32_TIM_FLAG_OF_CAPTURE_4; flags |= STM32_CAP_FLAG_OF_CH_4;
return src; return flags;
} }
@ -519,10 +641,9 @@ static stm32_cap_flags_t stm32_cap_getint(FAR struct stm32_cap_dev_s *dev)
************************************************************************************/ ************************************************************************************/
static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel, static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel,
stm32_cap_ch_cfg_t edge) stm32_cap_ch_cfg_t cfg)
{ {
int i; const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
uint32_t gpio = 0; uint32_t gpio = 0;
uint16_t mask; uint16_t mask;
uint16_t regval; uint16_t regval;
@ -556,36 +677,27 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel
return ERROR; return ERROR;
} }
mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP) mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP);
mask <<= (channel << 2); mask <<= (channel << 2);
regval <<= (channel << 2); regval <<= (channel << 2);
stm32_modifyreg16(priv,mask,regval); stm32_modifyreg16(priv,STM32_GTIM_CCER_OFFSET,mask,regval);
/* Set ccmr */ /* Set ccmr */
ccmr_val = cfg; regval = cfg;
mask = (GTIM_CCMR1_IC1F_MASK | GTIM_CCMR1_IC1PSC_MASK | GTIM_CCMR1_CC1S_MASK);
if ( (ccmr_val & GTIM_CCMR1_CC1S_MASK ) == 0 ) regval &= mask;
return ERROR; /* configured as output */
if ( (ccmr_val & GTIM_CCMR1_CC1S_MASK ) == 3 )
return ERROR; /* Not implemented */
/* Define its position (shift) and get register offset */
mask = (GTIM_CCMR1_IC1F_MASK | GTIM_CCMR1_IC1PSC_MASK | GTIM_CCMR1_CC1S_MASK)
ccmr_val &= mask
if (channel & 1) if (channel & 1)
{ {
ccmr_val <<= 8; regval <<= 8;
ccmr_mask <<= 8; mask <<= 8;
} }
if (channel < 2) if (channel < 2)
stm32_modifyreg16(priv,STM32_GTIM_CCMR1_OFFSET,ccmr_mask,ccmr_val); stm32_modifyreg16(priv,STM32_GTIM_CCMR1_OFFSET,mask,regval);
else else
stm32_modifyreg16(priv,STM32_GTIM_CCMR2_OFFSET,ccmr_mask,ccmr_val); stm32_modifyreg16(priv,STM32_GTIM_CCMR2_OFFSET,mask,regval);
/* set GPIO */ /* set GPIO */
@ -600,26 +712,26 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel
static int stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, uint8_t channel) static int stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, uint8_t channel)
{ {
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; const struct stm32_cap_priv_s *priv = (const struct stm32_cap_priv_s *)dev;
ASSERT(dev); ASSERT(dev);
switch (channel) switch (channel)
{ {
#ifdef HAVE_CH1IN #ifdef HAVE_CH1IN
case 1: case 1:
return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); return stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET);
#endif #endif
#ifdef HAVE_CH1IN #ifdef HAVE_CH1IN
case 2: case 2:
return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); return stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET);
#endif #endif
#ifdef HAVE_CH1IN #ifdef HAVE_CH1IN
case 3: case 3:
return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); return stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET);
#endif #endif
#ifdef HAVE_CH1IN #ifdef HAVE_CH1IN
case 4: case 4:
return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); return stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET);
#endif #endif
} }
@ -653,99 +765,80 @@ const struct stm32_cap_priv_s stm32_tim2_priv =
{ {
.ops = &stm32_cap_ops, .ops = &stm32_cap_ops,
.base = STM32_TIM2_BASE, .base = STM32_TIM2_BASE,
.irg = STM32_IRQ_TIM2, .irq = STM32_IRQ_TIM2,
#define HAVE_ADANCED_TIM 1 #ifdef USE_ADVENCED_TIM
.irg_of = -1, .irg_of = -1,
#endif #endif
.gpio_clk = GPIO_TIM2_CLKIN;
.channels = {
#if defined(GPIO_TIM2_CH1IN)
.gpio = GPIO_TIM2_CH1IN;
#endif
#if defined(GPIO_TIM2_CH2IN)
.gpio = GPIO_TIM2_CH2IN;
.ccmr = ( GPIO_TIM2_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT )|\
( GPIO_TIM2_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
#if defined(GPIO_TIM2_CH3IN)
.gpio = GPIO_TIM2_CH3IN;
.ccmr = ( GPIO_TIM2_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT )|\
( GPIO_TIM2_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
#if defined(GPIO_TIM2_CH4IN)
.gpio = GPIO_TIM2_CH4IN;
.ccmr = ( GPIO_TIM2_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT )|\
( GPIO_TIM2_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT );
#endif
}
}; };
#endif #endif
static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer)
{
switch (timer)
{
#ifdef CONFIG_STM32_TIM1_CAP
case 1: return &stm32_tim1_priv;
#endif
#ifdef CONFIG_STM32_TIM2_CAP
case 2: return &stm32_tim2_priv;
#endif
#ifdef CONFIG_STM32_TIM3_CAP
case 3: return &stm32_tim3_priv;
#endif
#ifdef CONFIG_STM32_TIM4_CAP
case 4: return &stm32_tim4_priv;
#endif
#ifdef CONFIG_STM32_TIM5_CAP
case 5: return &stm32_tim5_priv;
#endif
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32_TIM8_CAP
case 8: return &stm32_tim8_priv;
#endif
#ifdef CONFIG_STM32_TIM9_CAP
case 9: return &stm32_tim9_priv;
#endif
#ifdef CONFIG_STM32_TIM10_CAP
case 9: return &stm32_tim10_priv;
#endif
#ifdef CONFIG_STM32_TIM11_CAP
case 9: return &stm32_tim11_priv;
#endif
#ifdef CONFIG_STM32_TIM12_CAP
case 9: return &stm32_tim12_priv;
#endif
#ifdef CONFIG_STM32_TIM13_CAP
case 9: return &stm32_tim13_priv;
#endif
#ifdef CONFIG_STM32_TIM14_CAP
case 9: return &stm32_tim14_priv;
#endif
}
return NULL;
}
/************************************************************************************ /************************************************************************************
* Public Function - Initialization * Public Function - Initialization
************************************************************************************/ ************************************************************************************/
FAR struct stm32_cap_dev_s *stm32_cap_init(int timer) FAR struct stm32_cap_dev_s *stm32_cap_init(int timer)
{ {
struct stm32_cap_priv_s *priv = NULL; const struct stm32_cap_priv_s *priv = stm32_cap_get_priv(timer);
uint32_t gpio;
/* Get structure and enable power */ if ( priv )
switch (timer)
{ {
#ifdef CONFIG_STM32_TIM1_CAP
case 1:
priv = &stm32_tim1_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
break;
#endif
#ifdef CONFIG_STM32_TIM2_CAP
case 2:
priv = &stm32_tim2_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN);
break;
#endif
#ifdef CONFIG_STM32_TIM3_CAP
case 3:
priv = &stm32_tim3_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
break;
#endif
#ifdef CONFIG_STM32_TIM4_CAP
case 4:
priv = &stm32_tim4_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN);
break;
#endif
#ifdef CONFIG_STM32_TIM5_CAP
case 5:
priv = &stm32_tim5_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
break;
#endif
/* TIM6 and TIM7 cannot be used in capture */
#ifdef CONFIG_STM32_TIM8_CAP
case 8:
priv = &stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
#ifdef CONFIG_STM32_TIM9_CAP
case 9:
priv = &stm32_tim9_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
break;
#endif
default:
return NULL;
}
if (priv->gpio_clk) stm32_cap_set_rcc(priv,true);
stm32_configgpio(priv->gpio_clk)
gpio = stm32_cap_gpio(priv,GPIO_CLK);
if (gpio)
stm32_configgpio(gpio);
// disable timer while is not configured // disable timer while is not configured
stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0);
}
return (struct stm32_cap_dev_s *)priv; return (struct stm32_cap_dev_s *)priv;
} }
@ -753,50 +846,18 @@ FAR struct stm32_cap_dev_s *stm32_cap_init(int timer)
int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev) int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev)
{ {
struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; const struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev;
uint32_t gpio;
ASSERT(dev); ASSERT(dev);
// disable timer while is not configured // disable timer while is not configured
stm32_modifyreg16(dev, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0);
if (priv->gpio_clk) gpio = stm32_cap_gpio(priv,GPIO_CLK);
stm32_unconfiggpio(priv->gpio_clk) if (gpio)
stm32_unconfiggpio(gpio);
switch (priv->base) stm32_cap_set_rcc(priv,false);
{
#ifdef CONFIG_STM32_TIM2_CAP
case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM3_CAP
case STM32_TIM3_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM4_CAP
case STM32_TIM4_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM5_CAP
case STM32_TIM5_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM1_CAP
case STM32_TIM1_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
break;
#endif
#ifdef CONFIG_STM32_TIM8_CAP
case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
#endif
default:
return ERROR;
}
return OK; return OK;
} }

38
arch/arm/src/stm32/stm32_capture.h
View File

@ -53,13 +53,13 @@
************************************************************************************/ ************************************************************************************/
/* Helpers **************************************************************************/ /* Helpers **************************************************************************/
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) #define STM32_CAP_SETCLOCK(d,clk_src,psc,max) ((d)->ops->setclock(d,clk_src,psc,max))
#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) #define STM32_CAP_SETCHANNEL(d,ch,cfg) ((d)->ops->setchannel(d,ch,cfg))
#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) #define STM32_CAP_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
#define STM32_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s)) #define STM32_CAP_SETISR(d,hnd) ((d)->ops->setisr(d,hnd))
#define STM32_TIM_ENABLEINT(d,s,on) ((d)->ops->enableint(d,s,on)) #define STM32_CAP_ENABLEINT(d,s,on) ((d)->ops->enableint(d,s,on))
#define STM32_TIM_ACKFLAGS(d,s) ((d)->ops->ackflags(d,s)) #define STM32_CAP_ACKFLAGS(d,f) ((d)->ops->ackflags(d,f))
#define STM32_TIM_GETFLAGS(d) ((d)->ops->getflags(d)) #define STM32_CAP_GETFLAGS(d) ((d)->ops->getflags(d))
/************************************************************************************ /************************************************************************************
* Public Types * Public Types
@ -131,7 +131,7 @@ typedef enum
} stm32_cap_ch_cfg_t; } stm32_cap_ch_cfg_t;
/* TIM clock sources */ /* Capture clock sources */
typedef enum typedef enum
{ {
@ -143,13 +143,13 @@ typedef enum
} stm32_cap_clk_t; } stm32_cap_clk_t;
/* TIM Sources */ /* Capture flags */
typedef enum typedef enum
{ {
/* One of the following */ /* One of the following */
STM32_CAP_FLAG_IRQ_TIMER = (GTIM_SR_UIF), STM32_CAP_FLAG_IRG_COUNTER = (GTIM_SR_UIF),
STM32_CAP_FLAG_IRQ_CH_1 = (GTIM_SR_CC1IF), STM32_CAP_FLAG_IRQ_CH_1 = (GTIM_SR_CC1IF),
STM32_CAP_FLAG_IRQ_CH_2 = (GTIM_SR_CC2IF), STM32_CAP_FLAG_IRQ_CH_2 = (GTIM_SR_CC2IF),
@ -163,16 +163,20 @@ typedef enum
} stm32_cap_flags_t; } stm32_cap_flags_t;
#define STM32_CAP_FLAG_IRQ_CH(ch) (GTIM_SR_CC1IF<<((ch)-1))
#define STM32_CAP_FLAG_OF_CH(ch) (GTIM_SR_CC1OF<<((ch)-1))
/* TIM Operations */ /* Capture Operations */
struct stm32_cap_ops_s struct stm32_cap_ops_s
{ {
int (*setclock)(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src_t clk_src, int (*setclock)( FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_t clk, uint32_t prescaler, uint32_t max);
uint32_t prescaler); int (*setchannel)(FAR struct stm32_cap_dev_s *dev, uint8_t channel, stm32_cap_ch_cfg_t cfg);
int (*setchannel)(FAR struct stm32_cap_dev_s *dev, uint8_t channel); int (*getcapture)(FAR struct stm32_cap_dev_s *dev, uint8_t channel);
int (*setisr)(FAR struct stm32_tim_dev_s *dev,xcpt_t handler); int (*setisr)( FAR struct stm32_cap_dev_s *dev, xcpt_t handler);
void (*enableint)(FAR struct stm32_tim_dev_s *dev, stm32_cap_flags_t src, bool on ); void (*enableint)( FAR struct stm32_cap_dev_s *dev, stm32_cap_flags_t src, bool on );
void (*ackflags)( FAR struct stm32_cap_dev_s *dev, int flags);
stm32_cap_flags_t (*getflags)(FAR struct stm32_cap_dev_s *dev);
}; };
/************************************************************************************ /************************************************************************************
@ -194,4 +198,4 @@ int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev);
#endif #endif
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */ #endif /* __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H */