efm32 addons missing file
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pnb
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@ -76,7 +76,44 @@
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* Pre-processor Definitions
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*******************************************************************************************************************************/
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#define DEVINFO ((const struct efm32_devinfo_s *)EFM32_DEVINFO_BASE)
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/* MSC Register Offsets ********************************************************************************************************/
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#define EFM32_DEVINFO_CAL_OFFSET 0x0000
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#define EFM32_DEVINFO_ADC0CALn_OFFSET(n) (0x0004+(n)*4)
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#define EFM32_DEVINFO_DAC0CALn_OFFSET(n) (0x0018+(n)*4)
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#define EFM32_DEVINFO_AUXHFRCOCALn_OFFSET(n) (0x0024+(n)*4)
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#define EFM32_DEVINFO_HFRCOCALn_OFFSET(n) (0x002c+(n)*4)
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#define EFM32_DEVINFO_MEMINFO_PAGE_SIZE_OFFSET 0x0034
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#define EFM32_DEVINFO_UNIQUEL_OFFSET 0x0040
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#define EFM32_DEVINFO_UNIQUEH_OFFSET 0x0044
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#define EFM32_DEVINFO_MEMINFO_SIZE_OFFSET 0x0048
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#define EFM32_DEVINFO_PART_OFFSET 0x004c
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/* MSC Register Addresses ******************************************************************************************************/
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#define EFM32_DEVINFO_CAL (EFM32_DEVINFO_BASE+EFM32_DEVINFO_CAL_OFFSET)
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#define EFM32_DEVINFO_ADC0CALn(n) (EFM32_DEVINFO_BASE+EFM32_DEVINFO_ADC0CALn_OFFSET(n))
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#define EFM32_DEVINFO_ADC0CAL0 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_ADC0CALn_OFFSET(0))
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#define EFM32_DEVINFO_ADC0CAL1 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_ADC0CALn_OFFSET(1))
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#define EFM32_DEVINFO_ADC0CAL2 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_ADC0CALn_OFFSET(2))
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#define EFM32_DEVINFO_DAC0CALn(n) (EFM32_DEVINFO_BASE+EFM32_DEVINFO_DAC0CALn_OFFSET(n))
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#define EFM32_DEVINFO_DAC0CAL0 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_DAC0CALn_OFFSET(0))
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#define EFM32_DEVINFO_DAC0CAL1 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_DAC0CALn_OFFSET(1))
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#define EFM32_DEVINFO_DAC0CAL2 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_DAC0CALn_OFFSET(2))
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#define EFM32_DEVINFO_AUXHFRCOCALn(n) (EFM32_DEVINFO_BASE+EFM32_DEVINFO_AUXHFRCOCALn_OFFSET(n))
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#define EFM32_DEVINFO_AUXHFRCOCAL0 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_AUXHFRCOCALn_OFFSET(0))
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#define EFM32_DEVINFO_AUXHFRCOCAL1 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_AUXHFRCOCALn_OFFSET(1))
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#define EFM32_DEVINFO_HFRCOCALn(n) (EFM32_DEVINFO_BASE+EFM32_DEVINFO_HFRCOCALn_OFFSET(n))
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#define EFM32_DEVINFO_HFRCOCAL0 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_HFRCOCALn_OFFSET(0))
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#define EFM32_DEVINFO_HFRCOCAL1 (EFM32_DEVINFO_BASE+EFM32_DEVINFO_HFRCOCALn_OFFSET(1))
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#define EFM32_DEVINFO_MEMINFO_PAGE_SIZE (EFM32_DEVINFO_BASE+EFM32_DEVINFO_MEMINFO_PAGE_SIZE_OFFSET)
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#define EFM32_DEVINFO_UNIQUEL (EFM32_DEVINFO_BASE+EFM32_DEVINFO_UNIQUEL_OFFSET)
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#define EFM32_DEVINFO_UNIQUEH (EFM32_DEVINFO_BASE+EFM32_DEVINFO_UNIQUEH_OFFSET)
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#define EFM32_DEVINFO_MEMINFO_SIZE (EFM32_DEVINFO_BASE+EFM32_DEVINFO_MEMINFO_SIZE_OFFSET)
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#define EFM32_DEVINFO_PART (EFM32_DEVINFO_BASE+EFM32_DEVINFO_PART_OFFSET)
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/* Bit fields for struct efm32_devinfo_s */
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@ -166,10 +203,10 @@
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#define _DEVINFO_UNIQUEH_MASK 0xFFFFFFFFUL /* High part of 64-bit device unique number */
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#define _DEVINFO_UNIQUEH_SHIFT 0 /* Unique High 32-bit shift */
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#define _DEVINFO_MSIZE_SRAM_MASK 0xFFFF0000UL /* Flash size in kilobytes */
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#define _DEVINFO_MSIZE_SRAM_SHIFT 16 /* Bit position for flash size */
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#define _DEVINFO_MSIZE_FLASH_MASK 0x0000FFFFUL /* SRAM size in kilobytes */
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#define _DEVINFO_MSIZE_FLASH_SHIFT 0 /* Bit position for SRAM size */
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#define _DEVINFO_MEMINFO_SIZE_SRAM_MASK 0xFFFF0000UL /* Flash size in kilobytes */
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#define _DEVINFO_MEMINFO_SIZE_SRAM_SHIFT 16 /* Bit position for flash size */
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#define _DEVINFO_MEMINFO_SIZE_FLASH_MASK 0x0000FFFFUL /* SRAM size in kilobytes */
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#define _DEVINFO_MEMINFO_SIZE_FLASH_SHIFT 0 /* Bit position for SRAM size */
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#define _DEVINFO_PART_PROD_REV_MASK 0xFF000000UL /* Production revision */
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#define _DEVINFO_PART_PROD_REV_SHIFT 24 /* Bit position for production revision */
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@ -188,26 +225,5 @@
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* Public Type Definitions
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*******************************************************************************************************************************/
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struct efm32_devinfo_s
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{
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const uint32_t cal; /* Calibration temperature and checksum */
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const uint32_t adc0cal0; /* ADC0 Calibration register 0 */
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const uint32_t adc0cal1; /* ADC0 Calibration register 1 */
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const uint32_t adc0cal2; /* ADC0 Calibration register 2 */
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uint32_t reserved0[2]; /* Reserved */
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const uint32_t dac0cal0; /* DAC calibration register 0 */
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const uint32_t dac0cal1; /* DAC calibration register 1 */
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const uint32_t dac0cal2; /* DAC calibration register 2 */
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const uint32_t auxhfrcocal0; /* AUXHFRCO calibration register 0 */
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const uint32_t auxhfrcocal1; /* AUXHFRCO calibration register 1 */
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const uint32_t hfrcocal0; /* HFRCO calibration register 0 */
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const uint32_t hfrcocal1; /* HFRCO calibration register 1 */
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const uint32_t meminfo; /* Memory information */
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uint32_t reserved2[2]; /* Reserved */
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const uint32_t uniquel; /* Low 32 bits of device unique number */
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const uint32_t uniqueh; /* High 32 bits of device unique number */
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const uint32_t msize; /* Flash and SRAM Memory size in KiloBytes */
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const uint32_t part; /* Part description */
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};
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#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32_DEVINFO_H */
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56
arch/arm/src/efm32/chip/efm32_flash.h
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56
arch/arm/src/efm32/chip/efm32_flash.h
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@ -0,0 +1,56 @@
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/************************************************************************************
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* arch/arm/src/efm32/chip/efm32_flash.h
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*
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* Copyright (C) 2014 Bouteville Pierre-Noel. All rights reserved.
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* Author: Bouteville Pierre-Noel <pnb990@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_EFM32_CHIP_EFM32_FLASH_H
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#define __ARCH_ARM_SRC_EFM32_CHIP_EFM32_FLASH_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#if defined(CONFIG_EFM32_EFM32GG)
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# define EFM32_FLASH_PAGESIZE 4096
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#elif defined(CONFIG_EFM32_EFM32LG)
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# define EFM32_FLASH_PAGESIZE 2048
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#elif defined(CONFIG_EFM32_EFM32WG)
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# define EFM32_FLASH_PAGESIZE 2048
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#elif defined(CONFIG_EFM32_EFM32ZG)
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# define EFM32_FLASH_PAGESIZE 1024
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#elif defined(CONFIG_EFM32_EFM32G)
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# define EFM32_FLASH_PAGESIZE 512
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#elif defined(CONFIG_EFM32_EFM32TG)
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# define EFM32_FLASH_PAGESIZE 512
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#endif
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@ -544,6 +544,8 @@
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#define MSC_LOCK_LOCKKEY_LOCKED (_MSC_LOCK_LOCKKEY_LOCKED << 0) /* Shifted mode LOCKED for MSC_LOCK */
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#define MSC_LOCK_LOCKKEY_UNLOCK (_MSC_LOCK_LOCKKEY_UNLOCK << 0) /* Shifted mode UNLOCK for MSC_LOCK */
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#define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
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/* Bit fields for MSC CMD */
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#if defined(CONFIG_EFM32_EFM32GG)
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@ -137,4 +137,7 @@
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#define EFM32_CALIBRATE_BASE 0x0fe08000 /* CALIBRATE base address */
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#define EFM32_DEVINFO_BASE 0x0fe081b0 /* DEVINFO base address */
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#define EFM32_USERDATA_SIZE 0x00000800 /* User data page size */
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#define EFM32_USERDATA_NPAGES 1 /* User data page number */
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#endif /* __ARCH_ARM_SRC_EFM32_CHIP_EFM32GG_MEMORYMAP_H */
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