Add Kinetis CMP, ADC, PDB, and DAC header files
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3865 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -239,10 +239,10 @@
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#define ADC_SC3_AVGS_SHIFT (0) /* Bits 0-1: Hardware average select */
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#define ADC_SC3_AVGS_MASK (3 << ADC_SC3_AVGS_SHIFT)
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# define ADC_SC3_AVGS_4SAMPLS (0 << ADC_SC3_AVGS_SHIFT) /* 4 samples averaged */
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# define ADC_SC3_AVGS_8SAMPLS (1 << ADC_SC3_AVGS_SHIFT) /* 8 samples averaged */
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# define ADC_SC3_AVGS_16SAMPLS (2 << ADC_SC3_AVGS_SHIFT) /* 18 samples averaged */
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# define ADC_SC3_AVGS_32SAMPLS (3 << ADC_SC3_AVGS_SHIFT) /* 32 samples averaged */
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# define ADC_SC3_AVGS_4SMPLS (0 << ADC_SC3_AVGS_SHIFT) /* 4 samples averaged */
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# define ADC_SC3_AVGS_8SMPLS (1 << ADC_SC3_AVGS_SHIFT) /* 8 samples averaged */
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# define ADC_SC3_AVGS_16SMPLS (2 << ADC_SC3_AVGS_SHIFT) /* 18 samples averaged */
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# define ADC_SC3_AVGS_32SMPLS (3 << ADC_SC3_AVGS_SHIFT) /* 32 samples averaged */
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#define ADC_SC3_AVGE (1 << 2) /* Bit 2: Hardware average enable */
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#define ADC_SC3_ADCO (1 << 3) /* Bit 3: Continuous conversion enable */
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/* Bits 4-5: Reserved */
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@ -282,7 +282,9 @@
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# define ADC_PGA_PGAG_16 (4 << ADC_PGA_PGAG_SHIFT)
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# define ADC_PGA_PGAG_32 (5 << ADC_PGA_PGAG_SHIFT)
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# define ADC_PGA_PGAG_64 (6 << ADC_PGA_PGAG_SHIFT)
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#define ADC_PGA_PGALP (1 << 20) /* Bit 20: PGA low-power mode control*/
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#ifdef KINETIS_K40
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# define ADC_PGA_PGALP (1 << 20) /* Bit 20: PGA low-power mode control */
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#endif
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/* Bits 21-22: Reserved */
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#define ADC_PGA_PGAEN (1 << 23) /* Bit 23: PGA enable*/
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/* Bits 24-31: Reserved */
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190
arch/arm/src/kinetis/kinetis_cmp.h
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190
arch/arm/src/kinetis/kinetis_cmp.h
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/********************************************************************************************
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* arch/arm/src/kinetis/kinetis_cmp.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CMP_H
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#define __ARCH_ARM_SRC_KINETIS_KINETIS_CMP_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* Register Offsets *************************************************************************/
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#define KINESIS_CMP_OFFSET(n) ((n) << 3)
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#define KINESIS_CMP0_OFFSET 0x0000
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#define KINESIS_CMP1_OFFSET 0x0008
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#define KINESIS_CMP2_OFFSET 0x0010
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#define KINETIS_CMP_CR0_OFFSET 0x0000 /* CMP Control Register 0 */
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#define KINETIS_CMP_CR1_OFFSET 0x0001 /* CMP Control Register 1 */
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#define KINETIS_CMP_FPR_OFFSET 0x0002 /* CMP Filter Period Register */
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#define KINETIS_CMP_SCR_OFFSET 0x0003 /* CMP Status and Control Register */
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#define KINETIS_CMP_DACCR_OFFSET 0x0004 /* DAC Control Register */
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#define KINETIS_CMP_MUXCR_OFFSET 0x0005 /* MUX Control Register */
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/* Register Addresses ***********************************************************************/
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#define KINESIS_CMP_BASE(n) (KINETIS_CMP_BASE+KINESIS_CMP_OFFSET(n))
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#define KINESIS_CMP0_BASE (KINETIS_CMP_BASE+KINESIS_CMP0_OFFSET)
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#define KINESIS_CMP1_BASE (KINETIS_CMP_BASE+KINESIS_CMP1_OFFSET)
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#define KINESIS_CMP2_BASE (KINETIS_CMP_BASE+KINESIS_CMP2_OFFSET)
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#define KINETIS_CMP_CR0(n) (KINESIS_CMP_BASE(n)+KINETIS_CMP_CR0_OFFSET)
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#define KINETIS_CMP_CR1(n) (KINESIS_CMP_BASE(n)+KINETIS_CMP_CR1_OFFSET)
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#define KINETIS_CMP_FPR(n) (KINESIS_CMP_BASE(n)+KINETIS_CMP_FPR_OFFSET)
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#define KINETIS_CMP_SCR(n) (KINESIS_CMP_BASE(n)+KINETIS_CMP_SCR_OFFSET)
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#define KINETIS_CMP_DACCR(n) (KINESIS_CMP_BASE(n)+KINETIS_CMP_DACCR_OFFSET)
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#define KINETIS_CMP_MUXCR(n) (KINESIS_CMP_BASE(n)+KINETIS_CMP_MUXCR_OFFSET)
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#define KINETIS_CMP0_CR0 (KINETIS_CMP0_BASE+KINETIS_CMP_CR0_OFFSET)
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#define KINETIS_CMP0_CR1 (KINETIS_CMP0_BASE+KINETIS_CMP_CR1_OFFSET)
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#define KINETIS_CMP0_FPR (KINETIS_CMP0_BASE+KINETIS_CMP_FPR_OFFSET)
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#define KINETIS_CMP0_SCR (KINETIS_CMP0_BASE+KINETIS_CMP_SCR_OFFSET)
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#define KINETIS_CMP0_DACCR (KINETIS_CMP0_BASE+KINETIS_CMP_DACCR_OFFSET)
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#define KINETIS_CMP0_MUXCR (KINETIS_CMP0_BASE+KINETIS_CMP_MUXCR_OFFSET)
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#define KINETIS_CMP1_CR0 (KINETIS_CMP1_BASE+KINETIS_CMP_CR0_OFFSET)
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#define KINETIS_CMP1_CR1 (KINETIS_CMP1_BASE+KINETIS_CMP_CR1_OFFSET)
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#define KINETIS_CMP1_FPR (KINETIS_CMP1_BASE+KINETIS_CMP_FPR_OFFSET)
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#define KINETIS_CMP1_SCR (KINETIS_CMP1_BASE+KINETIS_CMP_SCR_OFFSET)
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#define KINETIS_CMP1_DACCR (KINETIS_CMP1_BASE+KINETIS_CMP_DACCR_OFFSET)
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#define KINETIS_CMP1_MUXCR (KINETIS_CMP1_BASE+KINETIS_CMP_MUXCR_OFFSET)
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#define KINETIS_CMP2_CR0 (KINETIS_CMP2_BASE+KINETIS_CMP_CR0_OFFSET)
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#define KINETIS_CMP2_CR1 (KINETIS_CMP2_BASE+KINETIS_CMP_CR1_OFFSET)
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#define KINETIS_CMP2_FPR (KINETIS_CMP2_BASE+KINETIS_CMP_FPR_OFFSET)
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#define KINETIS_CMP2_SCR (KINETIS_CMP2_BASE+KINETIS_CMP_SCR_OFFSET)
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#define KINETIS_CMP2_DACCR (KINETIS_CMP2_BASE+KINETIS_CMP_DACCR_OFFSET)
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#define KINETIS_CMP2_MUXCR (KINETIS_CMP2_BASE+KINETIS_CMP_MUXCR_OFFSET)
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/* Register Bit Definitions *****************************************************************/
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/* CMP Control Register 0 (8-bit) */
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#define CMP_CR0_HYSTCTR_SHIFT (0) /* Bits 0-1: Comparator hard block hysteresis control */
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#define CMP_CR0_HYSTCTR_MASK (3 << CMP_CR0_HYSTCTR_SHIFT)
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# define CMP_CR0_HYSTCTR_LVL0 (0 << CMP_CR0_HYSTCTR_SHIFT)
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# define CMP_CR0_HYSTCTR_LVL1 (1 << CMP_CR0_HYSTCTR_SHIFT)
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# define CMP_CR0_HYSTCTR_LVL2 (2 << CMP_CR0_HYSTCTR_SHIFT)
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# define CMP_CR0_HYSTCTR_LVL3 (3 << CMP_CR0_HYSTCTR_SHIFT)
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/* Bits 2-3: Reserved */
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#define CMP_CR0_FILTER_CNT_SHIFT (4) /* Bits 4-6: Filter Sample Count */
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#define CMP_CR0_FILTER_CNT_MASK (7 << CMP_CR0_FILTER_CNT_SHIFT)
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# define CMP_CR0_FILTER_DISABLED (0 << CMP_CR0_FILTER_CNT_SHIFT) /* Filter is disabled */
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# define CMP_CR0_FILTER_CNT1 (1 << CMP_CR0_FILTER_CNT_SHIFT) /* 1 consecutive sample must agree */
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# define CMP_CR0_FILTER_CNT2 (2 << CMP_CR0_FILTER_CNT_SHIFT) /* 2 consecutive samples must agree */
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# define CMP_CR0_FILTER_CNT3 (3 << CMP_CR0_FILTER_CNT_SHIFT) /* 3 consecutive samples must agree */
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# define CMP_CR0_FILTER_CNT4 (4 << CMP_CR0_FILTER_CNT_SHIFT) /* 4 consecutive samples must agree */
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# define CMP_CR0_FILTER_CNT5 (5 << CMP_CR0_FILTER_CNT_SHIFT) /* 5 consecutive samples must agree */
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# define CMP_CR0_FILTER_CNT6 (6 << CMP_CR0_FILTER_CNT_SHIFT) /* 6 consecutive samples must agree */
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# define CMP_CR0_FILTER_CNT7 (7 << CMP_CR0_FILTER_CNT_SHIFT) /* 7 consecutive samples must agree */
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/* Bit 7: Reserved */
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/* CMP Control Register 1 (8-bit) */
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#define CMP_CR1_EN (1 << 0) /* Bit 0: Comparator Module Enable */
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#define CMP_CR1_OPE (1 << 1) /* Bit 1: Comparator Output Pin Enable */
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#define CMP_CR1_COS (1 << 2) /* Bit 2: Comparator Output Select */
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#define CMP_CR1_INV (1 << 3) /* Bit 3: Comparator INVERT */
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#define CMP_CR1_PMODE (1 << 4) /* Bit 4: Power Mode Select */
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/* Bit 5: Reserved */
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#define CMP_CR1_WE (1 << 6) /* Bit 6: Windowing Enable */
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#define CMP_CR1_SE (1 << 7) /* Bit 7: Sample Enable */
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/* CMP Filter Period Register (8-bit Filter Sample Period) */
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/* CMP Status and Control Register (8-bit) */
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#define CMP_SCR_COUT (1 << 0) /* Bit 0: Analog Comparator Output */
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#define CMP_SCR_CFF (1 << 1) /* Bit 1: Analog Comparator Flag Falling */
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#define CMP_SCR_CFR (1 << 2) /* Bit 2: Analog Comparator Flag Rising */
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#define CMP_SCR_IEF (1 << 3) /* Bit 3: Comparator Interrupt Enable Falling */
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#define CMP_SCR_IER (1 << 4) /* Bit 4: Comparator Interrupt Enable Rising */
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#define CMP_SCR_SMELB (1 << 5) /* Bit 5: Stop Mode Edge/Level Interrupt Control */
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#define CMP_SCR_DMAEN (1 << 6) /* Bit 6: DMA Enable Control */
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/* Bit 7: Reserved */
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/* DAC Control Register (8-bit) */
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#define CMP_DACCR_VOSEL_SHIFT (0) /* Bits 0-5: DAC Output Voltage Select */
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#define CMP_DACCR_VOSEL_MASK (0x3f << CMP_DACCR_VOSEL_SHIFT)
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#define CMP_DACCR_VRSEL (1 << 6) /* Bit 6: Supply Voltage Reference Source Select */
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#define CMP_DACCR_DACEN (1 << 7) /* Bit 7: DAC Enable */
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/* MUX Control Register (8-bit) */
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#define CMP_MUXCR_MSEL_SHIFT (0) /* Bits 0-2: Minus Input MUX Control */
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#define CMP_MUXCR_MSEL_MASK (7 << CMP_MUXCR_MSEL_SHIFT)
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# define CMP_MUXCR_MSEL_IN0 (0 << CMP_MUXCR_MSEL_SHIFT)
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# define CMP_MUXCR_MSEL_IN1 (1 << CMP_MUXCR_MSEL_SHIFT)
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# define CMP_MUXCR_MSEL_IN2 (2 << CMP_MUXCR_MSEL_SHIFT)
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# define CMP_MUXCR_MSEL_IN3 (3 << CMP_MUXCR_MSEL_SHIFT)
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# define CMP_MUXCR_MSEL_IN4 (4 << CMP_MUXCR_MSEL_SHIFT)
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# define CMP_MUXCR_MSEL_IN5 (5 << CMP_MUXCR_MSEL_SHIFT)
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# define CMP_MUXCR_MSEL_IN6 (6 << CMP_MUXCR_MSEL_SHIFT)
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# define CMP_MUXCR_MSEL_IN7 (7 << CMP_MUXCR_MSEL_SHIFT)
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#define CMP_MUXCR_PSEL_SHIFT (3) /* Bits 3-5: Plus Input MUX Control */
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#define CMP_MUXCR_PSEL_MASK (7 << CMP_MUXCR_PSEL_SHIFT)
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# define CMP_MUXCR_PSEL_IN0 (0 << CMP_MUXCR_PSEL_SHIFT)
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# define CMP_MUXCR_PSEL_IN1 (1 << CMP_MUXCR_PSEL_SHIFT)
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# define CMP_MUXCR_PSEL_IN2 (2 << CMP_MUXCR_PSEL_SHIFT)
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# define CMP_MUXCR_PSEL_IN3 (3 << CMP_MUXCR_PSEL_SHIFT)
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# define CMP_MUXCR_PSEL_IN4 (4 << CMP_MUXCR_PSEL_SHIFT)
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# define CMP_MUXCR_PSEL_IN5 (5 << CMP_MUXCR_PSEL_SHIFT)
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# define CMP_MUXCR_PSEL_IN6 (6 << CMP_MUXCR_PSEL_SHIFT)
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# define CMP_MUXCR_PSEL_IN7 (7 << CMP_MUXCR_PSEL_SHIFT)
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#define CMP_MUXCR_MEN (1 << 6) /* Bit 6: MMUX Enable */
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#define CMP_MUXCR_PEN (1 << 7) /* Bit 7: PMUX Enable */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CMP_H */
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235
arch/arm/src/kinetis/kinetis_dac.h
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235
arch/arm/src/kinetis/kinetis_dac.h
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@ -0,0 +1,235 @@
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/********************************************************************************************
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* arch/arm/src/kinetis/kinetis_dac.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_DACE_H
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#define __ARCH_ARM_SRC_KINETIS_KINETIS_DACE_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* Register Offsets *************************************************************************/
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#define KINETIS_DAC_DATL_OFFSET(n) (0x0000+((n)<<1))
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#define KINETIS_DAC_DATH_OFFSET(n) (0x0001+((n)<<1))
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#define KINETIS_DAC_DAT0L_OFFSET 0x0000 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT0H_OFFSET 0x0001 /* DAC Data High Register */
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#define KINETIS_DAC_DAT1L_OFFSET 0x0002 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT1H_OFFSET 0x0003 /* DAC Data High Register */
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#define KINETIS_DAC_DAT2L_OFFSET 0x0004 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT2H_OFFSET 0x0005 /* DAC Data High Register */
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#define KINETIS_DAC_DAT3L_OFFSET 0x0006 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT3H_OFFSET 0x0007 /* DAC Data High Register */
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#define KINETIS_DAC_DAT4L_OFFSET 0x0008 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT4H_OFFSET 0x0009 /* DAC Data High Register */
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#define KINETIS_DAC_DAT5L_OFFSET 0x000a /* DAC Data Low Register */
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#define KINETIS_DAC_DAT5H_OFFSET 0x000b /* DAC Data High Register */
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#define KINETIS_DAC_DAT6L_OFFSET 0x000c /* DAC Data Low Register */
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#define KINETIS_DAC_DAT6H_OFFSET 0x000d /* DAC Data High Register */
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#define KINETIS_DAC_DAT7L_OFFSET 0x000e /* DAC Data Low Register */
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#define KINETIS_DAC_DAT7H_OFFSET 0x000f /* DAC Data High Register */
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#define KINETIS_DAC_DAT8L_OFFSET 0x0010 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT8H_OFFSET 0x0011 /* DAC Data High Register */
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#define KINETIS_DAC_DAT9L_OFFSET 0x0012 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT9H_OFFSET 0x0013 /* DAC Data High Register */
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#define KINETIS_DAC_DAT10L_OFFSET 0x0014 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT10H_OFFSET 0x0015 /* DAC Data High Register */
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#define KINETIS_DAC_DAT11L_OFFSET 0x0016 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT11H_OFFSET 0x0017 /* DAC Data High Register */
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#define KINETIS_DAC_DAT12L_OFFSET 0x0018 /* DAC Data Low Register */
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#define KINETIS_DAC_DAT12H_OFFSET 0x0019 /* DAC Data High Register */
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#define KINETIS_DAC_DAT13L_OFFSET 0x001a /* DAC Data Low Register */
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#define KINETIS_DAC_DAT13H_OFFSET 0x001b /* DAC Data High Register */
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#define KINETIS_DAC_DAT14L_OFFSET 0x001c /* DAC Data Low Register */
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#define KINETIS_DAC_DAT14H_OFFSET 0x001d /* DAC Data High Register */
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#define KINETIS_DAC_DAT15L_OFFSET 0x001e /* DAC Data Low Register */
|
||||
#define KINETIS_DAC_DAT15H_OFFSET 0x001f /* DAC Data High Register */
|
||||
#define KINETIS_DAC_SR_OFFSET 0x0020 /* DAC Status Register */
|
||||
#define KINETIS_DAC_C0_OFFSET 0x0021 /* DAC Control Register */
|
||||
#define KINETIS_DAC_C1_OFFSET 0x0022 /* DAC Control Register 1 */
|
||||
#define KINETIS_DAC_C2_OFFSET 0x0023 /* DAC Control Register 2 */
|
||||
|
||||
/* Register Addresses ***********************************************************************/
|
||||
|
||||
#define KINETIS_DAC0_DATL(n) (KINETIS_DAC0_BASE+KINETIS_DAC_DATL_OFFSET(n))
|
||||
#define KINETIS_DAC0_DATH(n) (KINETIS_DAC0_BASE+KINETIS_DAC_DATH_OFFSET(n))
|
||||
|
||||
#define KINETIS_DAC0_DAT0L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT0L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT0H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT0H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT1L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT1L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT1H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT1H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT2L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT2L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT2H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT2H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT3L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT3L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT3H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT3H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT4L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT4L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT4H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT4H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT5L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT5L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT5H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT5H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT6L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT6L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT6H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT6H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT7L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT7L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT7H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT7H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT8L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT8L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT8H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT8H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT9L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT9L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT9H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT9H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT10L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT10L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT10H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT10H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT11L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT11L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT11H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT11H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT12L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT12L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT12H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT12H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT13L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT13L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT13H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT13H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT14L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT14L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT14H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT14H_OFFSET)
|
||||
#define KINETIS_DAC0_DAT15L (KINETIS_DAC0_BASE+KINETIS_DAC_DAT15L_OFFSET)
|
||||
#define KINETIS_DAC0_DAT15H (KINETIS_DAC0_BASE+KINETIS_DAC_DAT15H_OFFSET)
|
||||
#define KINETIS_DAC0_SR (KINETIS_DAC0_BASE+KINETIS_DAC_SR_OFFSET)
|
||||
#define KINETIS_DAC0_C0 (KINETIS_DAC0_BASE+KINETIS_DAC_C0_OFFSET)
|
||||
#define KINETIS_DAC0_C1 (KINETIS_DAC0_BASE+KINETIS_DAC_C1_OFFSET)
|
||||
#define KINETIS_DAC0_C2 (KINETIS_DAC0_BASE+KINETIS_DAC_C2_OFFSET)
|
||||
|
||||
#define KINETIS_DAC1_DATL(n) (KINETIS_DAC1_BASE+KINETIS_DAC_DATL_OFFSET(n))
|
||||
#define KINETIS_DAC1_DATH(n) (KINETIS_DAC1_BASE+KINETIS_DAC_DATH_OFFSET(n))
|
||||
|
||||
#define KINETIS_DAC1_DAT0L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT0L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT0H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT0H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT1L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT1L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT1H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT1H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT2L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT2L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT2H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT2H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT3L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT3L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT3H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT3H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT4L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT4L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT4H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT4H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT5L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT5L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT5H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT5H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT6L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT6L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT6H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT6H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT7L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT7L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT7H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT7H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT8L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT8L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT8H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT8H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT9L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT9L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT9H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT9H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT10L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT10L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT10H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT10H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT11L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT11L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT11H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT11H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT12L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT12L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT12H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT12H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT13L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT13L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT13H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT13H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT14L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT14L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT14H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT14H_OFFSET)
|
||||
#define KINETIS_DAC1_DAT15L (KINETIS_DAC1_BASE+KINETIS_DAC_DAT15L_OFFSET)
|
||||
#define KINETIS_DAC1_DAT15H (KINETIS_DAC1_BASE+KINETIS_DAC_DAT15H_OFFSET)
|
||||
#define KINETIS_DAC1_SR (KINETIS_DAC1_BASE+KINETIS_DAC_SR_OFFSET)
|
||||
#define KINETIS_DAC1_C0 (KINETIS_DAC1_BASE+KINETIS_DAC_C0_OFFSET)
|
||||
#define KINETIS_DAC1_C1 (KINETIS_DAC1_BASE+KINETIS_DAC_C1_OFFSET)
|
||||
#define KINETIS_DAC1_C2 (KINETIS_DAC1_BASE+KINETIS_DAC_C2_OFFSET)
|
||||
|
||||
/* Register Bit Definitions *****************************************************************/
|
||||
|
||||
/* DAC Data Low Register (8-bits of data DATA[7:0]) */
|
||||
/* DAC Data High Register */
|
||||
|
||||
#define DAC_DAT0H_MASK (0x0f) /* Bits 0-3: DATA[11:8] */
|
||||
|
||||
/* DAC Status Register */
|
||||
|
||||
#define DAC_SR_DACBFRPBF (1 << 0) /* Bit 0: DAC buffer read pointer bottom position flag */
|
||||
#define DAC_SR_DACBFRPTF (1 << 1) /* Bit 1: DAC buffer read pointer top position flag */
|
||||
#define DAC_SR_DACBFWMF (1 << 2) /* Bit 2: DAC buffer watermark flag
|
||||
/* Bits 3-7: Reserved */
|
||||
/* DAC Control Register */
|
||||
|
||||
#define DAC_C0_DACBBIEN (1 << 0) /* Bit 0: DAC buffer read pointer bottom flag interrupt enable */
|
||||
#define DAC_C0_DACBTIEN (1 << 1) /* Bit 1: DAC buffer read pointer top flag interrupt enable */
|
||||
#define DAC_C0_LPEN (1 << 3) /* Bit 3: DAC low power control */
|
||||
#define DAC_C0_DACBWIEN (1 << 2) /* Bit 2: DAC buffer watermark interrupt enable */
|
||||
#define DAC_C0_DACSWTRG (1 << 4) /* Bit 4: DAC software trigger */
|
||||
#define DAC_C0_DACTRGSEL (1 << 5) /* Bit 5: DAC trigger select */
|
||||
#define DAC_C0_DACRFS (1 << 6) /* Bit 6: DAC Reference Select */
|
||||
#define DAC_C0_DACEN (1 << 7) /* Bit 7: DAC enable */
|
||||
|
||||
/* DAC Control Register 1 */
|
||||
|
||||
#define DAC_C1_DACBFEN (1 << 0) /* Bit nn: DAC buffer enable */
|
||||
#define DAC_C1_DACBFMD_SHIFT (1) /* Bits 1-2: DAC buffer work mode select00 Normal Mode */
|
||||
#define DAC_C1_DACBFMD_MASK (3 << DAC_C1_DACBFMD_SHIFT)
|
||||
# define DAC_C1_DACBFMD_NORMAL (0 << DAC_C1_DACBFMD_SHIFT) /* Normal Mode */
|
||||
# define DAC_C1_DACBFMD_SWING (1 << DAC_C1_DACBFMD_SHIFT) /* Swing Mode */
|
||||
# define DAC_C1_DACBFMD_OTSCAN (2 << DAC_C1_DACBFMD_SHIFT) /* One-Time Scan Mode */
|
||||
#define DAC_C1_DACBFWM_SHIFT (3) /* Bits 3-4: DAC buffer watermark select */
|
||||
#define DAC_C1_DACBFWM_MASK (3 << DAC_C1_DACBFWM_SHIFT)
|
||||
# define DAC_C1_DACBFWM_1WORD (0 << DAC_C1_DACBFWM_SHIFT)
|
||||
# define DAC_C1_DACBFWM_2WORDS (1 << DAC_C1_DACBFWM_SHIFT)
|
||||
# define DAC_C1_DACBFWM_3WORDS (2 << DAC_C1_DACBFWM_SHIFT)
|
||||
# define DAC_C1_DACBFWM_4WORDS (3 << DAC_C1_DACBFWM_SHIFT)
|
||||
/* Bits 5-6: Reserved */
|
||||
#define DAC_C1_DMAEN (1 << 7) /* Bit 7: DMA enable select */
|
||||
|
||||
/* DAC Control Register 2 */
|
||||
|
||||
#define DAC_C2_DACBFRP_SHIFT (4) /* Bits 4-7: DAC buffer read pointer */
|
||||
#define DAC_C2_DACBFRP_MASK (15 << DAC_C2_DACBFRP_SHIFT)
|
||||
#define DAC_C2_DACBFUP_SHIFT (0) /* Bits 0-3: DAC buffer upper limit */
|
||||
#define DAC_C2_DACBFUP_MASK (15 << DAC_C2_DACBFUP_SHIFT)
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_DACE_H */
|
||||
@ -110,7 +110,7 @@
|
||||
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
|
||||
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
|
||||
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
|
||||
# define KINETIS_PDB_BASE 0x40036000 /* Programmable delay block */
|
||||
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
|
||||
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
|
||||
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */
|
||||
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */
|
||||
@ -241,7 +241,7 @@
|
||||
# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */
|
||||
# define KINETIS_CRC_BASE 0x40032000 /* CRC */
|
||||
# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */
|
||||
# define KINETIS_PDB_BASE 0x40036000 /* Programmable delay block */
|
||||
# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */
|
||||
# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */
|
||||
# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */
|
||||
# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */
|
||||
|
||||
255
arch/arm/src/kinetis/kinetis_pdb.h
Normal file
255
arch/arm/src/kinetis/kinetis_pdb.h
Normal file
@ -0,0 +1,255 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/kinetis/kinetis_pdb.h
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PDB_H
|
||||
#define __ARCH_ARM_SRC_KINETIS_KINETIS_PDB_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/* Register Offsets *************************************************************************/
|
||||
|
||||
#define KINETIS_PDB_SC_OFFSET 0x0000 /* Status and Control Register */
|
||||
#define KINETIS_PDB_MOD_OFFSET 0x0004 /* Modulus Register */
|
||||
#define KINETIS_PDB_CNT_OFFSET 0x0008 /* Counter Register */
|
||||
#define KINETIS_PDB_IDLY_OFFSET 0x000c /* Interrupt Delay Register */
|
||||
|
||||
#define KINETIS_PDB_CH_OFFSET(n) (0x0010+(0x28*(n)) /* Channel n */
|
||||
#define KINETIS_PDB_CHC1_OFFSET 0x0000 /* Channel n Control Register 1 */
|
||||
#define KINETIS_PDB_CHS_OFFSET 0x0004 /* Channel n Status Register */
|
||||
#define KINETIS_PDB_CHDLY0_OFFSET 0x0008 /* Channel n Delay 0 Register */
|
||||
#define KINETIS_PDB_CHDLY1_OFFSET 0x000c /* Channel n Delay 1 Register */
|
||||
|
||||
#define KINETIS_PDB_CH0C1_OFFSET 0x0010 /* Channel 0 Control Register 1 */
|
||||
#define KINETIS_PDB_CH0S_OFFSET 0x0014 /* Channel 0 Status Register */
|
||||
#define KINETIS_PDB_CH0DLY0_OFFSET 0x0018 /* Channel 0 Delay 0 Register */
|
||||
#define KINETIS_PDB_CH0DLY1_OFFSET 0x001c /* Channel 0 Delay 1 Register */
|
||||
|
||||
#define KINETIS_PDB_CH1C1_OFFSET 0x0038 /* Channel 1 Control Register 1 */
|
||||
#define KINETIS_PDB_CH1S_OFFSET 0x003c /* Channel 1 Status Register */
|
||||
#define KINETIS_PDB_CH1DLY0_OFFSET 0x0040 /* Channel 1 Delay 0 Register */
|
||||
#define KINETIS_PDB_CH1DLY1_OFFSET 0x0044 /* Channel 1 Delay 1 Register */
|
||||
|
||||
#define KINETIS_PDB_INT_OFFSET(n) (0x0150+((n)<<3) /* DAC Interval n offset */
|
||||
#define KINETIS_PDB_DACINTC_OFFSET 0x0000 /* DAC Interval Trigger n Control Register */
|
||||
#define KINETIS_PDB_DACINT_OFFSET 0x0004 /* DAC Interval n Register */
|
||||
|
||||
#define KINETIS_PDB_DACINTC0_OFFSET 0x0150 /* DAC Interval Trigger 0 Control Register */
|
||||
#define KINETIS_PDB_DACINT0_OFFSET 0x0154 /* DAC Interval 0 Register */
|
||||
|
||||
#define KINETIS_PDB_DACINTC1_OFFSET 0x0158 /* DAC Interval Trigger 1 Control Register */
|
||||
#define KINETIS_PDB_DACINT1_OFFSET 0x015c /* DAC Interval 1 Register */
|
||||
|
||||
#define KINETIS_PDB_PO0EN_OFFSET 0x0190 /* Pulse-Out 0 Enable Register */
|
||||
#define KINETIS_PDB_PO0DLY_OFFSET 0x0194 /* Pulse-Out 0 Delay Register */
|
||||
|
||||
/* Register Addresses ***********************************************************************/
|
||||
|
||||
#define KINETIS_PDB0_SC (KINETIS_PDB0_BASE+KINETIS_PDB_SC_OFFSET)
|
||||
#define KINETIS_PDB0_MOD (KINETIS_PDB0_BASE+KINETIS_PDB_MOD_OFFSET)
|
||||
#define KINETIS_PDB0_CNT (KINETIS_PDB0_BASE+KINETIS_PDB_CNT_OFFSET)
|
||||
#define KINETIS_PDB0_IDLY (KINETIS_PDB0_BASE+KINETIS_PDB_IDLY_OFFSET)
|
||||
|
||||
#define KINETIS_PDB0_CH_BASE(n) (KINETIS_PDB0_BASE+KINETIS_PDB_CH_OFFSET(n))
|
||||
#define KINETIS_PDB0_CHC1(n) (KINETIS_PDB_CH_BASE(n)+KINETIS_PDB_CHC1_OFFSET)
|
||||
#define KINETIS_PDB0_CHS(n) (KINETIS_PDB_CH_BASE(n)+KINETIS_PDB_CHS_OFFSET)
|
||||
#define KINETIS_PDB0_CHDLY0(n) (KINETIS_PDB_CH_BASE(n)+KINETIS_PDB_CHDLY0_OFFSET)
|
||||
#define KINETIS_PDB0_CHDLY1(n) (KINETIS_PDB_CH_BASE(n)+KINETIS_PDB_CHDLY1_OFFSET)
|
||||
|
||||
#define KINETIS_PDB0_CH0C1 (KINETIS_PDB0_BASE+KINETIS_PDB_CH0C1_OFFSET)
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#define KINETIS_PDB0_CH0S (KINETIS_PDB0_BASE+KINETIS_PDB_CH0S_OFFSET)
|
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#define KINETIS_PDB0_CH0DLY0 (KINETIS_PDB0_BASE+KINETIS_PDB_CH0DLY0_OFFSET)
|
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#define KINETIS_PDB0_CH0DLY1 (KINETIS_PDB0_BASE+KINETIS_PDB_CH0DLY1_OFFSET)
|
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|
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#define KINETIS_PDB0_CH1C1 (KINETIS_PDB0_BASE+KINETIS_PDB_CH1C1_OFFSET)
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#define KINETIS_PDB0_CH1S (KINETIS_PDB0_BASE+KINETIS_PDB_CH1S_OFFSET)
|
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#define KINETIS_PDB0_CH1DLY0 (KINETIS_PDB0_BASE+KINETIS_PDB_CH1DLY0_OFFSET)
|
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#define KINETIS_PDB0_CH1DLY1 (KINETIS_PDB0_BASE+KINETIS_PDB_CH1DLY1_OFFSET)
|
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#define KINETIS_PDB0_INT_BASE(n) (KINETIS_PDB0_BASE+KINETIS_PDB_INT_OFFSET(n))
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#define KINETIS_PDB0_DACINTC(n) (KINETIS_PDB_INT_BASE(n)+KINETIS_PDB_DACINTC_OFFSET)
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#define KINETIS_PDB0_DACINT(n) (KINETIS_PDB_INT_BASE(n)+KINETIS_PDB_DACINT_OFFSET)
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#define KINETIS_PDB0_DACINTC0 (KINETIS_PDB0_BASE+KINETIS_PDB_DACINTC0_OFFSET)
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#define KINETIS_PDB0_DACINT0 (KINETIS_PDB0_BASE+KINETIS_PDB_DACINT0_OFFSET)
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#define KINETIS_PDB0_DACINTC1 (KINETIS_PDB0_BASE+KINETIS_PDB_DACINTC1_OFFSET)
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#define KINETIS_PDB0_DACINT1 (KINETIS_PDB0_BASE+KINETIS_PDB_DACINT1_OFFSET)
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#define KINETIS_PDB0_PO0EN (KINETIS_PDB0_BASE+KINETIS_PDB_PO0EN_OFFSET)
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#define KINETIS_PDB0_PO0DLY (KINETIS_PDB0_BASE+KINETIS_PDB_PO0DLY_OFFSET)
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/* Register Bit Definitions *****************************************************************/
|
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/* Status and Control Register */
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#define PDB_SC_LDOK (1 << 0) /* Bit 0: Load OK */
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#define PDB_SC_CONT (1 << 1) /* Bit 1: Continuous Mode Enable */
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#define PDB_SC_MULT_SHIFT (2) /* Bits 2-3: Multiplication Factor Select for Prescaler */
|
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#define PDB_SC_MULT_MASK (3 << PDB_SC_MULT_SHIFT)
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# define PDB_SC_MULT_1 (0 << PDB_SC_MULT_SHIFT)
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# define PDB_SC_MULT_10 (1 << PDB_SC_MULT_SHIFT)
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# define PDB_SC_MULT_20 (2 << PDB_SC_MULT_SHIFT)
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# define PDB_SC_MULT_40 (3 << PDB_SC_MULT_SHIFT)
|
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/* Bit 4: Reserved */
|
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#define PDB_SC_PDBIE (1 << 5) /* Bit 5: PDB Interrupt Enable */
|
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#define PDB_SC_PDBIF (1 << 6) /* Bit 6: PDB Interrupt Flag */
|
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#define PDB_SC_PDBEN (1 << 7) /* Bit 7: PDB Enable */
|
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#define PDB_SC_TRGSEL_SHIFT (8) /* Bits 8-11: Trigger Input Source Select */
|
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#define PDB_SC_TRGSEL_MASK (15 << PDB_SC_TRGSEL_SHIFT)
|
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# define PDB_SC_TRGSEL_TRGIN0 (0 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 0 */
|
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# define PDB_SC_TRGSEL_TRGIN1 (1 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 1 */
|
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# define PDB_SC_TRGSEL_TRGIN2 (2 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 2 */
|
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# define PDB_SC_TRGSEL_TRGIN3 (3 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 3 */
|
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# define PDB_SC_TRGSEL_TRGIN4 (4 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 4 */
|
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# define PDB_SC_TRGSEL_TRGIN5 (5 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 5 */
|
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# define PDB_SC_TRGSEL_TRGIN6 (6 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 6 */
|
||||
# define PDB_SC_TRGSEL_TRGIN7 (7 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 7 */
|
||||
# define PDB_SC_TRGSEL_TRGIN8 (8 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 8 */
|
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# define PDB_SC_TRGSEL_TRGIN9 (9 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 9 */
|
||||
# define PDB_SC_TRGSEL_TRGIN10 (10 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 0 */
|
||||
# define PDB_SC_TRGSEL_TRGIN11 (11 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 1 */
|
||||
# define PDB_SC_TRGSEL_TRGIN12 (12 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 2 */
|
||||
# define PDB_SC_TRGSEL_TRGIN13 (13 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 3 */
|
||||
# define PDB_SC_TRGSEL_TRGIN14 (14 << PDB_SC_TRGSEL_SHIFT) /* Trigger-In 4 */
|
||||
# define PDB_SC_TRGSEL_TRGSW (15 << PDB_SC_TRGSEL_SHIFT) /* Software trigger */
|
||||
#define PDB_SC_PRESCALER_SHIFT (12) /* Bits 12-14: Prescaler Divider Select */
|
||||
#define PDB_SC_PRESCALER_MASK (7 << PDB_SC_PRESCALER_SHIFT)
|
||||
# define PDB_SC_PRESCALER_DIVM (0 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / MULT */
|
||||
# define PDB_SC_PRESCALER_DIV2M (1 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 2*MULT */
|
||||
# define PDB_SC_PRESCALER_DIV4M (2 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 4*MULT */
|
||||
# define PDB_SC_PRESCALER_DIV8M (3 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 8*MULT */
|
||||
# define PDB_SC_PRESCALER_DIV16M (4 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 16*MULT */
|
||||
# define PDB_SC_PRESCALER_DIV32M (5 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 32*MULT */
|
||||
# define PDB_SC_PRESCALER_DIV64M (6 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 64*MULT */
|
||||
# define PDB_SC_PRESCALER_DIV128M (7 << PDB_SC_PRESCALER_SHIFT) /* Peripheral clock / 128*MULT */
|
||||
#define PDB_SC_DMAEN (1 << 15) /* Bit 15: DMA Enable */
|
||||
#define PDB_SC_SWTRIG (1 << 16) /* Bit 16: Software Trigger */
|
||||
#define PDB_SC_PDBEIE (1 << 17) /* Bit 17: PDB Sequence Error Interrupt Enable */
|
||||
#define PDB_SC_LDMOD_SHIFT (18) /* Bits 18-19: Load Mode Select */
|
||||
#define PDB_SC_LDMOD_MASK (3 << PDB_SC_LDMOD_SHIFT)
|
||||
# define PDB_SC_LDMOD_LDOK (0 << PDB_SC_LDMOD_SHIFT) /* Load after 1 written to LDOK */
|
||||
# define PDB_SC_LDMOD_PDBCNT (1 << PDB_SC_LDMOD_SHIFT) /* Load when the PDB counter = MOD */
|
||||
# define PDB_SC_LDMOD_TRIGGER (2 << PDB_SC_LDMOD_SHIFT) /* Load when trigger input event */
|
||||
# define PDB_SC_LDMOD_EITHER (3 << PDB_SC_LDMOD_SHIFT) /* Load when either occurs */
|
||||
/* Bits 20-31: Reserved */
|
||||
/* Modulus Register */
|
||||
|
||||
/* Bits 16-31: Reserved */
|
||||
#define PDB_MOD_MASK (0xffff) /* Bits 0-15: PDB Modulus */
|
||||
|
||||
/* Counter Register */
|
||||
|
||||
/* Bits 16-31: Reserved */
|
||||
#define PDB_CNT_MASK (0xffff) /* Bits 0-15: PDB Counter */
|
||||
|
||||
/* Interrupt Delay Register */
|
||||
|
||||
/* Bits 16-31: Reserved */
|
||||
#define PDB_IDLY_MASK (0xffff) /* Bits 0-15: PDB Interrupt Delay */
|
||||
|
||||
/* Channel n Control Register 1 */
|
||||
|
||||
#define PDB_CHC1_EN_SHIFT (0) /* Bits 0-7: Pre-Trigger Enable */
|
||||
#define PDB_CHC1_EN_MASK (0xff << PDB_CHC1_EN_SHIFT)
|
||||
# define PDB_CHC1_EN_CHAN(n) ((1 << (n)) << PDB_CHC1_EN_SHIFT)
|
||||
#define PDB_CHC1_TOS_SHIFT (8) /* Bits 8-15: Pre-Trigger Output Select */
|
||||
#define PDB_CHC1_TOS_MASK (0xff << PDB_CHC1_TOS_SHIFT)
|
||||
# define PDB_CHC1_TOS_CHAN(n) ((1 << (n)) << PDB_CHC1_TOS_SHIFT)
|
||||
#define PDB_CHC1_BB_SHIFT (16) /* Bits 16-23: Pre-Trigger Back-to-Back Operation Enable */
|
||||
#define PDB_CHC1_BB_MASK (0xff << PDB_CHC1_BB_SHIFT)
|
||||
# define PDB_CHC1_BB_CHAN(n) ((1 << (n)) << PDB_CHC1_BB_SHIFT)
|
||||
/* Bits 24-31: Reserved */
|
||||
/* Channel n Status Register */
|
||||
|
||||
#define PDB_CHS_ERR_SHIFT (0) /* Bits 0-7: PDB Channel Sequence Error Flags */
|
||||
#define PDB_CHS_ERR_MASK (0xff << PDB_CHS_ERR_SHIFT)
|
||||
# define PDB_CHS1_ERR_CHAN(n) ((1 << (n)) << PDB_CHS_ERR_SHIFT)
|
||||
/* Bits 8-15: Reserved */
|
||||
#define PDB_CHS_CF_SHIFT (16) /* Bits 16-23: PDB Channel Flags */
|
||||
#define PDB_CHS_CF_MASK (0xff << PDB_CHS_CF_SHIFT)
|
||||
# define PDB_CHS_CF_CHAN(n) ((1 << (n)) << PDB_CHS_CF_SHIFT)
|
||||
/* Bits 24-31: Reserved */
|
||||
/* Channel n Delay 0 Register */
|
||||
/* Bits 16-31: Reserved */
|
||||
#define PDB_CHDLY0_MASK (0xffff) /* Bits 0-15: PDB Channel Delay */
|
||||
|
||||
/* Channel n Delay 1 Register */
|
||||
/* Bits 16-31: Reserved */
|
||||
#define PDB_CHDLY1_MASK (0xffff) /* Bits 0-15: PDB Channel Delay */
|
||||
|
||||
/* DAC Interval Trigger n Control Register */
|
||||
|
||||
#define PDB_DACINTC_TOE (1 << 0) /* Bit 0: DAC Interval Trigger Enable */
|
||||
#define PDB_DACINTC_EXT (1 << 1) /* Bit 1: DAC External Trigger Input Enable */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* DAC Interval n Register */
|
||||
/* Bits 16-31: Reserved */
|
||||
#define PDB_DACINT_MASK (0xffff) /* Bits 0-15: DAC Interval */
|
||||
|
||||
/* Pulse-Out 0 Enable Register */
|
||||
#define PDB__
|
||||
/* Bits 6-31: Reserved */
|
||||
#define PDB_PO0EN_MASK (0xff) /* Bits 0-7: PDB Pulse-Out Enable */
|
||||
|
||||
/* Pulse-Out 0 Delay Register */
|
||||
|
||||
#define PDB_PO0DLY_DLY1_SHIFT (16) /* Bits 16-31: PDB Pulse-Out Delay 1 */
|
||||
#define PDB_PO0DLY_DLY1_MASK (0xffff << PDB_PO0DLY_DLY1_SHIFT)
|
||||
#define PDB_PO0DLY_DLY2_SHIFT (0) /* Bits 0-15: PDB Pulse-Out Delay 2 */
|
||||
#define PDB_PO0DLY_DLY2_MASK (0xffff << PDB_PO0DLY_DLY2_SHIFT)
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PDB_H */
|
||||
Loading…
Reference in New Issue
Block a user