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Merge remote-tracking branch 'origin/master' into ieee802154

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This commit is contained in:
Gregory Nutt 2017-03-23 07:54:46 -06:00
commit 56559c3330
6 changed files with 107 additions and 28 deletions
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14
arch/arm/src/stm32/Kconfig
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@ -2629,9 +2629,17 @@ config STM32_FLASH_PREFETCH
default y if STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446
default n
---help---
Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled
on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
properly and enabling this option may interfere with ADC accuracy.
Enable FLASH prefetch and F2 and F4 parts (FLASH pre-fetch is always enabled
on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
properly and enabling this option may interfere with ADC accuracy.
config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
bool "Workaround for FLASH data cache corruption"
default n
---help---
Enable the workaround to fix flash data cache corruption when reading
from one flash bank while writing on other flash bank. See your STM32
errata to check if your STM32 is affected by this problem.
choice
prompt "JTAG Configuration"

27
arch/arm/src/stm32/chip/stm32_flash.h
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@ -324,29 +324,30 @@
# define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */
# endif
#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
# define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
# define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
# define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT)
# define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
# define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define FLASH_CR_SNB_MASK (31 << FLASH_CR_SNB_SHIFT)
# define FLASH_CR_SNB(n) (((n % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */
#else
# define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT)
# define FLASH_CR_SNB(n) ((n) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..11 */
#endif
# define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
# define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
# define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00 program x8 */
# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* 01 program x16 */
# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* 10 program x32 */
# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* 11 program x64 */
# define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */
# define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
# define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
# define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
# define FLASH_CR_STRT (1 << 16) /* Bit 16: Start Erase */
# define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
# define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
# define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
#endif
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */
# define FLASH_CR_MER1 (1 << 15) /* Bit 15: Mass Erase sectors 12..23 */
#endif
/* Flash Option Control Register (OPTCR) */
@ -374,7 +375,7 @@
/* Flash Option Control Register (OPTCR1) */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-27: Not write protect (high bank) */
# define FLASH_OPTCR1_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT)
# define FLASH_OPTCR1_BFB2_SHIFT (4) /* Bits 4: Dual-bank Boot option byte */
@ -383,7 +384,7 @@
#endif
#if defined(CONFIG_STM32_STM32F446)
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-23: Not write protect (high bank) */
# define FLASH_OPTCR1_NWRP_SHIFT (16) /* Bits 16-23: Not write protect (high bank) */
# define FLASH_OPTCR1_NWRP_MASK (0xff << FLASH_OPTCR_NWRP_SHIFT)
#endif

86
arch/arm/src/stm32/stm32_flash.c
View File

@ -47,6 +47,10 @@
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <stdbool.h>
#include <semaphore.h>
#include <assert.h>
#include <errno.h>
#include "stm32_flash.h"
@ -80,14 +84,30 @@
#define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPERR
#endif
/************************************************************************************
* Private Data
************************************************************************************/
static sem_t g_sem = SEM_INITIALIZER(1);
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
void stm32_flash_unlock(void)
static void sem_lock(void)
{
while (sem_wait(&g_sem) < 0)
{
DEBUGASSERT(errno == EINTR);
}
}
static inline void sem_unlock(void)
{
sem_post(&g_sem);
}
static void flash_unlock(void)
{
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
@ -103,14 +123,46 @@ void stm32_flash_unlock(void)
}
}
void stm32_flash_lock(void)
static void flash_lock(void)
{
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
}
static void data_cache_disable(void)
{
modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0);
}
static void data_cache_enable(void)
{
/* Reset data cache */
modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST);
/* Enable data cache */
modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN);
}
/************************************************************************************
* Public Functions
************************************************************************************/
void stm32_flash_unlock(void)
{
sem_lock();
flash_unlock();
sem_unlock();
}
void stm32_flash_lock(void)
{
sem_lock();
flash_lock();
sem_unlock();
}
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
size_t up_progmem_pagesize(size_t page)
{
return STM32_FLASH_PAGESIZE;
@ -231,6 +283,8 @@ ssize_t up_progmem_erasepage(size_t page)
return -EFAULT;
}
sem_lock();
#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
@ -240,7 +294,7 @@ ssize_t up_progmem_erasepage(size_t page)
/* Get flash ready and begin erasing single page */
stm32_flash_unlock();
flash_unlock();
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE);
@ -259,6 +313,7 @@ ssize_t up_progmem_erasepage(size_t page)
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0);
sem_unlock();
/* Verify */
if (up_progmem_ispageerased(page) == 0)
@ -320,16 +375,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
return -EFAULT;
}
sem_lock();
#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
sem_unlock();
return -EPERM;
}
#endif
/* Get flash ready and begin flashing */
stm32_flash_unlock();
flash_unlock();
#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
data_cache_disable();
#endif
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
@ -351,17 +413,25 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR)
{
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
sem_unlock();
return -EROFS;
}
if (getreg16(addr) != *hword)
{
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
sem_unlock();
return -EIO;
}
}
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
data_cache_enable();
#endif
sem_unlock();
return written;
}

2
configs/Makefile
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@ -89,7 +89,7 @@ OBJS = $(AOBJS) $(COBJS)
BIN = libconfigs$(LIBEXT)
all: $(BIN)
.PHONY: depend ccontext clean_context clean distclean
.PHONY: depend context clean_context clean distclean
$(AOBJS): %$(OBJEXT): %.S
$(call ASSEMBLE, $<, $@)

2
configs/clicker2-stm32/src/stm32_spi.c
View File

@ -63,7 +63,7 @@
* Name: stm32_spidev_initialize
*
* Description:
* Called to configure SPI chip select GPIO pins for the stm32f4discovery board.
* Called to configure SPI chip select GPIO pins for the Mikroe Clicker2 STM32 board.
*
************************************************************************************/

4
include/semaphore.h
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@ -105,14 +105,14 @@ typedef struct sem_s sem_t;
#ifdef CONFIG_PRIORITY_INHERITANCE
# if CONFIG_SEM_PREALLOCHOLDERS > 0
# define SEM_INITIALIZER(c) \
{(c), 0, NULL} /* semcount, flags, hhead */
{(c), 0, NULL} /* semcount, flags, hhead */
# else
# define SEM_INITIALIZER(c) \
{(c), 0, {SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}} /* semcount, flags, holder[2] */
# endif
#else
# define SEM_INITIALIZER(c) \
{(c)} /* semcount */
{(c)} /* semcount */
#endif
/****************************************************************************