Finish ADC header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3013 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -51,6 +51,13 @@
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* Definitions
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****************************************************************************/
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/* General notes about the AVR32 ABI:
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*
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* Scratch/Volatile Registers: r8-r12
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* Preserved/Static Registers: r0-r7
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* Parameter Passing: r12-R8 (in that order)
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*/
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/* Register state save array indices.
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*
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* The following registers are saved by the AVR32 hardware (for the case of
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@ -48,15 +48,136 @@
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/* Register offsets *****************************************************************/
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#warning "Missing Logic"
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#define AVR32_ADC_CR_OFFSET 0x000 /* Control Register */
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#define AVR32_ADC_MR_OFFSET 0x004 /* Mode Register */
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#define AVR32_ADC_CHER_OFFSET 0x010 /* Channel Enable Register */
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#define AVR32_ADC_CHDR_OFFSET 0x014 /* Channel Disable Register */
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#define AVR32_ADC_CHSR_OFFSET 0x018 /* Channel Status Register */
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#define AVR32_ADC_SR_OFFSET 0x01c /* Status Register */
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#define AVR32_ADC_LCDR_OFFSET 0x020 /* Last Converted Data Register */
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#define AVR32_ADC_IER_OFFSET 0x024 /* Interrupt Enable Register */
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#define AVR32_ADC_IDR_OFFSET 0x028 /* Interrupt Disable Register */
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#define AVR32_ADC_IMR_OFFSET 0x02c /* Interrupt Mask Register */
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#define AVR32_ADC_CDR_OFFSET(n) (0x030+((n)<<2))
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#define AVR32_ADC_CDR0_OFFSET 0x030 /* Channel Data Register 0 */
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#define AVR32_ADC_CDR1_OFFSET 0x034 /* Channel Data Register 1 */
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#define AVR32_ADC_CDR2_OFFSET 0x038 /* Channel Data Register 2 */
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#define AVR32_ADC_CDR3_OFFSET 0x03c /* Channel Data Register 3 */
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#define AVR32_ADC_CDR4_OFFSET 0x040 /* Channel Data Register 4 */
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#define AVR32_ADC_CDR5_OFFSET 0x044 /* Channel Data Register 5 */
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#define AVR32_ADC_CDR6_OFFSET 0x048 /* Channel Data Register 6 */
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#define AVR32_ADC_CDR7_OFFSET 0x04c /* Channel Data Register 7 */
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#define AVR32_ADC_VERSION_OFFSET 0x0fc /* Version Register */
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/* Register Addresses ***************************************************************/
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#warning "Missing Logic"
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#define AVR32_ADC_CR (AVR32_ADC_BASE+AVR32_ADC_CR_OFFSET)
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#define AVR32_ADC_MR (AVR32_ADC_BASE+AVR32_ADC_MR_OFFSET)
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#define AVR32_ADC_CHER (AVR32_ADC_BASE+AVR32_ADC_CHER_OFFSET)
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#define AVR32_ADC_CHDR (AVR32_ADC_BASE+AVR32_ADC_CHDR_OFFSET)
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#define AVR32_ADC_CHSR (AVR32_ADC_BASE+AVR32_ADC_CHSR_OFFSET)
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#define AVR32_ADC_SR (AVR32_ADC_BASE+AVR32_ADC_SR_OFFSET)
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#define AVR32_ADC_LCDR (AVR32_ADC_BASE+AVR32_ADC_LCDR_OFFSET)
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#define AVR32_ADC_IER (AVR32_ADC_BASE+AVR32_ADC_IER_OFFSET)
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#define AVR32_ADC_IDR (AVR32_ADC_BASE+AVR32_ADC_IDR_OFFSET)
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#define AVR32_ADC_IMR (AVR32_ADC_BASE+AVR32_ADC_IMR_OFFSET)
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#define AVR32_ADC_CDR(n) (AVR32_ADC_BASE+AVR32_ADC_CDR_OFFSET(n))
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#define AVR32_ADC_CDR0 (AVR32_ADC_BASE+AVR32_ADC_CDR0_OFFSET)
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#define AVR32_ADC_CDR1 (AVR32_ADC_BASE+AVR32_ADC_CDR1_OFFSET)
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#define AVR32_ADC_CDR2 (AVR32_ADC_BASE+AVR32_ADC_CDR2_OFFSET)
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#define AVR32_ADC_CDR3 (AVR32_ADC_BASE+AVR32_ADC_CDR3_OFFSET)
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#define AVR32_ADC_CDR4 (AVR32_ADC_BASE+AVR32_ADC_CDR4_OFFSET)
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#define AVR32_ADC_CDR5 (AVR32_ADC_BASE+AVR32_ADC_CDR5_OFFSET)
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#define AVR32_ADC_CDR6 (AVR32_ADC_BASE+AVR32_ADC_CDR6_OFFSET)
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#define AVR32_ADC_CDR7 (AVR32_ADC_BASE+AVR32_ADC_CDR7_OFFSET)
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#define AVR32_ADC_VERSION (AVR32_ADC_BASE+AVR32_ADC_VERSION_OFFSET)
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/* Register Bit-field Definitions ***************************************************/
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#warning "Missing Logic"
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/* Control Register Bit-field Definitions */
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#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */
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#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */
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/* Mode Register Bit-field Definitions */
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#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */
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#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */
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#define ADC_MR_TRGSEL_MASK (7 << ADC_MR_TRGSEL_SHIFT)
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# define ADC_MR_TRGSEL_TRIG(n) ((n) << ADC_MR_TRGSEL_SHIFT) /* Internal trigger n */
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# define ADC_MR_TRGSEL_TRIG0 (0 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 0 */
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# define ADC_MR_TRGSEL_TRIG1 (1 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 1 */
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# define ADC_MR_TRGSEL_TRIG2 (2 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 2 */
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# define ADC_MR_TRGSEL_TRIG3 (3 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 3 */
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# define ADC_MR_TRGSEL_TRIG4 (4 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 4 */
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# define ADC_MR_TRGSEL_TRIG5 (5 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 5 */
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# define ADC_MR_TRGSEL_TRIG6 (6 << ADC_MR_TRGSEL_SHIFT) /* Internal trigger 6 */
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# define ADC_MR_TRGSEL_EXT (7 << ADC_MR_TRGSEL_SHIFT) /* External trigger */
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#define ADC_MR_LOWRES (1 << 4) /* Bit 4: Resolution */
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#define ADC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
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#define ADC_MR_PRESCAL_SHIFT (8) /* Bits 8-15: Prescaler Rate Selection */
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#define ADC_MR_PRESCAL_MASK (0xff << ADC_MR_PRESCAL_SHIFT)
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#define ADC_MR_STARTUP_SHIFT (16) /* Bits 16-22: Start Up Time */
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#define ADC_MR_STARTUP_MASK (0x7f << ADC_MR_STARTUP_SHIFT)
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#define ADC_MR_SHTIM_SHIFT (24) /* Bits 24-27 Sample & Hold Time */
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#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT)
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/* Channel Enable Register Bit-field Definitions */
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/* Channel Disable Register Bit-field Definitions */
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/* Channel Status Register Bit-field Definitions */
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#define ADC_CHAN(n) (1 << (n))
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#define ADC_CHAN0 (1 << 0)
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#define ADC_CHAN1 (1 << 1)
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#define ADC_CHAN2 (1 << 2)
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#define ADC_CHAN3 (1 << 3)
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#define ADC_CHAN4 (1 << 4)
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#define ADC_CHAN5 (1 << 5)
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#define ADC_CHAN6 (1 << 6)
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#define ADC_CHAN7 (1 << 7)
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/* Status Register Bit-field Definitions */
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/* Interrupt Enable Register Bit-field Definitions */
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/* Interrupt Disable Register Bit-field Definitions */
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/* Interrupt Mask Register Bit-field Definitions */
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#define ADC_INT_EOC(n) (1 << (n))
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#define ADC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */
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#define ADC_INT_EOC1 (1 << 1) /* Bit 1: End of Conversion 1 */
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#define ADC_INT_EOC2 (1 << 2) /* Bit 2: End of Conversion 2 */
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#define ADC_INT_EOC3 (1 << 3) /* Bit 3: End of Conversion 3 */
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#define ADC_INT_EOC4 (1 << 4) /* Bit 4: End of Conversion 4 */
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#define ADC_INT_EOC5 (1 << 5) /* Bit 5: End of Conversion 5 */
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#define ADC_INT_EOC6 (1 << 6) /* Bit 6: End of Conversion 6 */
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#define ADC_INT_EOC7 (1 << 7) /* Bit 7: End of Conversion 7 */
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#define ADC_INT_OVRE(n) (1 << ((n)+8))
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#define ADC_INT_OVRE0 (1 << 8) /* Bit 8: Overrun Error 0 */
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#define ADC_INT_OVRE1 (1 << 9) /* Bit 9: Overrun Error 1 */
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#define ADC_INT_OVRE2 (1 << 10) /* Bit 10: Overrun Error 2 */
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#define ADC_INT_OVRE3 (1 << 11) /* Bit 11: Overrun Error 3 */
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#define ADC_INT_OVRE4 (1 << 12) /* Bit 12: Overrun Error 4 */
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#define ADC_INT_OVRE5 (1 << 13) /* Bit 13: Overrun Error 5 */
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#define ADC_INT_OVRE6 (1 << 14) /* Bit 14: Overrun Error 6 */
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#define ADC_INT_OVRE7 (1 << 15) /* Bit 15: Overrun Error 7 */
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#define ADC_INT_DRDY (1 << 16) /* Bit 16: Data Ready */
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#define ADC_INT_GOVRE (1 << 17) /* Bit 17: General Overrun Error */
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#define ADC_INT_ENDRX (1 << 18) /* Bit 18: End of RX Buffer */
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#define ADC_INT_RXBUFF (1 << 19) /* Bit 19: RX Buffer Full */
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/* Last Converted Data Register Bit-field Definitions */
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#define ADC_LCDR_MASK (0x3ff)
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/* Channel Data Registers 0-7 Bit-field Definitions */
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#define ADC_CDR_MASK (0x3ff)
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/* Version Register Bit-field Definitions */
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#define ADC_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
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#define ADC_VERSION_VARIANT_MASK (15 << ADC_VERSION_VARIANT_SHIFT)
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#define ADC_VERSION_SHIFT (0) /* Bits 0-11: Version Number */
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#define ADC_VERSION_MASK (0xfff << ADC_VERSION_SHIFT)
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/************************************************************************************
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* Public Types
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@ -235,23 +235,73 @@ avr32_common:
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stm --sp, r0-r7
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/* Now call up_doirq passing the IRQ number in r12 and the base address */
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/* of the register context save area in r13. */
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/* of the register context save area in r11. */
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mov r11, sp
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/* Switch to the interrrupt stack if so configured. Move the current */
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/* stack pointer into a preserved register (r7) and set the interrupt */
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/* stack pointer. */
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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mov r7, sp
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mov sp, up_intstackbase
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movh sp, (up_intstackbase >> 0)
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#endif
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/* Call up_doirq with r12=IRQ number and r11=register save area */
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mov r12, sp
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mcall .Lup_doirq
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#warning "Missing Logic"
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rjmp $
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/* On return, r12 will hold the new address of the register context save
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* area. On an interrupt contex switch, this will (1) not be the same
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* as the value of r12 passed to up_doirq(), and (2) may not reside on
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* a stack.
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*/
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/* Restore the user stack pointer. */
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/* 07 06 05 04 03 02 01 00 SP SR PC LR 12 11 10 09 08 */
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/* ^sp */
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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mov sp, r7
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#endif
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/* On return, r12 will hold the new address of the register context */
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/* save area. On an interrupt contex switch, this will (1) not be the */
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/* same as the value of r12 passed to up_doirq(), and (2) may not */
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/* reside on a stack. */
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cp.w sp, r12
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brne 1f
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/* No context switch... do the simple return. First, restore r0-r7. */
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/* xx xx xx xx xx xx xx xx SP SR PC LR 12 11 10 09 08 */
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/* ^sp */
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ldm sp++, r0-r7
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/* Skip over the saved stack pointer and return from the interrupt. */
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/* xx xx xx xx xx xx xx xx xx SR PC LR 12 11 10 09 08 */
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/* ^sp */
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sub sp, -4
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rete
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/* Context switch... we need to do a little more work. */
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1:
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#warning "Missing Logic"
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.Lup_doirq:
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.word up_doirq
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/************************************************************************************
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* Name: up_interruptstack
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************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 3
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.bss
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.align 4
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.globl up_interruptstack
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.type up_interruptstack, object
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up_interruptstack:
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.skip (CONFIG_ARCH_INTERRUPTSTACK & ~3)
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up_intstackbase:
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.size up_interruptstack, .-up_interruptstack
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#endif
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.end
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