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arch/cortex-m/Make.defs: unify arch common source include

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Signed-off-by: chao.an <anchao@xiaomi.com>
This commit is contained in:
chao.an 2022-04-30 12:58:59 +08:00 committed by Xiang Xiao
parent a560eb5f8d
commit 5677fe2153
35 changed files with 93 additions and 645 deletions
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14
arch/arm/src/armv6-m/Make.defs
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@ -21,3 +21,17 @@
# Common ARM files
include common/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_svcall.c
CMN_CSRCS += arm_systemreset.c arm_tcbinfo.c arm_vectors.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif

34
arch/arm/src/armv7-m/Make.defs
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@ -21,3 +21,37 @@
# Common ARM files
include common/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_busfault.c arm_cache.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_initialstate.c arm_itm.c
CMN_CSRCS += arm_memfault.c arm_perf.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_tcbinfo.c
CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_vectors.c
ifeq ($(CONFIG_ARMV7M_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
endif

35
arch/arm/src/armv8-m/Make.defs
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@ -21,3 +21,38 @@
# Common ARM files
include common/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_busfault.c arm_cache.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_initialstate.c arm_itm.c
CMN_CSRCS += arm_memfault.c arm_perf.c arm_sau.c
CMN_CSRCS += arm_schedulesigaction.c arm_securefault.c arm_secure_irq.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c
CMN_CSRCS += arm_systemreset.c arm_tcbinfo.c
CMN_CSRCS += arm_trigger_irq.c arm_usagefault.c arm_vectors.c
ifeq ($(CONFIG_ARMV8M_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
ifeq ($(CONFIG_ARMV8M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
ifeq ($(CONFIG_ARMV8M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
endif

27
arch/arm/src/cxd56xx/Make.defs
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@ -20,33 +20,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_tcbinfo.c arm_vectors.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
CHIP_ASRCS += cxd56_farapistub.S
CHIP_CSRCS = cxd56_allocateheap.c cxd56_idle.c

24
arch/arm/src/efm32/Make.defs
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@ -20,30 +20,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_itm.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
CHIP_CSRCS = efm32_start.c efm32_clockconfig.c efm32_irq.c efm32_timerisr.c
CHIP_CSRCS += efm32_gpio.c efm32_lowputc.c efm32_timer.c efm32_i2c.c

16
arch/arm/src/eoss3/Make.defs
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@ -20,22 +20,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_itm.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_svcall.c
CMN_CSRCS += arm_systemreset.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
CHIP_CSRCS = eoss3_start.c eoss3_gpio.c eoss3_lowputc.c eoss3_clockconfig.c
CHIP_CSRCS += eoss3_irq.c
CHIP_CSRCS += eoss3_serial.c

26
arch/arm/src/imxrt/Make.defs
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@ -22,32 +22,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_systemreset.c
CMN_CSRCS += arm_tcbinfo.c arm_vectors.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
CMN_CSRCS += arm_cache.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
# Required i.MX RT files
CHIP_CSRCS = imxrt_allocateheap.c imxrt_start.c imxrt_clockconfig.c

28
arch/arm/src/kinetis/Make.defs
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@ -20,34 +20,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_memfault.c arm_initialstate.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_systemreset.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
# Required Kinetis files
CHIP_CSRCS = kinetis_allocateheap.c kinetis_clockconfig.c kinetis_clrpend.c

10
arch/arm/src/kl/Make.defs
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@ -20,16 +20,6 @@
include armv6-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif
CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_irq.c kl_lowputc.c
CHIP_CSRCS += kl_serial.c kl_start.c kl_cfmconfig.c

22
arch/arm/src/lc823450/Make.defs
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@ -20,25 +20,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_systemreset.c
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_svcall.c arm_trigger_irq.c
CMN_CSRCS += arm_tcbinfo.c arm_vectors.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += memcpy-armv7m.S
endif
ifeq ($(CONFIG_ARCH_MEMMOVE),y)
CMN_CSRCS += up_memmove.c
endif
CHIP_CSRCS = lc823450_allocateheap2.c lc823450_start.c lc823450_irq.c lc823450_timer.c
CHIP_CSRCS += lc823450_lowputc.c lc823450_serial.c lc823450_clockconfig.c
CHIP_CSRCS += lc823450_syscontrol.c lc823450_gpio.c
@ -75,7 +56,7 @@ CHIP_CSRCS += lc823450_spi.c
endif
ifeq ($(CONFIG_ARCH_DMA), y)
CMN_CSRCS += lc823450_dma.c
CHIP_CSRCS += lc823450_dma.c
endif
ifeq ($(CONFIG_RTC),y)
@ -134,6 +115,5 @@ CHIP_CSRCS += lc823450_userspace.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
CHIP_CSRCS += lc823450_mpuinit2.c
endif

24
arch/arm/src/lpc17xx_40xx/Make.defs
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@ -22,30 +22,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_memfault.c arm_initialstate.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_trigger_irq.c
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_svcall.c arm_systemreset.c
CMN_CSRCS += arm_tcbinfo.c arm_perf.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
# Required LPC17xx files
CHIP_CSRCS = lpc17_40_allocateheap.c lpc17_40_clockconfig.c lpc17_40_clrpend.c

19
arch/arm/src/lpc43xx/Make.defs
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@ -20,25 +20,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
CHIP_CSRCS = lpc43_allocateheap.c lpc43_cgu.c lpc43_clrpend.c lpc43_gpio.c
CHIP_CSRCS += lpc43_irq.c lpc43_pinconfig.c lpc43_rgu.c lpc43_serial.c
CHIP_CSRCS += lpc43_start.c lpc43_uart.c

19
arch/arm/src/lpc54xx/Make.defs
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@ -20,25 +20,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
CHIP_CSRCS = lpc54_start.c lpc54_clockconfig.c lpc54_irq.c lpc54_clrpend.c
CHIP_CSRCS += lpc54_allocateheap.c lpc54_lowputc.c lpc54_gpio.c lpc54_reset.c

20
arch/arm/src/max326xx/Make.defs
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@ -22,26 +22,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
# Common MAX326XX Source Files
CHIP_CSRCS = max326_start.c max326_irq.c max326_clrpend.c

30
arch/arm/src/nrf52/Make.defs
View File

@ -20,39 +20,15 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_systemreset.c
CMN_CSRCS += arm_tcbinfo.c
ifeq ($(CONFIG_NRF52_SYSTIMER_SYSTICK),y)
CMN_CSRCS += arm_systick.c nrf52_systick.c
CHIP_CSRCS += nrf52_systick.c
else
ifeq ($(CONFIG_NRF52_SYSTIMER_RTC),y)
CMN_CSRCS += nrf52_tickless_rtc.c
CHIP_CSRCS += nrf52_tickless_rtc.c
endif
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
CHIP_CSRCS = nrf52_start.c nrf52_clockconfig.c nrf52_irq.c nrf52_utils.c
CHIP_CSRCS += nrf52_start.c nrf52_clockconfig.c nrf52_irq.c nrf52_utils.c
CHIP_CSRCS += nrf52_allocateheap.c nrf52_lowputc.c nrf52_gpio.c nrf52_nvmc.c
CHIP_CSRCS += nrf52_uid.c

10
arch/arm/src/nuc1xx/Make.defs
View File

@ -20,16 +20,6 @@
include armv6-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif
CHIP_CSRCS = nuc_clockconfig.c nuc_gpio.c nuc_irq.c nuc_lowputc.c
CHIP_CSRCS += nuc_serial.c nuc_start.c

14
arch/arm/src/phy62xx/Make.defs
View File

@ -20,20 +20,10 @@
include armv6-m/Make.defs
CMN_ASRCS := $(filter-out arm_exception.S,$(CMN_ASRCS))
CMN_ASRCS += phy62xx_exception.S phy62xx_start.S
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c phy62xx_hardfault.c
CMN_CSRCS += arm_svcall.c arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_pthread_exit.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif
CHIP_CSRCS = start.c gpio.c irq.c timer.c uart.c pwrmgr.c idle.c my_printf.c
#CHIP_CSRCS = start.c gpio.c irq.c timer.c clock.c uart.c pwrmgr.c idle.c my_printf.c flash.c
CHIP_CSRCS += jump_table.c

14
arch/arm/src/rp2040/Make.defs
View File

@ -20,20 +20,6 @@
include armv6-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif
CHIP_CSRCS += rp2040_idle.c
CHIP_CSRCS += rp2040_irq.c
CHIP_CSRCS += rp2040_uart.c

10
arch/arm/src/rtl8720c/Make.defs
View File

@ -20,16 +20,6 @@
include armv8-m/Make.defs
# arch/arm/src/armv8-m
#
CMN_ASRCS += arm_exception.S arm_setjmp.S
CMN_CSRCS += arm_cache.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_itm_syslog.c arm_memfault.c arm_mpu.c arm_ramvec_attach.c
CMN_CSRCS += arm_ramvec_initialize.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_stackcheck.c arm_svcall.c arm_systick.c
CMN_CSRCS += arm_tcbinfo.c
# arch/arm/src/rtl8720c
#
CHIP_CSRCS += ameba_nvic.c ameba_heap.c ameba_idle.c ameba_uart.c ameba_start.c

9
arch/arm/src/s32k1xx/Make.defs
View File

@ -18,15 +18,6 @@
#
############################################################################
# Common ARM source files
CMN_CSRCS += arm_tcbinfo.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
# Source files common to all S32K1xx chip families.
CHIP_CSRCS = s32k1xx_start.c s32k1xx_lowputc.c s32k1xx_clockconfig.c

10
arch/arm/src/s32k1xx/s32k11x/Make.defs
View File

@ -22,16 +22,6 @@
include armv6-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_systemreset.c arm_doirq.c
CMN_CSRCS += arm_hardfault.c arm_svcall.c arm_vectors.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif
# Source file specific to the S32k11x family
CHIP_CSRCS += s32k11x_irq.c s32k11x_clockmapping.c s32k11x_periphfeatures.c

14
arch/arm/src/s32k1xx/s32k14x/Make.defs
View File

@ -22,20 +22,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c arm_systemreset.c
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c
endif
# Source file specific to the S32k11x family
CHIP_CSRCS += s32k14x_irq.c s32k14x_clrpend.c s32k14x_clockmapping.c

21
arch/arm/src/sam34/Make.defs
View File

@ -24,27 +24,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c
# Configuration-dependent common files
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
# Required SAM3/4 files
CHIP_CSRCS = sam_allocateheap.c sam_irq.c sam_lowputc.c sam_serial.c

10
arch/arm/src/samd2l2/Make.defs
View File

@ -20,16 +20,6 @@
include armv6-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif
CHIP_CSRCS = sam_irq.c sam_lowputc.c sam_port.c sam_sercom.c sam_serial.c
CHIP_CSRCS += sam_start.c sam_usart.c

21
arch/arm/src/samd5e5/Make.defs
View File

@ -24,27 +24,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_initialstate.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_svcall.c
CMN_CSRCS += arm_trigger_irq.c arm_doirq.c arm_hardfault.c arm_tcbinfo.c
# Configuration-dependent common files
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
# Required SAMD5x/E5x files
CHIP_CSRCS = sam_clockconfig.c sam_gclk.c sam_irq.c sam_lowputc.c

26
arch/arm/src/samv7/Make.defs
View File

@ -25,32 +25,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_systemreset.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_trigger_irq.c
CMN_CSRCS += arm_doirq.c arm_tcbinfo.c arm_cache.c
# Configuration-dependent common files
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
# Required SAMV7 files
CHIP_CSRCS = sam_start.c sam_clockconfig.c sam_irq.c sam_allocateheap.c

32
arch/arm/src/stm32/Make.defs
View File

@ -20,38 +20,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c
CMN_CSRCS += arm_doirq.c arm_tcbinfo.c arm_perf.c
ifeq ($(CONFIG_STM32_TICKLESS_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c
CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c

10
arch/arm/src/stm32f0l0g0/Make.defs
View File

@ -20,16 +20,6 @@
include armv6-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_initialstate.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_systemreset.c arm_doirq.c arm_hardfault.c arm_svcall.c
CMN_CSRCS += arm_vectors.c arm_tcbinfo.c
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += arm_dumpnvic.c
endif
CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c
CHIP_CSRCS += stm32_lse.c stm32_lowputc.c stm32_serial.c stm32_rcc.c

30
arch/arm/src/stm32f7/Make.defs
View File

@ -25,36 +25,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c
CMN_CSRCS += arm_tcbinfo.c arm_cache.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
# Configuration-dependent common files
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
endif
# Required STM32F7 files
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c

32
arch/arm/src/stm32h7/Make.defs
View File

@ -25,41 +25,13 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c
CMN_CSRCS += arm_tcbinfo.c arm_cache.c arm_perf.c
ifeq ($(CONFIG_ARMV7M_SYSTICK),y)
CMN_CSRCS += arm_systick.c
endif
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_STM32H7_PROGMEM),y)
CMN_CSRCS += stm32_flash.c
endif
ifneq ($(filter y,$(CONFIG_ARM_MPU) $(CONFIG_ARM_MPU_EARLY_RESET)),)
CMN_CSRCS += arm_mpu.c
CHIP_CSRCS += stm32_flash.c
endif
# Required STM32H7 files
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c
CHIP_CSRCS += stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c
CHIP_CSRCS += stm32_start.c stm32_rcc.c stm32_lowputc.c stm32_serial.c
CHIP_CSRCS += stm32_uid.c

24
arch/arm/src/stm32l4/Make.defs
View File

@ -25,30 +25,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c
CMN_CSRCS += arm_tcbinfo.c arm_vectors.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
# Required STM32L4 files
CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c

25
arch/arm/src/stm32l5/Make.defs
View File

@ -27,31 +27,6 @@ HEAD_ASRC =
include armv8-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_tcbinfo.c
# Configuration-dependent common files
ifeq ($(CONFIG_ARMV8M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c
endif
# Required STM32L5 files
CHIP_ASRCS =

28
arch/arm/src/stm32u5/Make.defs
View File

@ -27,34 +27,6 @@ HEAD_ASRC =
include armv8-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_hardfault.c
CMN_CSRCS += arm_initialstate.c arm_memfault.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_tcbinfo.c
CMN_CSRCS += arm_trigger_irq.c
# Configuration-dependent common files
ifeq ($(CONFIG_ARMV8M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c
CMN_CSRCS += arm_pthread_exit.c
endif
# Required STM32U5 files
CHIP_ASRCS =

23
arch/arm/src/tiva/Make.defs
View File

@ -20,30 +20,11 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_doirq.c arm_hardfault.c arm_initialstate.c
CMN_CSRCS += arm_memfault.c arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_svcall.c arm_trigger_irq.c arm_tcbinfo.c arm_vectors.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += tiva_idle.c
CHIP_CSRCS += tiva_idle.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
CHIP_CSRCS = tiva_allocateheap.c tiva_irq.c tiva_lowputc.c tiva_serial.c
CHIP_CSRCS += tiva_allocateheap.c tiva_irq.c tiva_lowputc.c tiva_serial.c
CHIP_CSRCS += tiva_ssi.c
ifeq ($(CONFIG_ARCH_CHIP_LM3S),y)

27
arch/arm/src/xmc4/Make.defs
View File

@ -20,33 +20,6 @@
include armv7-m/Make.defs
CMN_ASRCS += arm_exception.S
CMN_CSRCS += arm_vectors.c arm_doirq.c arm_initialstate.c
CMN_CSRCS += arm_hardfault.c arm_memfault.c arm_schedulesigaction.c
CMN_CSRCS += arm_sigdeliver.c arm_svcall.c arm_systemreset.c arm_tcbinfo.c
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += arm_mpu.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_CSRCS += arm_fpuconfig.c
CMN_CSRCS += arm_fpucmp.c
endif
ifeq ($(CONFIG_ARMV7M_ITMSYSLOG),y)
CMN_CSRCS += arm_itm_syslog.c
endif
# Required XMC4xxx files
CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clockutils.c