sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch: imx6: Fix style warnings in chip.h

Browse Source 
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
Masayuki Ishikawa 2020-10-19 13:04:54 +09:00 committed by Xiang Xiao
parent d8d19911ef
commit 56a081515c
1 changed files with 25 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

54
arch/arm/src/imx6/chip.h
View File

@ -72,8 +72,8 @@
#ifdef __ASSEMBLY__
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
.globl g_irqstack_top
.globl g_fiqstack_top
.globl g_irqstack_top
.globl g_fiqstack_top
#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */
#endif /* __ASSEMBLY__ */
@ -84,7 +84,7 @@
#ifdef __ASSEMBLY__
/***************************************************************************
/****************************************************************************
* Name: cpuindex
*
* Description:
@ -93,30 +93,30 @@
****************************************************************************/
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
.macro cpuindex, index
mrc p15, 0, \index, c0, c0, 5 /* Read the MPIDR */
and \index, \index, #3 /* Bits 0-1=CPU ID */
.endm
.macro cpuindex, index
mrc p15, 0, \index, c0, c0, 5 /* Read the MPIDR */
and \index, \index, #3 /* Bits 0-1=CPU ID */
.endm
#endif
/***************************************************************************
/****************************************************************************
* Name: setirqstack
*
* Description:
* Set the current stack pointer to the -"top" of the IRQ interrupt
* stack for the current CPU.
*
***************************************************************************/
****************************************************************************/
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
.macro setirqstack, tmp1, tmp2
mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */
and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */
ldr \tmp2, =g_irqstack_top /* tmp2=Array of IRQ stack pointers */
lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */
add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */
ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */
.endm
.macro setirqstack, tmp1, tmp2
mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */
and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */
ldr \tmp2, =g_irqstack_top /* tmp2=Array of IRQ stack pointers */
lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */
add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */
ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */
.endm
#endif
/****************************************************************************
@ -129,14 +129,14 @@
****************************************************************************/
#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7
.macro setfiqstack, tmp1, tmp2
mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */
and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */
ldr \tmp2, =g_fiqstack_top /* tmp2=Array of FIQ stack pointers */
lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */
add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */
ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */
.endm
.macro setfiqstack, tmp1, tmp2
mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */
and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */
ldr \tmp2, =g_fiqstack_top /* tmp2=Array of FIQ stack pointers */
lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */
add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */
ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */
.endm
#endif
#endif /* __ASSEMBLY__ */
@ -188,8 +188,4 @@ static inline uintptr_t arm_intstack_top(void)
#endif /* !__ASSEMBLY__ */
/****************************************************************************
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_IMX6_CHIP_H */