From 56a081515ce6dabf3c43624f3e84ee823efb035b Mon Sep 17 00:00:00 2001 From: Masayuki Ishikawa Date: Mon, 19 Oct 2020 13:04:54 +0900 Subject: [PATCH] arch: imx6: Fix style warnings in chip.h Signed-off-by: Masayuki Ishikawa --- arch/arm/src/imx6/chip.h | 54 +++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 29 deletions(-) diff --git a/arch/arm/src/imx6/chip.h b/arch/arm/src/imx6/chip.h index b22e877cdd..54a31a38fa 100644 --- a/arch/arm/src/imx6/chip.h +++ b/arch/arm/src/imx6/chip.h @@ -72,8 +72,8 @@ #ifdef __ASSEMBLY__ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .globl g_irqstack_top - .globl g_fiqstack_top + .globl g_irqstack_top + .globl g_fiqstack_top #endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 7 */ #endif /* __ASSEMBLY__ */ @@ -84,7 +84,7 @@ #ifdef __ASSEMBLY__ -/*************************************************************************** +/**************************************************************************** * Name: cpuindex * * Description: @@ -93,30 +93,30 @@ ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .macro cpuindex, index - mrc p15, 0, \index, c0, c0, 5 /* Read the MPIDR */ - and \index, \index, #3 /* Bits 0-1=CPU ID */ - .endm + .macro cpuindex, index + mrc p15, 0, \index, c0, c0, 5 /* Read the MPIDR */ + and \index, \index, #3 /* Bits 0-1=CPU ID */ + .endm #endif -/*************************************************************************** +/**************************************************************************** * Name: setirqstack * * Description: * Set the current stack pointer to the -"top" of the IRQ interrupt * stack for the current CPU. * - ***************************************************************************/ + ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .macro setirqstack, tmp1, tmp2 - mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */ - and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */ - ldr \tmp2, =g_irqstack_top /* tmp2=Array of IRQ stack pointers */ - lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */ - add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */ - ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */ - .endm + .macro setirqstack, tmp1, tmp2 + mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */ + and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */ + ldr \tmp2, =g_irqstack_top /* tmp2=Array of IRQ stack pointers */ + lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */ + add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */ + ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */ + .endm #endif /**************************************************************************** @@ -129,14 +129,14 @@ ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 - .macro setfiqstack, tmp1, tmp2 - mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */ - and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */ - ldr \tmp2, =g_fiqstack_top /* tmp2=Array of FIQ stack pointers */ - lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */ - add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */ - ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */ - .endm + .macro setfiqstack, tmp1, tmp2 + mrc p15, 0, \tmp1, c0, c0, 5 /* tmp1=MPIDR */ + and \tmp1, \tmp1, #3 /* Bits 0-1=CPU ID */ + ldr \tmp2, =g_fiqstack_top /* tmp2=Array of FIQ stack pointers */ + lsls \tmp1, \tmp1, #2 /* tmp1=Array byte offset */ + add \tmp2, \tmp2, \tmp1 /* tmp2=Offset address into array */ + ldr sp, [\tmp2, #0] /* sp=Address in stack allocation */ + .endm #endif #endif /* __ASSEMBLY__ */ @@ -188,8 +188,4 @@ static inline uintptr_t arm_intstack_top(void) #endif /* !__ASSEMBLY__ */ -/**************************************************************************** - * Public Functions - ****************************************************************************/ - #endif /* __ARCH_ARM_SRC_IMX6_CHIP_H */