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Fix all occurrences of "the the" in documentation and comments

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This commit is contained in:
Gregory Nutt 2013-08-27 09:40:19 -06:00
parent a55dda98b3
commit 56f9092a87
43 changed files with 89 additions and 89 deletions
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2
arch/arm/src/arm/up_head.S
View File

@ -275,7 +275,7 @@ __start:
* effect. First populate the L1 table for the locked and paged
* text regions.
*
* We could probably make the the pg_l1span and pg_l2map macros into
* We could probably make the pg_l1span and pg_l2map macros into
* call-able subroutines, but we would have to be carefully during
* this phase while we are operating in a physical address space.
*

2
arch/arm/src/armv7-a/arm_pghead.S
View File

@ -265,7 +265,7 @@ __start:
* effect. First populate the L1 table for the locked and paged
* text regions.
*
* We could probably make the the pg_l1span and pg_l2map macros into
* We could probably make the pg_l1span and pg_l2map macros into
* call-able subroutines, but we would have to be carefully during
* this phase while we are operating in a physical address space.
*

2
arch/arm/src/armv7-a/arm_vectoraddrexcptn.S
View File

@ -75,7 +75,7 @@
* Description:
* Shouldn't happen. This exception handler is in a separate file from
* other vector handlers because some processors (e.g., Cortex-A5) do not
* support the the Address Exception vector.
* support the Address Exception vector.
*
****************************************************************************/

2
arch/arm/src/armv7-a/cache.h
View File

@ -968,7 +968,7 @@ void cp15_clean_dcache(uintptr_t start, uintptr_t end);
*
* Description:
* Flush the data cache within the specified region by cleaning and
* invalidating the the D cache.
* invalidating the D cache.
*
* Input Parameters:
* start - virtual start address of region

2
arch/arm/src/armv7-a/cp15_flush_dcache.S
View File

@ -76,7 +76,7 @@
*
* Description:
* Flush the data cache within the specified region by cleaning and
* invalidating the the D cache.
* invalidating the D cache.
*
* Input Parameters:
* start - virtual start address of region

2
arch/arm/src/armv7-m/ram_vectors.h
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@ -77,7 +77,7 @@
/* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide
* ARM-specific implementations of irq_initialize(), irq_attach(), and
* irq_dispatch. In this case, it is also assumed that the ARM vector
* table resides in RAM, has the the name up_ram_vectors, and has been
* table resides in RAM, has the name up_ram_vectors, and has been
* properly positioned and aligned in memory by the linker script.
*/

2
arch/arm/src/armv7-m/up_ramvec_initialize.c
View File

@ -65,7 +65,7 @@
/* If CONFIG_ARCH_RAMVECTORS is defined, then the ARM logic must provide
* ARM-specific implementations of up_ramvec_initialize(), irq_attach(), and
* irq_dispatch. In this case, it is also assumed that the ARM vector
* table resides in RAM, has the the name up_ram_vectors, and has been
* table resides in RAM, has the name up_ram_vectors, and has been
* properly positioned and aligned in memory by the linker script.
*/

2
arch/arm/src/kinetis/kinetis_sdhc.c
View File

@ -742,7 +742,7 @@ static void kinetis_dataconfig(struct kinetis_dev_s *priv, bool bwrite,
* Name: kinetis_datadisable
*
* Description:
* Disable the the SDIO data path setup by kinetis_dataconfig() and
* Disable the SDIO data path setup by kinetis_dataconfig() and
* disable DMA.
*
****************************************************************************/

16
arch/arm/src/kinetis/kinetis_serial.c
View File

@ -900,8 +900,8 @@ static int up_interrupts(int irq, void *context)
if (count > 0)
#else
/* Check if the receive data register is full (RDRF). NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is full,
* rather, it means that the the number of bytes in the RX FIFO has
* FIFOS are enabled, this does not mean that the FIFO is full,
* rather, it means that the number of bytes in the RX FIFO has
* exceeded the watermark setting. There may actually be RX data
* available!
*
@ -929,8 +929,8 @@ static int up_interrupts(int irq, void *context)
# error "Missing logic"
#else
/* Check if the transmit data register is "empty." NOTE: If FIFOS
* are enabled, this does not mean that the the FIFO is empty, rather,
* it means that the the number of bytes in the TX FIFO is below the
* are enabled, this does not mean that the FIFO is empty, rather,
* it means that the number of bytes in the TX FIFO is below the
* watermark setting. There could actually be space for additional TX
* data.
*
@ -1090,8 +1090,8 @@ static bool up_rxavailable(struct uart_dev_s *dev)
return count > 0;
#else
/* Return true if the receive data register is full (RDRF). NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is full,
* rather, it means that the the number of bytes in the RX FIFO has
* FIFOS are enabled, this does not mean that the FIFO is full,
* rather, it means that the number of bytes in the RX FIFO has
* exceeded the watermark setting. There may actually be RX data
* available!
*/
@ -1175,8 +1175,8 @@ static bool up_txready(struct uart_dev_s *dev)
# error "Missing logic"
#else
/* Return true if the transmit data register is "empty." NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is empty,
* rather, it means that the the number of bytes in the TX FIFO is
* FIFOS are enabled, this does not mean that the FIFO is empty,
* rather, it means that the number of bytes in the TX FIFO is
* below the watermark setting. There may actually be space for
* additional TX data.
*/

2
arch/arm/src/kinetis/kinetis_vectors.S
View File

@ -626,7 +626,7 @@ kinetis_common:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/

16
arch/arm/src/kl/kl_serial.c
View File

@ -547,8 +547,8 @@ static int up_interrupts(int irq, void *context)
s1 = up_serialin(priv, KL_UART_S1_OFFSET);
/* Check if the receive data register is full (RDRF). NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is full,
* rather, it means that the the number of bytes in the RX FIFO has
* FIFOS are enabled, this does not mean that the FIFO is full,
* rather, it means that the number of bytes in the RX FIFO has
* exceeded the watermark setting. There may actually be RX data
* available!
*
@ -567,8 +567,8 @@ static int up_interrupts(int irq, void *context)
/* Handle outgoing, transmit bytes */
/* Check if the transmit data register is "empty." NOTE: If FIFOS
* are enabled, this does not mean that the the FIFO is empty, rather,
* it means that the the number of bytes in the TX FIFO is below the
* are enabled, this does not mean that the FIFO is empty, rather,
* it means that the number of bytes in the TX FIFO is below the
* watermark setting. There could actually be space for additional TX
* data.
*
@ -728,8 +728,8 @@ static bool up_rxavailable(struct uart_dev_s *dev)
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
/* Return true if the receive data register is full (RDRF). NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is full,
* rather, it means that the the number of bytes in the RX FIFO has
* FIFOS are enabled, this does not mean that the FIFO is full,
* rather, it means that the number of bytes in the RX FIFO has
* exceeded the watermark setting. There may actually be RX data
* available!
*/
@ -804,8 +804,8 @@ static bool up_txready(struct uart_dev_s *dev)
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
/* Return true if the transmit data register is "empty." NOTE: If
* FIFOS are enabled, this does not mean that the the FIFO is empty,
* rather, it means that the the number of bytes in the TX FIFO is
* FIFOS are enabled, this does not mean that the FIFO is empty,
* rather, it means that the number of bytes in the TX FIFO is
* below the watermark setting. There may actually be space for
* additional TX data.
*/

2
arch/arm/src/lm/lm_vectors.S
View File

@ -229,7 +229,7 @@ lm_irqcommon:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/

2
arch/arm/src/lpc17xx/lpc17_ethernet.c
View File

@ -2495,7 +2495,7 @@ static inline int lpc17_ethinitialize(int intf)
#endif
if (ret != 0)
{
/* We could not attach the ISR to the the interrupt */
/* We could not attach the ISR to the interrupt */
return -EAGAIN;
}

4
arch/arm/src/lpc17xx/lpc17_sdcard.c
View File

@ -636,7 +636,7 @@ static void lpc17_setpwrctrl(uint32_t pwrctrl)
*
* Description:
* Return the current value of the the PWRCTRL field of the SD card P
* register. This function can be used to see the the SD card is power ON
* register. This function can be used to see if the SD card is powered ON
* or OFF
*
* Input Parameters:
@ -908,7 +908,7 @@ static void lpc17_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
* Name: lpc17_datadisable
*
* Description:
* Disable the the SD card data path setup by lpc17_dataconfig() and
* Disable the SD card data path setup by lpc17_dataconfig() and
* disable DMA.
*
****************************************************************************/

2
arch/arm/src/lpc17xx/lpc17_vectors.S
View File

@ -238,7 +238,7 @@ lpc17_common:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/

4
arch/arm/src/lpc31xx/lpc31_cgudrvr.h
View File

@ -794,7 +794,7 @@ EXTERN uint32_t lpc31_clkfreq(enum lpc31_clockid_e clkid,
* Name: lpc31_enableexten
*
* Description:
* Enable external enabling for the the specified possible clocks.
* Enable external enabling for the specified possible clocks.
*
************************************************************************/
@ -804,7 +804,7 @@ EXTERN void lpc31_enableexten(enum lpc31_clockid_e clkid);
* Name: lpc31_disableexten
*
* Description:
* Disable external enabling for the the specified possible clocks.
* Disable external enabling for the specified possible clocks.
*
************************************************************************/

4
arch/arm/src/lpc31xx/lpc31_clkexten.c
View File

@ -69,7 +69,7 @@
* Name: lpc31_enableexten
*
* Description:
* Enable external enabling for the the specified possible clocks.
* Enable external enabling for the specified possible clocks.
*
****************************************************************************/
@ -112,7 +112,7 @@ void lpc31_enableexten(enum lpc31_clockid_e clkid)
* Name: lpc31_disableexten
*
* Description:
* Disable external enabling for the the specified possible clocks.
* Disable external enabling for the specified possible clocks.
*
****************************************************************************/

2
arch/arm/src/lpc31xx/lpc31_softreset.c
View File

@ -84,7 +84,7 @@ void lpc31_softreset(enum lpc31_resetid_e resetid)
for (i = 0;i < 1000; i++);
/* Then set the the soft reset bit */
/* Then set the soft reset bit */
putreg32(CGU_SOFTRESET, address);
}

4
arch/arm/src/lpc43xx/lpc43_rgu.c
View File

@ -76,7 +76,7 @@
* Reset as many of the LPC43 peripherals as possible. This is necessary
* because the LPC43 does not provide any way of performing a full system
* reset under debugger control. So, if CONFIG_DEBUG is set (indicating
* that a debugger is being used?), the the boot logic will call this
* that a debugger is being used?), the boot logic will call this
* function on all restarts.
*
* Assumptions:
@ -93,7 +93,7 @@ void lpc43_softreset(void)
/* Disable interrupts */
flags = irqsave();
/* Reset all of the peripherals that we can (safely) */
putreg32((RGU_CTRL0_LCD_RST | RGU_CTRL0_USB0_RST |

2
arch/arm/src/lpc43xx/lpc43_rgu.h
View File

@ -76,7 +76,7 @@ extern "C" {
* Reset as many of the LPC43 peripherals as possible. This is necessary
* because the LPC43 does not provide any way of performing a full system
* reset under debugger control. So, if CONFIG_DEBUG is set (indicating
* that a debugger is being used?), the the boot logic will call this
* that a debugger is being used?), the boot logic will call this
* function on all restarts.
*
****************************************************************************/

8
arch/arm/src/lpc43xx/lpc43_start.c
View File

@ -114,7 +114,7 @@ static inline void lpc43_setbootrom(void)
putreg32(LPC43_ROM_BASE, LPC43_CREG_M4MEMMAP);
/* Address zero now maps to the Boot ROM. Make sure the the VTOR will
/* Address zero now maps to the Boot ROM. Make sure that the VTOR will
* use the ROM vector table at that address.
*/
@ -197,7 +197,7 @@ static inline void lpc43_fpuconfig(void)
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval = getcontrol();
regval |= (1 << 2);
setcontrol(regval);
@ -227,7 +227,7 @@ static inline void lpc43_fpuconfig(void)
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval = getcontrol();
regval &= ~(1 << 2);
setcontrol(regval);
@ -273,7 +273,7 @@ void __start(void)
/* Reset as many of the LPC43 peripherals as possible. This is necessary
* because the LPC43 does not provide any way of performing a full system
* reset under debugger control. So, if CONFIG_DEBUG is set (indicating
* that a debugger is being used?), the the boot logic will call this
* that a debugger is being used?), the boot logic will call this
* function on all restarts.
*/

2
arch/arm/src/nuc1xx/nuc_gpio.c
View File

@ -101,7 +101,7 @@ int nuc_configgpio(gpio_cfgset_t cfgset)
DEBUGASSERT((unsigned)port <= NUC_GPIO_PORTE);
base = NUC_GPIO_CTRL_BASE(port);
/* Set the the GPIO PMD register */
/* Set the GPIO PMD register */
regaddr = base + NUC_GPIO_PMD_OFFSET;
regval = getreg32(regaddr);

2
arch/arm/src/nuc1xx/nuc_lowputc.c
View File

@ -86,7 +86,7 @@
#endif
/* Select either the external high speed crystal, the PLL output, or
* the internal high speed clock as the the UART clock source.
* the internal high speed clock as the UART clock source.
*/
#if defined(CONFIG_NUC_UARTCLK_XTALHI)

12
arch/arm/src/sam34/sam3u_dmac.c
View File

@ -298,7 +298,7 @@ static inline uint32_t sam_fifocfg(struct sam_dma_s *dmach)
* Name: sam_txcfg
*
* Description:
* Decode the the flags to get the correct CFG register bit settings for
* Decode the flags to get the correct CFG register bit settings for
* a transmit (memory to peripheral) transfer.
*
****************************************************************************/
@ -322,7 +322,7 @@ static inline uint32_t sam_txcfg(struct sam_dma_s *dmach)
* Name: sam_rxcfg
*
* Description:
* Decode the the flags to get the correct CFG register bit settings for
* Decode the flags to get the correct CFG register bit settings for
* a receive (peripheral to memory) transfer.
*
****************************************************************************/
@ -346,7 +346,7 @@ static inline uint32_t sam_rxcfg(struct sam_dma_s *dmach)
* Name: sam_txctrlabits
*
* Description:
* Decode the the flags to get the correct CTRLA register bit settings for
* Decode the flags to get the correct CTRLA register bit settings for
* a transmit (memory to peripheral) transfer. These are only the "fixed"
* CTRLA values and need to be updated with the actual transfer size before
* being written to CTRLA sam_txctrla).
@ -492,7 +492,7 @@ static inline uint32_t sam_txctrla(struct sam_dma_s *dmach,
* Name: sam_rxctrlabits
*
* Description:
* Decode the the flags to get the correct CTRLA register bit settings for
* Decode the flags to get the correct CTRLA register bit settings for
* a read (peripheral to memory) transfer. These are only the "fixed" CTRLA
* values and need to be updated with the actual transfer size before being
* written to CTRLA sam_rxctrla).
@ -637,7 +637,7 @@ static inline uint32_t sam_rxctrla(struct sam_dma_s *dmach,
* Name: sam_txctrlb
*
* Description:
* Decode the the flags to get the correct CTRLB register bit settings for
* Decode the flags to get the correct CTRLB register bit settings for
* a transmit (memory to peripheral) transfer.
*
****************************************************************************/
@ -716,7 +716,7 @@ static inline uint32_t sam_txctrlb(struct sam_dma_s *dmach)
* Name: sam_rxctrlb
*
* Description:
* Decode the the flags to get the correct CTRLB register bit settings for
* Decode the flags to get the correct CTRLB register bit settings for
* a receive (peripheral to memory) transfer.
*
****************************************************************************/

2
arch/arm/src/sam34/sam_vectors.S
View File

@ -244,7 +244,7 @@ sam_common:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/

2
arch/arm/src/sama5/chip/sama5d3x_memorymap.h
View File

@ -527,7 +527,7 @@
* in the file mmu.h
*
* We must declare the page table at the bottom or at the top of internal
* SRAM. We pick the the bottom of internal SRAM *unless* there are vectors
* SRAM. We pick the bottom of internal SRAM *unless* there are vectors
* in the way at that position.
*/

2
arch/arm/src/sama5/sam_boot.c
View File

@ -172,7 +172,7 @@ static const struct section_mapping_s section_mapping[] =
/* SAMA5 External SDRAM Memory. The SDRAM is not usable until it has been
* initialized. If we are running out of SDRAM now, we can assume that some
* second level boot loader has properly configured SRAM for us. In that
* case, we set the the MMU flags for the final, fully cache-able state.
* case, we set the MMU flags for the final, fully cache-able state.
*
* If we are running from ISRAM or NOR flash, then we will need to configure
* the SDRAM ourselves. In this case, we set the MMU flags to the strongly

16
arch/arm/src/sama5/sam_dmac.c
View File

@ -748,7 +748,7 @@ static uint32_t sam_sink_channel(struct sam_dmach_s *dmach, uint8_t pid,
* Name: sam_txcfg
*
* Description:
* Decode the the flags to get the correct CFG register bit settings for
* Decode the flags to get the correct CFG register bit settings for
* a transmit (memory to peripheral) transfer.
*
****************************************************************************/
@ -788,7 +788,7 @@ static inline uint32_t sam_txcfg(struct sam_dmach_s *dmach)
* Name: sam_rxcfg
*
* Description:
* Decode the the flags to get the correct CFG register bit settings for
* Decode the flags to get the correct CFG register bit settings for
* a receive (peripheral to memory) transfer.
*
****************************************************************************/
@ -828,7 +828,7 @@ static inline uint32_t sam_rxcfg(struct sam_dmach_s *dmach)
* Name: sam_txctrlabits
*
* Description:
* Decode the the flags to get the correct CTRLA register bit settings for
* Decode the flags to get the correct CTRLA register bit settings for
* a transmit (memory to peripheral) transfer. These are only the "fixed"
* CTRLA values and need to be updated with the actual transfer size before
* being written to CTRLA sam_txctrla).
@ -932,7 +932,7 @@ static uint32_t sam_ntxtransfers(struct sam_dmach_s *dmach, uint32_t dmasize)
{
unsigned int srcwidth;
/* Adjust the the source transfer size for the source chunk size (memory
/* Adjust the source transfer size for the source chunk size (memory
* chunk size). BTSIZE is "the number of transfers to be performed, that
* is, for writes it refers to the number of source width transfers
* to perform when DMAC is flow controller. For Reads, BTSIZE refers to
@ -992,7 +992,7 @@ static inline uint32_t sam_txctrla(struct sam_dmach_s *dmach,
* Name: sam_rxctrlabits
*
* Description:
* Decode the the flags to get the correct CTRLA register bit settings for
* Decode the flags to get the correct CTRLA register bit settings for
* a read (peripheral to memory) transfer. These are only the "fixed" CTRLA
* values and need to be updated with the actual transfer size before being
* written to CTRLA sam_rxctrla).
@ -1100,7 +1100,7 @@ static uint32_t sam_nrxtransfers(struct sam_dmach_s *dmach, uint32_t dmasize)
{
unsigned int srcwidth;
/* Adjust the the source transfer size for the source chunk size (peripheral
/* Adjust the source transfer size for the source chunk size (peripheral
* chunk size). BTSIZE is "the number of transfers to be performed, that
* is, for writes it refers to the number of source width transfers
* to perform when DMAC is flow controller. For Reads, BTSIZE refers to
@ -1160,7 +1160,7 @@ static inline uint32_t sam_rxctrla(struct sam_dmach_s *dmach,
* Name: sam_txctrlb
*
* Description:
* Decode the the flags to get the correct CTRLB register bit settings for
* Decode the flags to get the correct CTRLB register bit settings for
* a transmit (memory to peripheral) transfer.
*
****************************************************************************/
@ -1251,7 +1251,7 @@ static inline uint32_t sam_txctrlb(struct sam_dmach_s *dmach)
* Name: sam_rxctrlb
*
* Description:
* Decode the the flags to get the correct CTRLB register bit settings for
* Decode the flags to get the correct CTRLB register bit settings for
* a receive (peripheral to memory) transfer.
*
****************************************************************************/

8
arch/arm/src/sama5/sam_ehci.c
View File

@ -1389,7 +1389,7 @@ static void sam_qh_enqueue(struct sam_qh_s *qh)
{
uintptr_t physaddr;
/* Set the internal fqp field. When we transverse the the QH list later,
/* Set the internal fqp field. When we transverse the QH list later,
* we need to know the correct place to start because the overlay may no
* longer point to the first qTD entry.
*/
@ -1554,7 +1554,7 @@ static int sam_qtd_addbpl(struct sam_qtd_s *qtd, const void *buffer, size_t bufl
next = (physaddr + 4096) & ~4095;
/* How many bytes were included in the last buffer? Was the the whole
/* How many bytes were included in the last buffer? Was it the whole
* thing?
*/
@ -2059,7 +2059,7 @@ static int sam_qtd_ioccheck(struct sam_qtd_s *qtd, uint32_t **bp, void *arg)
**bp = qtd->hw.nqp;
/* Subtract the number of bytes left untransferred. The epinfo->xfrd
* field is initialized to the the total number of bytes to be transferred
* field is initialized to the total number of bytes to be transferred
* (all qTDs in the list). We subtract out the number of untransferred
* bytes on each transfer and the final result will be the number of bytes
* actually transferred.
@ -3825,7 +3825,7 @@ FAR struct usbhost_connection_s *sam_ehci_initialize(int controller)
regval16 = sam_swap16(HCCR->hciversion);
uvdbg("HCIVERSION %x.%02x\n", regval16 >> 8, regval16 & 0xff);
/* Verify the the correct number of ports is reported */
/* Verify that the correct number of ports is reported */
regval = sam_getreg(&HCCR->hcsparams);
nports = (regval & EHCI_HCSPARAMS_NPORTS_MASK) >> EHCI_HCSPARAMS_NPORTS_SHIFT;

2
arch/arm/src/stm32/stm32_can.c
View File

@ -1332,7 +1332,7 @@ static int can_bittiming(struct stm32_can_s *priv)
canllvdbg("TS1: %d TS2: %d BRP: %d\n", ts1, ts2, brp);
/* Configure bit timing. This also does the the following, less obvious
/* Configure bit timing. This also does the following, less obvious
* things. Unless loopback mode is enabled, it:
*
* - Disables silent mode.

8
arch/arm/src/stm32/stm32_eth.c
View File

@ -1219,7 +1219,7 @@ static int stm32_uiptxpoll(struct uip_driver_s *dev)
*
* Description:
* The function is called when a frame is received using the DMA receive
* interrupt. It scans the RX descriptors to the the received frame.
* interrupt. It scans the RX descriptors to the received frame.
*
* Parameters:
* priv - Reference to the driver state structure
@ -1347,7 +1347,7 @@ static void stm32_disableint(FAR struct stm32_ethmac_s *priv, uint32_t ierbit)
*
* Description:
* The function is called when a frame is received using the DMA receive
* interrupt. It scans the RX descriptors to the the received frame.
* interrupt. It scans the RX descriptors to the received frame.
*
* Parameters:
* priv - Reference to the driver state structure
@ -1506,7 +1506,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
dev->d_len = ((rxdesc->rdes0 & ETH_RDES0_FL_MASK) >> ETH_RDES0_FL_SHIFT) - 4;
/* Get a buffer from the free list. We don't even check if
* this is successful because we already assure the the free
* this is successful because we already assure the free
* list is not empty above.
*/
@ -2536,7 +2536,7 @@ static inline int stm32_dm9161(FAR struct stm32_ethmac_s *priv)
return ret;
}
/* Bit 8 of the DSCR register is zero, the the DM9161 has not selected RMII.
/* Bit 8 of the DSCR register is zero, then the DM9161 has not selected RMII.
* If RMII is not selected, then reset the MCU to recover.
*/

2
arch/arm/src/stm32/stm32_iwdg.c
View File

@ -673,7 +673,7 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
/* Make sure that the LSI ocsillator is enabled. NOTE: The LSI oscillator
* is enabled here but is not disabled by this file (because this file does
* not know the the global usage of the oscillator. Any clock management
* not know the global usage of the oscillator. Any clock management
* logic (say, as part of a power management scheme) needs handle other
* LSI controls outside of this file.
*/

6
arch/arm/src/stm32/stm32_otgfshost.c
View File

@ -996,7 +996,7 @@ static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv,
static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv,
FAR struct stm32_chan_s *chan)
{
/* Is the the transfer complete? Is there a thread waiting for this transfer
/* Is the transfer complete? Is there a thread waiting for this transfer
* to complete?
*/
@ -1774,7 +1774,7 @@ static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv,
stm32_chan_halt(priv, chidx, CHREASON_XFRC);
/* Clear any pending NAK condition. The 'indata1' data toggle
* should have been appropriately updated by the the RxFIFO
* should have been appropriately updated by the RxFIFO
* logic as each packet was received.
*/
@ -2961,7 +2961,7 @@ static inline void stm32_hostinit_enable(void)
* Enable Tx FIFO empty interrupts. This is necessary when the entire
* transfer will not fit into Tx FIFO. The transfer will then be completed
* when the Tx FIFO is empty. NOTE: The Tx FIFO interrupt is disabled
* the the fifo empty interrupt handler when the transfer is complete.
* the fifo empty interrupt handler when the transfer is complete.
*
* Input Parameters:
* priv - Driver state structure reference

2
arch/arm/src/stm32/stm32_rcc.h
View File

@ -76,7 +76,7 @@ extern "C"
* Public Data
************************************************************************************/
/* This symbol references the Cortex-M3 vector table (as positioned by the the linker
/* This symbol references the Cortex-M3 vector table (as positioned by the linker
* script, ld.script or ld.script.dfu. The standard location for the vector table is
* at the beginning of FLASH at address 0x0800:0000. If we are using the STMicro DFU
* bootloader, then the vector table will be offset to a different location in FLASH

6
arch/arm/src/stm32/stm32_sdio.c
View File

@ -203,7 +203,7 @@
# error "Unknown STM32 DMA"
#endif
/* SDIO DMA Channel/Stream selection. For the the case of the STM32 F4, there
/* SDIO DMA Channel/Stream selection. For the case of the STM32 F4, there
* are multiple DMA stream options that must be dis-ambiguated in the board.h
* file.
*/
@ -682,7 +682,7 @@ static void stm32_setpwrctrl(uint32_t pwrctrl)
*
* Description:
* Return the current value of the the PWRCTRL field of the SDIO POWER
* register. This function can be used to see the the SDIO is power ON
* register. This function can be used to see if the SDIO is powered ON
* or OFF
*
* Input Parameters:
@ -952,7 +952,7 @@ static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl)
* Name: stm32_datadisable
*
* Description:
* Disable the the SDIO data path setup by stm32_dataconfig() and
* Disable the SDIO data path setup by stm32_dataconfig() and
* disable DMA.
*
****************************************************************************/

2
arch/arm/src/stm32/stm32_vectors.S
View File

@ -251,7 +251,7 @@ stm32_common:
sub r1, #(4*SW_FPU_REGS)
#endif
/* Save the the remaining registers on the stack after the registers pushed
/* Save the remaining registers on the stack after the registers pushed
* by the exception handling logic. r2=SP and r3=primask or basepri, r4-r11,
* r14=register values.
*/

2
arch/arm/src/stm32/stm32_wwdg.c
View File

@ -623,7 +623,7 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
* lower - A pointer the publicly visible representation of the "lower-half"
* driver state structure.
* newhandler - The new watchdog expiration function pointer. If this
* function pointer is NULL, then the the reset-on-expiration
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
*
* Returned Values:

2
arch/arm/src/stm32/stm32f20xxx_dma.c
View File

@ -521,7 +521,7 @@ void weak_function up_dmainitialize(void)
*
* Input parameter:
* dmamap - Identifies the stream/channel resource. For the STM32 F2, this
* is a bit-encoded value as provided by the the DMAMAP_* definitions
* is a bit-encoded value as provided by the DMAMAP_* definitions
* in chip/stm32f20xxx_dma.h
*
* Returned Value:

2
arch/arm/src/stm32/stm32f40xxx_dma.c
View File

@ -520,7 +520,7 @@ void weak_function up_dmainitialize(void)
*
* Input parameter:
* dmamap - Identifies the stream/channel resource. For the STM32 F4, this
* is a bit-encoded value as provided by the the DMAMAP_* definitions
* is a bit-encoded value as provided by the DMAMAP_* definitions
* in chip/stm32f40xxx_dma.h
*
* Returned Value:

2
arch/avr/src/avr/excptmacros.h
View File

@ -524,7 +524,7 @@
ld r25, x+
ld r24, x+
/* Finally, recover X [r26-r27] from the the new stack. The PC remains on the new
/* Finally, recover X [r26-r27] from the new stack. The PC remains on the new
* stack so that the user of this macro can return with ret (not reti, ret will
* preserve the restored interrupt state).
*/

4
arch/hc/src/m9s12/m9s12_ethernet.c
View File

@ -504,7 +504,7 @@ static int emac_ifdown(struct uip_driver_s *dev)
wd_cancel(priv->d_txpoll);
wd_cancel(priv->d_txtimeout);
/* Put the the EMAC is its reset, non-operational state. This should be
/* Put the EMAC is its reset, non-operational state. This should be
* a known configuration that will guarantee the emac_ifup() always
* successfully brings the interface back up.
*/
@ -655,7 +655,7 @@ int emac_initialize(int intf)
if (irq_attach(CONFIG_HCS12_IRQ, emac_interrupt))
{
/* We could not attach the ISR to the the interrupt */
/* We could not attach the ISR to the interrupt */
return -EAGAIN;
}

2
arch/mips/src/pic32mx/pic32mx-ethernet.c
View File

@ -3136,7 +3136,7 @@ static inline int pic32mx_ethinitialize(int intf)
#endif
if (ret != 0)
{
/* We could not attach the ISR to the the interrupt */
/* We could not attach the ISR to the interrupt */
return -EAGAIN;
}

6
arch/sim/src/up_touchscreen.c
View File

@ -153,7 +153,7 @@ static int up_poll(FAR struct file *filep, struct pollfd *fds, bool setup);
* Private Data
****************************************************************************/
/* This the the vtable that supports the character driver interface */
/* This the vtable that supports the character driver interface */
static const struct file_operations up_fops =
{
@ -168,7 +168,7 @@ static const struct file_operations up_fops =
#endif
};
/* Only one simulated touchscreen is supported o the the driver state
/* Only one simulated touchscreen is supported so the driver state
* structure may as well be pre-allocated.
*/
@ -324,7 +324,7 @@ static int up_waitsample(FAR struct up_dev_s *priv,
}
}
/* Re-acquire the the semaphore that manages mutually exclusive access to
/* Re-acquire the semaphore that manages mutually exclusive access to
* the device structure. We may have to wait here. But we have our sample.
* Interrupts and pre-emption will be re-enabled while we wait.
*/