* SAMV7: SPI: SPI-Freq. 40MHz; VARSELECT; hw-features
This change adds the following improvements:
- Increase the allowed SPI-Frequency from 20 to 40 MHz.
- Correct and rename the "VARSELECT" option This option was included in the code as "CONFIG_SPI_VARSELECT" but nowhere defined in a Kconfig file. The patch renames it to "CONFIG_SAMV7_SPI_VARSELECT" and corrects the implementation according the datasheet of Atmel. In short, this option switches the processor from "fixed peripheral selection" (single device) to "variable peripheral selection" (multiple devices on the bus).
- Add a new Function to the interface to control the timing and delays of the chip according the ChipSelect lines. This function can control the delay between the assertion of the ChipSelect and the first bit, between the last bit and the de-assertion of the ChipSelect and between two ChipSelects. This is needed to tune the transfer according the specification of the connected devices.
- Add three "hw-features" for the SAMV7, which controls the behavior of the ChipSelect:
1. force CS inactive after transfer: this forces a (short) de-assertion of the CS after a transfer, even if more data is
available in time
2. force CS active after transfer: this forces the CS to stay active after a transfer, even if the chip runs out of data. Btw.: this is a prerequisit to make the LASTXFER bit working at all.
- escape LASTXFER: this suppresses the LASTXFER bit at the end of the next transfer. The "escape"-Flag is reset automatically.
This commit is contained in:
Frank Benkert
Gregory Nutt
parent
5cc9a13f95
commit
573b1d415c
@ -835,6 +835,23 @@ config SAMV7_SPI_CS_DECODING
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---help---
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Use Peripheral Chip Select Decoding on SPI Master
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config SAMV7_SPI_VARSELECT
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bool "SPI Variable Peripheral Select Mode"
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default n
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---help---
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When enabled, the spi device is working in the "Variable Peripheral
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Select Mode" (VARMODE) instead of the "Fixed Peripheral Select Mode"
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(FIXEDMODE).
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In FIXEDMODE the ChipSelect is set (once) with a call to spi_select and
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stays the same value all the time. In addition an eventually signaled
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LASTXFER has to be written to the global control register (SPI_CR).
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Within the VARMODE, the ChipSelect can be changed with each datablock
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transferred via spi_exchange because it is encoded by the driver
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within the data.
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The same behavior applies for the LASTXFER bit.
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config SAMV7_SPI_DMA
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bool "SPI DMA"
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default n
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/samv7/sam_spi.c
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*
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* Copyright (C) 2015=2016 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Diego Sanchez <dsanchez@nx-engineering.com>
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*
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@ -194,6 +194,7 @@ struct sam_spidev_s
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sem_t spisem; /* Assures mutually exclusive access to SPI */
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select_t select; /* SPI select call-out */
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bool initialized; /* TRUE: Controller has been initialized */
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bool escape_lastxfer; /* Dont set LASTXFER-Bit in the next transfer */
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#ifdef CONFIG_SAMV7_SPI_DMA
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uint8_t pid; /* SPI peripheral ID */
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#endif
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@ -266,6 +267,12 @@ static int spi_lock(struct spi_dev_s *dev, bool lock);
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static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
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bool selected);
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static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency);
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#ifdef CONFIG_SPI_CS_DELAY_CONTROL
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static int spi_setdelay(struct spi_dev_s *dev, uint32_t a, uint32_t b, uint32_t c);
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#endif
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#ifdef CONFIG_SPI_HWFEATURES
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static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features);
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#endif
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static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode);
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static void spi_setbits(struct spi_dev_s *dev, int nbits);
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static uint16_t spi_send(struct spi_dev_s *dev, uint16_t ch);
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@ -313,10 +320,13 @@ static const struct spi_ops_s g_spi0ops =
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.lock = spi_lock,
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.select = spi_select,
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.setfrequency = spi_setfrequency,
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#ifdef CONFIG_SPI_CS_DELAY_CONTROL
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.setdelay = spi_setdelay,
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#endif
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.setmode = spi_setmode,
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.setbits = spi_setbits,
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#ifdef CONFIG_SPI_HWFEATURES
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.hwfeatures = 0, /* Not supported */
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.hwfeatures = spi_hwfeatures,
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#endif
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.status = sam_spi0status,
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#ifdef CONFIG_SPI_CMDDATA
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@ -352,6 +362,9 @@ static const struct spi_ops_s g_spi1ops =
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.lock = spi_lock,
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.select = spi_select,
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.setfrequency = spi_setfrequency,
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#ifdef CONFIG_SPI_CS_DELAY_CONTROL
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.setdelay = spi_setdelay,
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#endif
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.setmode = spi_setmode,
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.setbits = spi_setbits,
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.status = sam_spi1status,
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@ -951,7 +964,18 @@ static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid,
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regval = spi_getreg(spi, SAM_SPI_MR_OFFSET);
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regval &= ~SPI_MR_PCS_MASK;
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/* SPI_VARSELECT means, that the ChipSelect for each device is set within
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* the transferred data (SAM_SPI_TDR) instead inside the mode register
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* (SAM_SPI_MR).
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* In addition, the LASTXFER flag is also set within the transferred data
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* (SAM_SPI_TDR) instead inside the control register (SAM_SPI_CR).
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* (see spi_exchange)
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*/
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#ifndef CONFIG_SAMV7_SPI_VARSELECT
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regval |= (spi_cs2pcs(spics) << SPI_MR_PCS_SHIFT);
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#endif
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spi_putreg(spi, regval, SAM_SPI_MR_OFFSET);
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}
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@ -1016,9 +1040,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
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scbr = SAM_SPI_CLOCK / frequency;
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if (scbr < 8)
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if (scbr < 2)
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{
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scbr = 8;
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scbr = 2;
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}
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else if (scbr > 254)
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{
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@ -1079,6 +1103,189 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency)
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return actual;
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}
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/****************************************************************************
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* Name: spi_setdelay
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*
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* Description:
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* Set the SPI Delays in nanoseconds. Optional.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* startdelay - The delay between CS active and first CLK
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* stopdelay - The delay between last CLK and CS inactive
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* csdelay - The delay between CS inactive and CS active again
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*
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* Returned Value:
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* Returns 0 if ok
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*
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****************************************************************************/
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#ifdef CONFIG_SPI_CS_DELAY_CONTROL
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static int spi_setdelay(struct spi_dev_s *dev, uint32_t startdelay,
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uint32_t stopdelay, uint32_t csdelay)
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{
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struct sam_spics_s *spics = (struct sam_spics_s *)dev;
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struct sam_spidev_s *spi = spi_device(spics);
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uint64_t dlybs;
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uint64_t dlybct;
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uint64_t dlybcs;
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uint32_t regval;
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unsigned int offset;
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spivdbg("cs=%d startdelay=%d\n", spics->cs, startdelay);
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spivdbg("cs=%d stopdelay=%d\n", spics->cs, stopdelay);
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spivdbg("cs=%d csdelay=%d\n", spics->cs, csdelay);
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offset = (unsigned int)g_csroffset[spics->cs];
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/* startdelay = DLYBS: Delay Before SPCK.
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* This field defines the delay from NPCS valid to the first valid SPCK
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* transition. When DLYBS equals zero, the NPCS valid to SPCK transition is
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* 1/2 the SPCK clock period.
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* Otherwise, the following equations determine the delay:
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*
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* Delay Before SPCK = DLYBS / SPI_CLK
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*
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* For a 2uS delay
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*
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* DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000
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*
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* TODO: Check for boundaries!
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*/
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dlybs = SAM_SPI_CLOCK;
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dlybs *= startdelay;
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dlybs /= 1000000000;
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regval = spi_getreg(spi, offset);
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regval &= ~SPI_CSR_DLYBS_MASK;
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regval |= (uint32_t) dlybs << SPI_CSR_DLYBS_SHIFT;
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/* stopdelay = DLYBCT: Delay Between Consecutive Transfers.
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* This field defines the delay between two consecutive transfers with the
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* same peripheral without removing the chip select. The delay is always
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* inserted after each transfer and before removing the chip select if
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* needed.
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*
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* Delay Between Consecutive Transfers = (32 x DLYBCT) / SPI_CLK
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*
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* For a 5uS delay:
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*
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* DLYBCT = SPI_CLK * 0.000005 / 32 = SPI_CLK / 200000 / 32
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*/
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dlybct = SAM_SPI_CLOCK;
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dlybct *= stopdelay;
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dlybct /= 1000000000;
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dlybct /= 32;
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regval = spi_getreg(spi, offset);
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regval &= ~SPI_CSR_DLYBCT_MASK;
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regval |= (uint32_t) dlybct << SPI_CSR_DLYBCT_SHIFT;
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spi_putreg(spi, regval, offset);
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/* csdelay = DLYBCS: Delay Between Chip Selects.
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* This field defines the delay between the inactivation and the activation
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* of NPCS. The DLYBCS time guarantees non-overlapping chip selects and
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* solves bus contentions in case of peripherals having long data float
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* times. If DLYBCS is lower than 6, six peripheral clock periods are
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* inserted by default.
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*
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* Delay Between Chip Selects = DLYBCS / SPI_CLK
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*
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* DLYBCS = SPI_CLK * Delay
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*/
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dlybcs = SAM_SPI_CLOCK;
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dlybcs *= csdelay;
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dlybcs /= 1000000000;
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regval = spi_getreg(spi, SAM_SPI_MR_OFFSET);
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regval &= ~SPI_MR_DLYBCS_MASK;
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regval |= dlybcs << SPI_MR_DLYBCS_SHIFT;
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spi_putreg(spi, regval, SAM_SPI_MR_OFFSET);
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return 0;
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}
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#endif
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/****************************************************************************
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* Name: spi_hwfeatures
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*
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* Description:
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* Use some super-special hardware Features. Optional.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* features - Bitmask of the activated features
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*
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* Returned Value:
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* Returns 0 if ok
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*
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****************************************************************************/
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#ifdef CONFIG_SPI_HWFEATURES
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static int spi_hwfeatures(struct spi_dev_s *dev, uint8_t features)
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{
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struct sam_spics_s *spics = (struct sam_spics_s *)dev;
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struct sam_spidev_s *spi = spi_device(spics);
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uint32_t regval;
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unsigned int offset;
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/* CS rises after every Transmission, also if we provide new data
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* immediately.
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*/
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if (features & HWFEAT_FORCE_CS_INACTIVE_AFTER_TRANSFER)
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{
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offset = (unsigned int)g_csroffset[spics->cs];
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regval = spi_getreg(spi, offset);
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regval |= SPI_CSR_CSNAAT; /* Chip Select Not Active After Transfer */
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regval &= ~SPI_CSR_CSAAT; /* Chip Select Active After Transfer */
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spi_putreg(spi, regval, offset);
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}
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else
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{
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offset = (unsigned int)g_csroffset[spics->cs];
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regval = spi_getreg(spi, offset);
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regval &= ~SPI_CSR_CSNAAT; /* Chip Select Not Active After Transfer */
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spi_putreg(spi, regval, offset);
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}
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/* CS does not rise automatically after a transmission, also if the spi runs
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* out of data (for a long time)
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*/
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if ((features & HWFEAT_FORCE_CS_ACTIVE_AFTER_TRANSFER) != 0)
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{
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offset = (unsigned int)g_csroffset[spics->cs];
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regval = spi_getreg(spi, offset);
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regval &= ~SPI_CSR_CSNAAT; /* Chip Select Not Active After Transfer */
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regval |= SPI_CSR_CSAAT; /* Chip Select Active After Transfer */
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spi_putreg(spi, regval, offset);
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}
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else
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{
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offset = (unsigned int)g_csroffset[spics->cs];
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regval = spi_getreg(spi, offset);
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regval &= ~SPI_CSR_CSAAT; /* Chip Select Not Active After Transfer */
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spi_putreg(spi, regval, offset);
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}
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/* Do not set the LASTXFER-Bit at the last word of the next exchange,
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* Flag is auto-resetting after the next LASTXFER condition.
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* (see spi_exchange)
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*/
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if ((features & HWFEAT_ESCAPE_LASTXFER) != 0)
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{
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spi->escape_lastxfer = true;
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}
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else
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{
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spi->escape_lastxfer = false;
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}
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return 0;
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}
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#endif
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/****************************************************************************
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* Name: spi_setmode
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*
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@ -1191,7 +1398,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits)
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spiinfo("csr[offset=%02x]=%08x\n", offset, regval);
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/* Save the selection so the subsequence re-configurations will be faster */
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/* Save the selection so the subsequence re-configurations will be
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* faster.
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*/
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spics->nbits = nbits;
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}
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@ -1347,16 +1556,37 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
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data = 0xffff;
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}
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/* SPI_VARSELECT means, that the ChipSelect for each device is set within
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* the transferred data (SAM_SPI_TDR) instead inside the mode register
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* (SAM_SPI_MR).
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* In addition, the LASTXFER flag is also set within the transferred data
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* (SAM_SPI_TDR) instead inside the control register (SAM_SPI_CR).
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*/
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#ifdef CONFIG_SAMV7_SPI_VARSELECT
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/* Set the PCS field in the value written to the TDR */
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data |= pcs;
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/* Do we need to set the LASTXFER bit in the TDR value too? */
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#ifdef CONFIG_SPI_VARSELECT
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if (nwords == 1)
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{
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data |= SPI_TDR_LASTXFER;
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if (spi->escape_lastxfer == false)
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{
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/* According the data sheet (SAME70 Rev. 2016-01) this LASTXFER
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* bit has no effect without also setting CSAAT.
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* (see HWFEAT_FORCE_CS_ACTIVE_AFTER_TRANSFER)
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*/
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data |= SPI_TDR_LASTXFER;
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}
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else
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{
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/* the escaping should only prevent ONE last-xfer */
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spi->escape_lastxfer = false;
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}
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}
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#endif
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@ -1370,6 +1600,32 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
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spi_putreg(spi, data, SAM_SPI_TDR_OFFSET);
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#ifndef CONFIG_SAMV7_SPI_VARSELECT
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/* To de-assert the chip select line at the end of the transfer, the
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* Last Transfer (LASTXFER) bit in SPI_CR must be set after writing the
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* last data to transmit into SPI_TDR.
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*/
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if (nwords == 1)
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{
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if (spi->escape_lastxfer == false)
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{
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/* According the datasheet (SAME70 Rev. 2016-01) this LASTXFER
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* bit has no effect without also setting CSAAT.
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* (see HWFEAT_FORCE_CS_ACTIVE_AFTER_TRANSFER)
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*/
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spi_putreg(spi, SPI_CR_LASTXFER, SAM_SPI_CR_OFFSET);
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}
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else
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{
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/* the escaping should only prevent ONE last-xfer */
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spi->escape_lastxfer = false;
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}
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}
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#endif
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/* Wait for the read data to be available in the RDR.
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* TODO: Data transfer rates would be improved using the RX FIFO
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* (and also DMA)
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@ -1870,15 +2126,22 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
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/* Configure the SPI mode register */
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regval = SPI_MR_MSTR | SPI_MR_MODFDIS;
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#if defined(CONFIG_SAMV7_SPI_CS_DECODING)
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/* Enable Peripheral Chip Select Decoding? */
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spi_putreg(spi, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCSDEC,
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SAM_SPI_MR_OFFSET);
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#else
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spi_putreg(spi, SPI_MR_MSTR | SPI_MR_MODFDIS, SAM_SPI_MR_OFFSET);
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regval |= SPI_MR_PCSDEC;
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#endif
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# ifdef CONFIG_SAMV7_SPI_VARSELECT
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/* Enable Variable Peripheral Selection? */
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regval |= SPI_MR_PS;
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#endif
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spi_putreg(spi, regval, SAM_SPI_MR_OFFSET);
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/* And enable the SPI */
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spi_putreg(spi, SPI_CR_SPIEN, SAM_SPI_CR_OFFSET);
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@ -1894,6 +2157,7 @@ FAR struct spi_dev_s *sam_spibus_initialize(int port)
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*/
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sem_init(&spi->spisem, 0, 1);
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spi->escape_lastxfer = false;
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spi->initialized = true;
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#ifdef CONFIG_SAMV7_SPI_DMA
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@ -71,6 +71,25 @@ config SPI_CRCGENERATION
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generation of SPI CRCs. Enables the HWFEAT_CRCGENERATION option
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as well as the hwfeartures() interface method.
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config SPI_CS_CONTROL
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bool "SPI CS Behavior Control"
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default n
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select SPI_HWFEATURES
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---help---
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Enables possibilities to define the behavior of CS.
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Also enables the hwfeatures() interface method.
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config SPI_CS_DELAY_CONTROL
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bool "SPI CS Delay Control"
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default n
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---help---
|
||||
Enables possibilities to define the SPI-ChipSelect-Delays like
|
||||
time between ChipSelect assertion and first Data-Bit, the time
|
||||
between the last Data-Bit and the de-assertion and the minimum
|
||||
delay between two ChipSelects.
|
||||
|
||||
This option enables the setdelay() interface method.
|
||||
|
||||
if SPI_BITBANG
|
||||
|
||||
config SPI_BITBANG_VARWIDTH
|
||||
|
||||
@ -127,6 +127,27 @@
|
||||
|
||||
#define SPI_SETFREQUENCY(d,f) ((d)->ops->setfrequency(d,f))
|
||||
|
||||
/****************************************************************************
|
||||
* Name: SPI_SETDELAY
|
||||
*
|
||||
* Description:
|
||||
* Set the SPI Delays in nanoseconds. Optional.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* startdelay - The delay between CS active and first CLK
|
||||
* stopdelay - The delay between last CLK and CS inactive
|
||||
* csdelay - The delay between CS inactive and CS active again
|
||||
*
|
||||
* Returned Value:
|
||||
* Returns the actual frequency selected
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CS_DELAY_CONTROL
|
||||
# define SPI_SETDELAY(d,a,b,c) ((d)->ops->setdelay(d,a,b,c))
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: SPI_SETMODE
|
||||
*
|
||||
@ -189,15 +210,35 @@
|
||||
# define SPI_HWFEATURES(d,f) \
|
||||
(((d)->ops->hwfeatures) ? (d)->ops->hwfeatures(d,f) : ((f) == 0 ? OK : -ENOSYS))
|
||||
|
||||
/* These are currently defined feature flags */
|
||||
/* These are currently defined feature flags:
|
||||
*
|
||||
* Bit 0: HWFEAT_CRCGENERATION
|
||||
* Hardware CRC generation
|
||||
* Bit 1: HWFEAT_FORCE_CS_INACTIVE_AFTER_TRANSFER
|
||||
* CS rises after every Transmission, also if we provide new data
|
||||
* immediately
|
||||
* Bit 2: HWFEAT_FORCE_CS_ACTIVE_AFTER_TRANSFER
|
||||
* CS does not rise automatically after a transmission, also if
|
||||
* the spi runs out of data (for a long time)
|
||||
* Bit 3: HWFEAT_ESCAPE_LASTXFER
|
||||
* Do not set the LASTXFER-Bit at the last word of the next
|
||||
* exchange, Flag is auto-resetting after the next LASTXFER
|
||||
* condition. (see spi_exchange)
|
||||
*/
|
||||
|
||||
# ifdef CONFIG_SPI_CRCGENERATION
|
||||
# HWFEAT_CRCGENERATION (1 << 0) /* Bit 0: Hardward CRC generation */
|
||||
# define HWFEAT_CRCGENERATION (1 << 0)
|
||||
# endif
|
||||
|
||||
# ifdef CONFIG_SPI_CS_CONTROL
|
||||
# define HWFEAT_FORCE_CS_INACTIVE_AFTER_TRANSFER (1 << 1)
|
||||
# define HWFEAT_FORCE_CS_ACTIVE_AFTER_TRANSFER (1 << 2)
|
||||
# define HWFEAT_ESCAPE_LASTXFER (1 << 3)
|
||||
# endif
|
||||
|
||||
#else
|
||||
/* Any attempt to select hardware features with CONFIG_SPI_HWFEATURES
|
||||
* deselected will cause an assertion.
|
||||
* deselected will return an -ENOSYS error.
|
||||
*/
|
||||
|
||||
# define SPI_HWFEATURES(d,f) (((f) == 0) ? OK : -ENOSYS)
|
||||
@ -431,6 +472,10 @@ struct spi_ops_s
|
||||
CODE void (*select)(FAR struct spi_dev_s *dev, enum spi_dev_e devid,
|
||||
bool selected);
|
||||
CODE uint32_t (*setfrequency)(FAR struct spi_dev_s *dev, uint32_t frequency);
|
||||
#ifdef CONFIG_SPI_CS_DELAY_CONTROL
|
||||
CODE int (*setdelay)(FAR struct spi_dev_s *dev, uint32_t a, uint32_t b,
|
||||
uint32_t c);
|
||||
#endif
|
||||
CODE void (*setmode)(FAR struct spi_dev_s *dev, enum spi_mode_e mode);
|
||||
CODE void (*setbits)(FAR struct spi_dev_s *dev, int nbits);
|
||||
#ifdef CONFIG_SPI_HWFEATURES
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user