arch/risc-v/qemu-rv: Support both rv32/rv64 core
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
Xiang Xiao
parent
74cce59ac6
commit
5792d851e5
@ -110,9 +110,8 @@ config ARCH_CHIP_RV32M1
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---help---
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NXP RV32M1 processor (RISC-V Core with PULP extensions).
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config ARCH_CHIP_QEMU_RV32
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bool "QEMU RV32"
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select ARCH_RV32
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config ARCH_CHIP_QEMU_RV
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bool "QEMU RV"
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select ARCH_RV_ISA_F
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select ARCH_RV_ISA_D
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---help---
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@ -176,7 +175,7 @@ config ARCH_CHIP
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default "c906" if ARCH_CHIP_C906
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default "mpfs" if ARCH_CHIP_MPFS
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default "rv32m1" if ARCH_CHIP_RV32M1
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default "qemu-rv32" if ARCH_CHIP_QEMU_RV32
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default "qemu-rv" if ARCH_CHIP_QEMU_RV
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config ARCH_RISCV_INTXCPT_EXTENSIONS
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bool "RISC-V Integer Context Extensions"
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@ -221,7 +220,7 @@ endif
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if ARCH_CHIP_RV32M1
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source "arch/risc-v/src/rv32m1/Kconfig"
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endif
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if ARCH_CHIP_QEMU_RV32
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source "arch/risc-v/src/qemu-rv32/Kconfig"
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if ARCH_CHIP_QEMU_RV
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source "arch/risc-v/src/qemu-rv/Kconfig"
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endif
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endif
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/include/qemu-rv32/chip.h
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* arch/risc-v/include/qemu-rv/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -18,7 +18,7 @@
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_QEMU_RV32_CHIP_H
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#define __ARCH_RISCV_INCLUDE_QEMU_RV32_CHIP_H
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#ifndef __ARCH_RISCV_INCLUDE_QEMU_RV_CHIP_H
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#define __ARCH_RISCV_INCLUDE_QEMU_RV_CHIP_H
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#endif /* __ARCH_RISCV_INCLUDE_QEMU_RV32_CHIP_H */
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#endif /* __ARCH_RISCV_INCLUDE_QEMU_RV_CHIP_H */
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/include/qemu-rv32/irq.h
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* arch/risc-v/include/qemu-rv/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -18,8 +18,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_QEMU_RV32_IRQ_H
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#define __ARCH_RISCV_INCLUDE_QEMU_RV32_IRQ_H
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#ifndef __ARCH_RISCV_INCLUDE_QEMU_RV_IRQ_H
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#define __ARCH_RISCV_INCLUDE_QEMU_RV_IRQ_H
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/****************************************************************************
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* Included Files
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@ -35,29 +35,29 @@
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/* IRQ 0-15 : (exception:interrupt=0) */
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#define QEMU_RV32_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
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#define QEMU_RV32_IRQ_IAFAULT (1) /* Instruction Address Fault */
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#define QEMU_RV32_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
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#define QEMU_RV32_IRQ_BPOINT (3) /* Break Point */
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#define QEMU_RV32_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
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#define QEMU_RV32_IRQ_LAFAULT (5) /* Load Access Fault */
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#define QEMU_RV32_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
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#define QEMU_RV32_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
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#define QEMU_RV32_IRQ_ECALLU (8) /* Environment Call from U-mode */
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#define QEMU_RV_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
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#define QEMU_RV_IRQ_IAFAULT (1) /* Instruction Address Fault */
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#define QEMU_RV_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
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#define QEMU_RV_IRQ_BPOINT (3) /* Break Point */
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#define QEMU_RV_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
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#define QEMU_RV_IRQ_LAFAULT (5) /* Load Access Fault */
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#define QEMU_RV_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
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#define QEMU_RV_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
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#define QEMU_RV_IRQ_ECALLU (8) /* Environment Call from U-mode */
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/* 9-10: Reserved */
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#define QEMU_RV32_IRQ_ECALLM (11) /* Environment Call from M-mode */
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#define QEMU_RV_IRQ_ECALLM (11) /* Environment Call from M-mode */
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/* 12-15: Reserved */
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/* IRQ 16- : (async event:interrupt=1) */
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#define QEMU_RV32_IRQ_ASYNC (16)
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#define QEMU_RV32_IRQ_MSOFT (QEMU_RV32_IRQ_ASYNC + 3) /* Machine Software Int */
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#define QEMU_RV32_IRQ_MTIMER (QEMU_RV32_IRQ_ASYNC + 7) /* Machine Timer Int */
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#define QEMU_RV32_IRQ_MEXT (QEMU_RV32_IRQ_ASYNC + 11) /* Machine External Int */
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#define QEMU_RV_IRQ_ASYNC (16)
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#define QEMU_RV_IRQ_MSOFT (QEMU_RV_IRQ_ASYNC + 3) /* Machine Software Int */
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#define QEMU_RV_IRQ_MTIMER (QEMU_RV_IRQ_ASYNC + 7) /* Machine Timer Int */
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#define QEMU_RV_IRQ_MEXT (QEMU_RV_IRQ_ASYNC + 11) /* Machine External Int */
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#define QEMU_RV32_IRQ_UART0 (QEMU_RV32_IRQ_MEXT + 10)
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#define QEMU_RV_IRQ_UART0 (QEMU_RV_IRQ_MEXT + 10)
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#define NR_IRQS (QEMU_RV32_IRQ_UART0 + 1)
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#define NR_IRQS (QEMU_RV_IRQ_UART0 + 1)
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#endif /* __ARCH_RISCV_INCLUDE_QEMU_RV32_IRQ_H */
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#endif /* __ARCH_RISCV_INCLUDE_QEMU_RV_IRQ_H */
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@ -3,20 +3,34 @@
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_CHIP_QEMU_RV32
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comment "QEMU RV32 Options"
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if ARCH_CHIP_QEMU_RV
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comment "QEMU RISC-V Options"
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config ARCH_CHIP_QEMU_RV32_ISA_M
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choice
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prompt "QEMU Chip Selection"
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default ARCH_CHIP_QEMU_RV32
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config ARCH_CHIP_QEMU_RV32
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bool "QEMU RV32"
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select ARCH_RV32
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config ARCH_CHIP_QEMU_RV64
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bool "QEMU RV64"
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select ARCH_RV64
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endchoice
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config ARCH_CHIP_QEMU_RV_ISA_M
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bool "Standard Extension for Integer Multiplication and Division"
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default y
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select ARCH_RV_ISA_M
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config ARCH_CHIP_QEMU_RV32_ISA_A
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config ARCH_CHIP_QEMU_RV_ISA_A
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bool "Standard Extension for Atomic Instructions"
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default y
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select ARCH_RV_ISA_A
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config ARCH_CHIP_QEMU_RV32_ISA_C
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config ARCH_CHIP_QEMU_RV_ISA_C
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bool "Standard Extension for Compressed Instructions"
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default y
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select ARCH_RV_ISA_C
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@ -20,7 +20,7 @@
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# Specify our HEAD assembly file. This will be linked as
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# the first object file, so it will appear at address 0
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HEAD_ASRC = qemu_rv32_head.S
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HEAD_ASRC = qemu_rv_head.S
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# Specify our general Assembly files
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CMN_ASRCS += riscv_vectors.S riscv_exception_common.S
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@ -59,5 +59,5 @@ CMN_ASRCS += riscv_testset.S
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endif
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# Specify our C code within this directory to be included
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CHIP_CSRCS = qemu_rv32_start.c qemu_rv32_irq_dispatch.c qemu_rv32_irq.c
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CHIP_CSRCS += qemu_rv32_idle.c qemu_rv32_timerisr.c
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CHIP_CSRCS = qemu_rv_start.c qemu_rv_irq_dispatch.c qemu_rv_irq.c
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CHIP_CSRCS += qemu_rv_idle.c qemu_rv_timerisr.c
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/qemu-rv32/chip.h
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* arch/risc-v/src/qemu-rv/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -18,8 +18,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_QEMU_RV32_CHIP_H
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#define __ARCH_RISCV_SRC_QEMU_RV32_CHIP_H
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#ifndef __ARCH_RISCV_SRC_QEMU_RV_CHIP_H
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#define __ARCH_RISCV_SRC_QEMU_RV_CHIP_H
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/****************************************************************************
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* Included Files
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@ -27,7 +27,7 @@
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/* Include the chip capabilities file */
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#include <arch/qemu-rv32/chip.h>
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#include <arch/qemu-rv/chip.h>
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#ifndef __ASSEMBLY__
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@ -40,6 +40,6 @@ extern void up_serialinit(void);
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#endif
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#include "qemu_rv32_memorymap.h"
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#include "qemu_rv_memorymap.h"
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#endif /* __ARCH_RISCV_SRC_QEMU_RV32_CHIP_H */
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#endif /* __ARCH_RISCV_SRC_QEMU_RV_CHIP_H */
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/qemu-rv32/hardware/qemu_rv32_clint.h
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* arch/risc-v/src/qemu-rv/hardware/qemu_rv_clint.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -18,14 +18,14 @@
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_QEMU_RV32_HARDWARE_QEMU_RV32_CLINT_H
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#define __ARCH_RISCV_SRC_QEMU_RV32_HARDWARE_QEMU_RV32_CLINT_H
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#ifndef __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_CLINT_H
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#define __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_CLINT_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define QEMU_RV32_CLINT_MTIMECMP (QEMU_RV32_CLINT_BASE + 0x4000)
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#define QEMU_RV32_CLINT_MTIME (QEMU_RV32_CLINT_BASE + 0xbff8)
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#define QEMU_RV_CLINT_MTIMECMP (QEMU_RV_CLINT_BASE + 0x4000)
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#define QEMU_RV_CLINT_MTIME (QEMU_RV_CLINT_BASE + 0xbff8)
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#endif /* __ARCH_RISCV_SRC_QEMU_RV32_HARDWARE_QEMU_RV32_CLINT_H */
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#endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_CLINT_H */
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/qemu-rv32/hardware/qemu_rv32_memorymap.h
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* arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -18,8 +18,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_QEMU_RV32_HARDWARE_QEMU_RV32_MEMORYMAP_H
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#define __ARCH_RISCV_SRC_QEMU_RV32_HARDWARE_QEMU_RV32_MEMORYMAP_H
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#ifndef __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H
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#define __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H
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/****************************************************************************
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* Pre-processor Definitions
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@ -27,7 +27,7 @@
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/* Register Base Address ****************************************************/
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#define QEMU_RV32_CLINT_BASE 0x02000000
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#define QEMU_RV32_PLIC_BASE 0x0c000000
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#define QEMU_RV_CLINT_BASE 0x02000000
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#define QEMU_RV_PLIC_BASE 0x0c000000
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#endif /* __ARCH_RISCV_SRC_QEMU_RV32_HARDWARE_QEMU_RV32_MEMORYMAP_H */
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#endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H */
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/qemu-rv32/hardware/qemu_rv32_plic.h
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* arch/risc-v/src/qemu-rv/hardware/qemu_rv_plic.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -18,18 +18,18 @@
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_PLIC_H
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#define __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_PLIC_H
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#ifndef __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_PLIC_H
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#define __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_PLIC_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define QEMU_RV32_PLIC_PRIORITY (QEMU_RV32_PLIC_BASE + 0x000000)
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#define QEMU_RV32_PLIC_PENDING1 (QEMU_RV32_PLIC_BASE + 0x001000)
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#define QEMU_RV32_PLIC_ENABLE1 (QEMU_RV32_PLIC_BASE + 0x002000)
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#define QEMU_RV32_PLIC_ENABLE2 (QEMU_RV32_PLIC_BASE + 0x002004)
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#define QEMU_RV32_PLIC_THRESHOLD (QEMU_RV32_PLIC_BASE + 0x200000)
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#define QEMU_RV32_PLIC_CLAIM (QEMU_RV32_PLIC_BASE + 0x200004)
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#define QEMU_RV_PLIC_PRIORITY (QEMU_RV_PLIC_BASE + 0x000000)
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#define QEMU_RV_PLIC_PENDING1 (QEMU_RV_PLIC_BASE + 0x001000)
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#define QEMU_RV_PLIC_ENABLE1 (QEMU_RV_PLIC_BASE + 0x002000)
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#define QEMU_RV_PLIC_ENABLE2 (QEMU_RV_PLIC_BASE + 0x002004)
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#define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x200000)
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#define QEMU_RV_PLIC_CLAIM (QEMU_RV_PLIC_BASE + 0x200004)
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#endif /* __ARCH_RISCV_SRC_FE310_HARDWARE_FE310_PLIC_H */
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#endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_PLIC_H */
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/qemu-rv32/qemu_rv32_head.S
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* arch/risc-v/src/qemu-rv/qemu_rv_head.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -40,17 +40,16 @@ __start:
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/* Set stack pointer to the idle thread stack */
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lui sp, %hi(QEMU_RV32_IDLESTACK_TOP)
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addi sp, sp, %lo(QEMU_RV32_IDLESTACK_TOP)
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la sp, QEMU_RV_IDLESTACK_TOP
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csrw mie, zero
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la t0, __trap_vec
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csrw mtvec, t0
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/* Jump to qemu_rv32_start */
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/* Jump to qemu_rv_start */
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jal x1, qemu_rv32_start
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jal x1, qemu_rv_start
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/* We shouldn't return from _start */
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/qemu-rv32/qemu_rv32_idle.c
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* arch/risc-v/src/qemu-rv/qemu_rv_idle.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/risc-v/src/qemu-rv32/qemu_rv32_irq.c
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* arch/risc-v/src/qemu-rv/qemu_rv_irq.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -37,8 +37,8 @@
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#include "riscv_internal.h"
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#include "riscv_arch.h"
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#include "hardware/qemu_rv32_memorymap.h"
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#include "hardware/qemu_rv32_plic.h"
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#include "hardware/qemu_rv_memorymap.h"
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#include "hardware/qemu_rv_plic.h"
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/****************************************************************************
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* Public Functions
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@ -56,8 +56,8 @@ void up_irqinitialize(void)
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/* Disable all global interrupts */
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putreg32(0x0, QEMU_RV32_PLIC_ENABLE1);
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putreg32(0x0, QEMU_RV32_PLIC_ENABLE2);
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putreg32(0x0, QEMU_RV_PLIC_ENABLE1);
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putreg32(0x0, QEMU_RV_PLIC_ENABLE2);
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/* Colorize the interrupt stack for debug purposes */
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@ -72,12 +72,12 @@ void up_irqinitialize(void)
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for (id = 1; id <= 52; id++)
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{
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putreg32(1, QEMU_RV32_PLIC_PRIORITY + 4 * id);
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putreg32(1, (uintptr_t)(QEMU_RV_PLIC_PRIORITY + 4 * id));
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}
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/* Set irq threshold to 0 (permits all global interrupts) */
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putreg32(0, QEMU_RV32_PLIC_THRESHOLD);
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putreg32(0, QEMU_RV_PLIC_THRESHOLD);
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/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
@ -85,7 +85,7 @@ void up_irqinitialize(void)
|
||||
|
||||
/* Attach the ecall interrupt handler */
|
||||
|
||||
irq_attach(QEMU_RV32_IRQ_ECALLM, riscv_swint, NULL);
|
||||
irq_attach(QEMU_RV_IRQ_ECALLM, riscv_swint, NULL);
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
||||
@ -108,7 +108,7 @@ void up_disable_irq(int irq)
|
||||
int extirq;
|
||||
uint32_t oldstat;
|
||||
|
||||
if (irq == QEMU_RV32_IRQ_MTIMER)
|
||||
if (irq == QEMU_RV_IRQ_MTIMER)
|
||||
{
|
||||
/* Read mstatus & clear machine timer interrupt enable in mie */
|
||||
|
||||
@ -116,15 +116,15 @@ void up_disable_irq(int irq)
|
||||
: "=r"(oldstat)
|
||||
: "r"(MIE_MTIE));
|
||||
}
|
||||
else if (irq > QEMU_RV32_IRQ_MEXT)
|
||||
else if (irq > QEMU_RV_IRQ_MEXT)
|
||||
{
|
||||
extirq = irq - QEMU_RV32_IRQ_MEXT;
|
||||
extirq = irq - QEMU_RV_IRQ_MEXT;
|
||||
|
||||
/* Clear enable bit for the irq */
|
||||
|
||||
if (0 <= extirq && extirq <= 63)
|
||||
{
|
||||
modifyreg32(QEMU_RV32_PLIC_ENABLE1 + (4 * (extirq / 32)),
|
||||
modifyreg32(QEMU_RV_PLIC_ENABLE1 + (4 * (extirq / 32)),
|
||||
1 << (extirq % 32), 0);
|
||||
}
|
||||
else
|
||||
@ -147,7 +147,7 @@ void up_enable_irq(int irq)
|
||||
int extirq;
|
||||
uint32_t oldstat;
|
||||
|
||||
if (irq == QEMU_RV32_IRQ_MTIMER)
|
||||
if (irq == QEMU_RV_IRQ_MTIMER)
|
||||
{
|
||||
/* Read mstatus & set machine timer interrupt enable in mie */
|
||||
|
||||
@ -155,15 +155,15 @@ void up_enable_irq(int irq)
|
||||
: "=r"(oldstat)
|
||||
: "r"(MIE_MTIE));
|
||||
}
|
||||
else if (irq > QEMU_RV32_IRQ_MEXT)
|
||||
else if (irq > QEMU_RV_IRQ_MEXT)
|
||||
{
|
||||
extirq = irq - QEMU_RV32_IRQ_MEXT;
|
||||
extirq = irq - QEMU_RV_IRQ_MEXT;
|
||||
|
||||
/* Set enable bit for the irq */
|
||||
|
||||
if (0 <= extirq && extirq <= 63)
|
||||
{
|
||||
modifyreg32(QEMU_RV32_PLIC_ENABLE1 + (4 * (extirq / 32)),
|
||||
modifyreg32(QEMU_RV_PLIC_ENABLE1 + (4 * (extirq / 32)),
|
||||
0, 1 << (extirq % 32));
|
||||
}
|
||||
else
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/qemu-rv32/qemu_rv32_irq_dispatch.c
|
||||
* arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
@ -35,8 +35,18 @@
|
||||
#include "riscv_arch.h"
|
||||
#include "riscv_internal.h"
|
||||
|
||||
#include "hardware/qemu_rv32_memorymap.h"
|
||||
#include "hardware/qemu_rv32_plic.h"
|
||||
#include "hardware/qemu_rv_memorymap.h"
|
||||
#include "hardware/qemu_rv_plic.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_RV32
|
||||
# define RV_IRQ_MASK 27
|
||||
#else
|
||||
# define RV_IRQ_MASK 59
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
@ -54,14 +64,14 @@ volatile uintptr_t *g_current_regs[1];
|
||||
|
||||
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
{
|
||||
uintptr_t irq = (vector >> 27) | (vector & 0xf);
|
||||
uintptr_t irq = (vector >> RV_IRQ_MASK) | (vector & 0xf);
|
||||
uintptr_t *mepc = regs;
|
||||
|
||||
/* Firstly, check if the irq is machine external interrupt */
|
||||
|
||||
if (QEMU_RV32_IRQ_MEXT == irq)
|
||||
if (QEMU_RV_IRQ_MEXT == irq)
|
||||
{
|
||||
uintptr_t val = getreg32(QEMU_RV32_PLIC_CLAIM);
|
||||
uintptr_t val = getreg32(QEMU_RV_PLIC_CLAIM);
|
||||
|
||||
/* Add the value to nuttx irq which is offset to the mext */
|
||||
|
||||
@ -70,7 +80,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
|
||||
/* NOTE: In case of ecall, we need to adjust mepc in the context */
|
||||
|
||||
if (QEMU_RV32_IRQ_ECALLM == irq)
|
||||
if (QEMU_RV_IRQ_ECALLM == irq)
|
||||
{
|
||||
*mepc += 4;
|
||||
}
|
||||
@ -91,11 +101,11 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
|
||||
irq_dispatch(irq, regs);
|
||||
|
||||
if (QEMU_RV32_IRQ_MEXT <= irq)
|
||||
if (QEMU_RV_IRQ_MEXT <= irq)
|
||||
{
|
||||
/* Then write PLIC_CLAIM to clear pending in PLIC */
|
||||
|
||||
putreg32(irq - QEMU_RV32_IRQ_MEXT, QEMU_RV32_PLIC_CLAIM);
|
||||
putreg32(irq - QEMU_RV_IRQ_MEXT, QEMU_RV_PLIC_CLAIM);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/qemu-rv32/qemu_rv32_memorymap.h
|
||||
* arch/risc-v/src/qemu-rv/qemu_rv_memorymap.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
@ -18,8 +18,8 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_RISCV_SRC_QEMU_RV32_QEMU_RV32_MEMORYMAP_H
|
||||
#define __ARCH_RISCV_SRC_QEMU_RV32_QEMU_RV32_MEMORYMAP_H
|
||||
#ifndef __ARCH_RISCV_SRC_QEMU_RV_QEMU_RV_MEMORYMAP_H
|
||||
#define __ARCH_RISCV_SRC_QEMU_RV_QEMU_RV_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
@ -32,12 +32,12 @@
|
||||
/* Idle thread stack starts from _ebss */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define QEMU_RV32_IDLESTACK_BASE (uint32_t)&_ebss
|
||||
#define QEMU_RV_IDLESTACK_BASE (uintptr_t)&_ebss
|
||||
#else
|
||||
#define QEMU_RV32_IDLESTACK_BASE _ebss
|
||||
#define QEMU_RV_IDLESTACK_BASE _ebss
|
||||
#endif
|
||||
|
||||
#define QEMU_RV32_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
|
||||
#define QEMU_RV32_IDLESTACK_TOP (QEMU_RV32_IDLESTACK_BASE + QEMU_RV32_IDLESTACK_SIZE)
|
||||
#define QEMU_RV_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
|
||||
#define QEMU_RV_IDLESTACK_TOP (QEMU_RV_IDLESTACK_BASE + QEMU_RV_IDLESTACK_SIZE)
|
||||
|
||||
#endif /* __ARCH_RISCV_SRC_QEMU_RV32_QEMU_RV32_MEMORYMAP_H */
|
||||
#endif /* __ARCH_RISCV_SRC_QEMU_RV_QEMU_RV_MEMORYMAP_H */
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/qemu-rv32/qemu_rv32_start.c
|
||||
* arch/risc-v/src/qemu-rv/qemu_rv_start.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
@ -50,17 +50,17 @@
|
||||
* for CPU0 and this value is used in up_initial_state()
|
||||
*/
|
||||
|
||||
uintptr_t g_idle_topstack = QEMU_RV32_IDLESTACK_TOP;
|
||||
uintptr_t g_idle_topstack = QEMU_RV_IDLESTACK_TOP;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: qemu_rv32_start
|
||||
* Name: qemu_rv_start
|
||||
****************************************************************************/
|
||||
|
||||
void qemu_rv32_start(void)
|
||||
void qemu_rv_start(void)
|
||||
{
|
||||
uint32_t *dest;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* arch/risc-v/src/qemu-rv32/qemu_rv32_timerisr.c
|
||||
* arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
@ -35,8 +35,8 @@
|
||||
|
||||
#include "riscv_arch.h"
|
||||
|
||||
#include "hardware/qemu_rv32_memorymap.h"
|
||||
#include "hardware/qemu_rv32_clint.h"
|
||||
#include "hardware/qemu_rv_memorymap.h"
|
||||
#include "hardware/qemu_rv_clint.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -58,10 +58,10 @@ static bool _b_tick_started = false;
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: qemu_rv32_reload_mtimecmp
|
||||
* Name: qemu_rv_reload_mtimecmp
|
||||
****************************************************************************/
|
||||
|
||||
static void qemu_rv32_reload_mtimecmp(void)
|
||||
static void qemu_rv_reload_mtimecmp(void)
|
||||
{
|
||||
irqstate_t flags = spin_lock_irqsave(NULL);
|
||||
|
||||
@ -71,26 +71,26 @@ static void qemu_rv32_reload_mtimecmp(void)
|
||||
if (!_b_tick_started)
|
||||
{
|
||||
_b_tick_started = true;
|
||||
current = getreg64(QEMU_RV32_CLINT_MTIME);
|
||||
current = getreg64(QEMU_RV_CLINT_MTIME);
|
||||
}
|
||||
else
|
||||
{
|
||||
current = getreg64(QEMU_RV32_CLINT_MTIMECMP);
|
||||
current = getreg64(QEMU_RV_CLINT_MTIMECMP);
|
||||
}
|
||||
|
||||
next = current + TICK_COUNT;
|
||||
putreg64(next, QEMU_RV32_CLINT_MTIMECMP);
|
||||
putreg64(next, QEMU_RV_CLINT_MTIMECMP);
|
||||
|
||||
spin_unlock_irqrestore(NULL, flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: qemu_rv32_timerisr
|
||||
* Name: qemu_rv_timerisr
|
||||
****************************************************************************/
|
||||
|
||||
static int qemu_rv32_timerisr(int irq, void *context, void *arg)
|
||||
static int qemu_rv_timerisr(int irq, void *context, void *arg)
|
||||
{
|
||||
qemu_rv32_reload_mtimecmp();
|
||||
qemu_rv_reload_mtimecmp();
|
||||
|
||||
/* Process timer interrupt */
|
||||
|
||||
@ -115,13 +115,13 @@ void up_timer_initialize(void)
|
||||
{
|
||||
/* Attach timer interrupt handler */
|
||||
|
||||
irq_attach(QEMU_RV32_IRQ_MTIMER, qemu_rv32_timerisr, NULL);
|
||||
irq_attach(QEMU_RV_IRQ_MTIMER, qemu_rv_timerisr, NULL);
|
||||
|
||||
/* Reload CLINT mtimecmp */
|
||||
|
||||
qemu_rv32_reload_mtimecmp();
|
||||
qemu_rv_reload_mtimecmp();
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(QEMU_RV32_IRQ_MTIMER);
|
||||
up_enable_irq(QEMU_RV_IRQ_MTIMER);
|
||||
}
|
||||
@ -1451,9 +1451,9 @@ config ARCH_BOARD_RV32M1_VEGA
|
||||
This is the board configuration for the port of NuttX to the
|
||||
RV32M1 VEGA board. This board features the RV32M1 RISC-V Core(s).
|
||||
|
||||
config ARCH_BOARD_QEMU_RV32_VIRT
|
||||
bool "QEMU RV32 Virt"
|
||||
depends on ARCH_CHIP_QEMU_RV32
|
||||
config ARCH_BOARD_QEMU_RV_VIRT
|
||||
bool "QEMU RV Virt"
|
||||
depends on ARCH_CHIP_QEMU_RV
|
||||
---help---
|
||||
This is the board configuration for the port of NuttX to the
|
||||
QEMU RV32 Virt board. This board features the QEMU RV32 CPU.
|
||||
@ -2506,7 +2506,7 @@ config ARCH_BOARD
|
||||
default "s32k144evb" if ARCH_BOARD_S32K144EVB
|
||||
default "ucans32k146" if ARCH_BOARD_UCANS32K146
|
||||
default "rv32m1-vega" if ARCH_BOARD_RV32M1_VEGA
|
||||
default "rv32-virt" if ARCH_BOARD_QEMU_RV32_VIRT
|
||||
default "rv-virt" if ARCH_BOARD_QEMU_RV_VIRT
|
||||
default "s32k146evb" if ARCH_BOARD_S32K146EVB
|
||||
default "s32k148evb" if ARCH_BOARD_S32K148EVB
|
||||
default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD
|
||||
@ -3254,8 +3254,8 @@ endif
|
||||
if ARCH_BOARD_RV32M1_VEGA
|
||||
source "boards/risc-v/rv32m1/rv32m1-vega/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_QEMU_RV32_VIRT
|
||||
source "boards/risc-v/qemu-rv32/rv32-virt/Kconfig"
|
||||
if ARCH_BOARD_QEMU_RV_VIRT
|
||||
source "boards/risc-v/qemu-rv/rv-virt/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_ESP32C3_DEVKIT
|
||||
source "boards/risc-v/esp32c3/esp32c3-devkit/Kconfig"
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
|
||||
$ git clone https://github.com/qemu/qemu
|
||||
$ cd qemu
|
||||
$ ./configure --target-list=riscv32-softmmu
|
||||
$ ./configure --target-list=riscv32-softmmu,riscv64-softmmu
|
||||
$ make
|
||||
$ sudo make install
|
||||
|
||||
@ -17,13 +17,17 @@
|
||||
$ git clone https://github.com/apache/incubator-nuttx-apps.git
|
||||
$ cd nuttx
|
||||
$ make distclean
|
||||
$ ./tools/configure.sh rv32-virt:nsh
|
||||
$ ./tools/configure.sh rv-virt:nsh
|
||||
$ make
|
||||
|
||||
4. Run the nuttx with qemu
|
||||
|
||||
$ qemu-system-riscv32 -M virt -cpu rv32 -bios none -kernel nuttx -nographic
|
||||
|
||||
or
|
||||
|
||||
$ qemu-system-riscv64 -M virt -cpu rv64 -bios none -kernel nuttx -nographic
|
||||
|
||||
5. TODO
|
||||
|
||||
Support FPU
|
||||
@ -18,7 +18,7 @@
|
||||
# CONFIG_NSH_DISABLE_PS is not set
|
||||
# CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set
|
||||
# CONFIG_NSH_DISABLE_UNAME is not set
|
||||
CONFIG_16550_ADDRWIDTH=32
|
||||
CONFIG_16550_ADDRWIDTH=0
|
||||
CONFIG_16550_UART0=y
|
||||
CONFIG_16550_UART0_BASE=0x10000000
|
||||
CONFIG_16550_UART0_CLOCK=3686400
|
||||
@ -26,10 +26,14 @@ CONFIG_16550_UART0_IRQ=37
|
||||
CONFIG_16550_UART0_SERIAL_CONSOLE=y
|
||||
CONFIG_16550_UART=y
|
||||
CONFIG_ARCH="risc-v"
|
||||
CONFIG_ARCH_BOARD="rv32-virt"
|
||||
CONFIG_ARCH_BOARD_QEMU_RV32_VIRT=y
|
||||
CONFIG_ARCH_CHIP="qemu-rv32"
|
||||
CONFIG_ARCH_BOARD="rv-virt"
|
||||
CONFIG_ARCH_BOARD_QEMU_RV_VIRT=y
|
||||
CONFIG_ARCH_CHIP="qemu-rv"
|
||||
CONFIG_ARCH_CHIP_QEMU_RV32=y
|
||||
CONFIG_ARCH_CHIP_QEMU_RV=y
|
||||
CONFIG_ARCH_CHIP_QEMU_RV_ISA_A=y
|
||||
CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y
|
||||
CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=2048
|
||||
CONFIG_ARCH_RISCV=y
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/qemu-rv32/rv32-virt/include/board.h
|
||||
* boards/risc-v/qemu-rv/rv-virt/include/board.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
@ -18,8 +18,8 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __BOARDS_RISCV_QEMU_RV32_RV32_VIRT_INCLUDE_BOARD_H
|
||||
#define __BOARDS_RISCV_QEMU_RV32_RV32_VIRT_INCLUDE_BOARD_H
|
||||
#ifndef __BOARDS_RISCV_QEMU_RV_RV_VIRT_INCLUDE_BOARD_H
|
||||
#define __BOARDS_RISCV_QEMU_RV_RV_VIRT_INCLUDE_BOARD_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
@ -65,14 +65,14 @@ extern "C"
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: qemu_rv32_boardinitialize
|
||||
* Name: qemu_rv_boardinitialize
|
||||
****************************************************************************/
|
||||
|
||||
void qemu_rv32_boardinitialize(void);
|
||||
void qemu_rv_boardinitialize(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __BOARDS_RISCV_QEMU_RV32_RV32_VIRT_INCLUDE_BOARD_H */
|
||||
#endif /* __BOARDS_RISCV_QEMU_RV_RV_VIRT_INCLUDE_BOARD_H */
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/qemu-rv32/rv32-virt/include/nsh_romfsimg.h
|
||||
* boards/risc-v/qemu-rv/rv-virt/include/nsh_romfsimg.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
@ -18,8 +18,8 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __BOARDS_RISCV_QEMU_RV32_RV32_VIRT_INCLUDE_NSH_ROMFSIMG_H
|
||||
#define __BOARDS_RISCV_QEMU_RV32_RV32_VIRT_INCLUDE_NSH_ROMFSIMG_H
|
||||
#ifndef __BOARDS_RISCV_QEMU_RV_RV_VIRT_INCLUDE_NSH_ROMFSIMG_H
|
||||
#define __BOARDS_RISCV_QEMU_RV_RV_VIRT_INCLUDE_NSH_ROMFSIMG_H
|
||||
extern const unsigned char romfs_img[];
|
||||
extern const unsigned int romfs_img_len;
|
||||
#endif
|
||||
@ -1,5 +1,5 @@
|
||||
############################################################################
|
||||
# boards/risc-v/qemu-rv32/rv32-virt/scripts/Make.defs
|
||||
# boards/risc-v/qemu-rv/rv-virt/scripts/Make.defs
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
@ -22,7 +22,7 @@ include $(TOPDIR)/.config
|
||||
include $(TOPDIR)/tools/Config.mk
|
||||
include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs
|
||||
|
||||
ifeq ($(CONFIG_ARCH_CHIP_QEMU_RV32),y)
|
||||
ifeq ($(CONFIG_ARCH_CHIP_QEMU_RV),y)
|
||||
LDSCRIPT = ld.script
|
||||
endif
|
||||
|
||||
@ -43,6 +43,7 @@ ifneq ($(CONFIG_DEBUG_NOOPT),y)
|
||||
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce
|
||||
endif
|
||||
|
||||
ARCHCPUFLAGS += -mcmodel=medany
|
||||
ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
|
||||
@ -60,4 +61,8 @@ NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
||||
ifeq ($(CONFIG_ARCH_RV32),y)
|
||||
LDFLAGS += --gc-sections -melf32lriscv
|
||||
else
|
||||
LDFLAGS += --gc-sections -melf64lriscv
|
||||
endif
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/qemu-rv32/rv32-virt/scripts/ld.script
|
||||
* boards/risc-v/qemu-rv/rv-virt/scripts/ld.script
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
@ -22,6 +22,6 @@ include $(TOPDIR)/Make.defs
|
||||
|
||||
RCSRCS = etc/init.d/rcS
|
||||
|
||||
CSRCS = qemu_rv32_appinit.c
|
||||
CSRCS = qemu_rv_appinit.c
|
||||
|
||||
include $(TOPDIR)/boards/Board.mk
|
||||
@ -1,5 +1,5 @@
|
||||
/****************************************************************************
|
||||
* boards/risc-v/qemu-rv32/rv32-virt/src/qemu_rv32_appinit.c
|
||||
* boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
Loading…
Reference in New Issue
Block a user