ARMv7-A: Exception register save/restore needs to work a little differently if we support user mode processes
This commit is contained in:
Gregory Nutt
parent
17e798993d
commit
57d78ddd93
2
TODO
2
TODO
@ -1439,7 +1439,7 @@ o ARM (arch/arm/)
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Priority: Low
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Title: CORTEX-M3 STACK OVERFLOW
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Description: There is bit bit logic inf up_fullcontextrestore() that executes on
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Description: There is bit bit logic in up_fullcontextrestore() that executes on
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return from interrupts (and other context switches) that looks like:
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ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the stored CPSR value */
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@ -57,6 +57,11 @@
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g_irqtmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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#ifdef CONFIG_BUILD_KERNEL
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g_svctmp:
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.word 0 /* User R13 */
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.word 0 /* User R14 */
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#endif
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g_undeftmp:
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.word 0 /* Saved lr */
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.word 0 /* Saved spsr */
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@ -123,15 +128,46 @@ arm_vectorirq:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Lirqtmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_IRQ, r4=spsr_IRQ */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
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cmp r1, #PSR_MODE_USR /* User mode? */
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bne .Lirqentersvc /* Branch if not user mode */
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/* ldmia with ^ will return the user mode registers (provided that r15
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* is not in the register list).
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*/
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stmia r0, {r13, r14}^ /* Get user mode R13/R14 into scratch area */
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ldmia r0, {r1, r2} /* Then reload into R1 and R2 */
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b .Lirqcontinue
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.Lirqentersvc:
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/* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
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* and r2.
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*/
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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.Lirqcontinue:
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ldr r0, .Lirqtmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
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#else
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/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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#endif
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/* Save r13(sp), r14(lr), r15(pc), and the CPSR */
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add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
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stmia r0, {r1-r4}
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@ -163,8 +199,30 @@ arm_vectorirq:
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/* Restore the CPSR, SVC mode registers and return */
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ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r1
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ldr r1, [r0, #(4*REG_CPSR)] /* Setup the return SPSR */
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msr spsr, r1 /* Establish the return mode SPSR */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r2, r1, #PSR_MODE_MASK /* Interrupted mode */
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cmp r2, #PSR_MODE_USR /* User mode? */
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bne .Lirqleavesvc /* Branch if not user mode */
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/* ldmia with ^ will return the user mode registers (provided that r15
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* is not in the register list).
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*/
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add r1, r0, #(4*REG_R13) /* R1=address of R13/R14 storage */
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ldmia r1, {r13, r14}^ /* Restore to user mode USER R13/R14 */
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ldmia r0, {r0-R12,r15}^ /* Return */
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.Lirqleavesvc:
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#endif
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/* Life is simple when everything is SVC mode */
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ldmia r0, {r0-r15}^ /* Return */
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.Lirqtmp:
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@ -197,14 +255,47 @@ arm_vectorsvc:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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/* Get the correct values of r13(sp), r14(lr), r15(pc)
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* and CPSR in r1-r4.
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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mov r3, r14 /* Save r14 as the PC as well */
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mrs r4, spsr /* Get the saved CPSR */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
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cmp r1, #PSR_MODE_USR /* User mode? */
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bne .Lsvcentersvc /* Branch if not user mode */
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/* ldmia with ^ will return the user mode registers (provided that r15
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* is not in the register list).
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*/
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ldr r0, .Lsvctmp /* Points to temp storage */
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stmia r0, {r13, r14}^ /* Get user mode R13/R14 into temp storage */
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ldmia r0, {r1, r2} /* Then reload into R1 and R2 */
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b .Lsvccontinue
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.Lsvcentersvc:
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/* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
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* and r2.
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*/
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14 /* R14 is altered on return from SVC */
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mov r3, r14 /* Save r14 as the PC as well */
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mrs r4, spsr /* Get the saved CPSR */
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mov r2, r14
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.Lsvccontinue:
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#else
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/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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#endif
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/* Save r13(sp), r14(lr), r15(pc), and the CPSR */
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add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
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stmia r0, {r1-r4}
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@ -229,8 +320,35 @@ arm_vectorsvc:
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/* Restore the CPSR, SVC mode registers and return */
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ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr, r1
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msr spsr, r1 /* Establish the return mode SPSR */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r2, r1, #PSR_MODE_MASK /* Interrupted mode */
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cmp r2, #PSR_MODE_USR /* User mode? */
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bne .Lleavesvcsvc /* Branch if not user mode */
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/* ldmia with ^ will return the user mode registers (provided that r15
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* is not in the register list).
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*/
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add r1, r0, #(4*REG_R13) /* R1=address of R13/R14 storage */
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ldmia r1, {r13, r14}^ /* Restore to user mode USER R13/R14 */
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ldmia r0, {r0-R12,r15}^ /* Return */
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.Lleavesvcsvc:
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#endif
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/* Life is simple when everything is SVC mode */
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ldmia r0, {r0-r15}^ /* Return */
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#ifdef CONFIG_BUILD_KERNEL
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.Lsvctmp:
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.word g_svctmp
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#endif
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.size arm_vectorsvc, . - arm_vectorsvc
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.align 5
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@ -274,15 +392,46 @@ arm_vectordata:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Ldaborttmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_ABT, r4=spsr_ABT */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
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cmp r1, #PSR_MODE_USR /* User mode? */
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bne .Ldabtentersvc /* Branch if not user mode */
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/* ldmia with ^ will return the user mode registers (provided that r15
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* is not in the register list).
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*/
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stmia r0, {r13, r14}^ /* Get user mode R13/R14 into scratch area */
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ldmia r0, {r1, r2} /* Then reload into R1 and R2 */
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b .Ldabtcontinue
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.Ldabtentersvc:
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/* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
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* and r2.
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*/
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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.Ldabtcontinue:
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ldr r0, .Ldaborttmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
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#else
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/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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#endif
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/* Save r13(sp), r14(lr), r15(pc), and the CPSR */
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add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
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stmia r0, {r1-r4}
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@ -309,7 +458,29 @@ arm_vectordata:
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/* Restore the CPSR, SVC mode registers and return */
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ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr_cxsf, r1
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msr spsr_cxsf, r1 /* Establish the return mode SPSR */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r2, r1, #PSR_MODE_MASK /* Interrupted mode */
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cmp r2, #PSR_MODE_USR /* User mode? */
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bne .Ldabtleavesvc /* Branch if not user mode */
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/* ldmia with ^ will return the user mode registers (provided that r15
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* is not in the register list).
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*/
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add r1, r0, #(4*REG_R13) /* R1=address of R13/R14 storage */
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ldmia r1, {r13, r14}^ /* Restore to user mode USER R13/R14 */
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ldmia r0, {r0-R12,r15}^ /* Return */
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.Ldabtleavesvc:
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#endif
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/* Life is simple when everything is SVC mode */
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ldmia r0, {r1-r15}^ /* Return */
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.Ldaborttmp:
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@ -357,15 +528,46 @@ arm_vectorprefetch:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Lpaborttmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_ABT, r4=spsr_ABT */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
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cmp r1, #PSR_MODE_USR /* User mode? */
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bne .Lpabtentersvc /* Branch if not user mode */
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/* ldmia with ^ will return the user mode registers (provided that r15
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* is not in the register list).
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*/
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stmia r0, {r13, r14}^ /* Get user mode R13/R14 into scratch area */
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ldmia r0, {r1, r2} /* Then reload into R1 and R2 */
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b .Lpabtcontinue
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.Lpabtentersvc:
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/* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
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* and r2.
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*/
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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.Lpabtcontinue:
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ldr r0, .Lpaborttmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
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#else
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/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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#endif
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/* Save r13(sp), r14(lr), r15(pc), and the CPSR */
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add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
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stmia r0, {r1-r4}
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@ -392,7 +594,29 @@ arm_vectorprefetch:
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/* Restore the CPSR, SVC mode registers and return */
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ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr_cxsf, r1
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msr spsr_cxsf, r1 /* Establish the return mode SPSR */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r2, r1, #PSR_MODE_MASK /* Interrupted mode */
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cmp r2, #PSR_MODE_USR /* User mode? */
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bne .Lpabtleavesvc /* Branch if not user mode */
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/* ldmia with ^ will return the user mode registers (provided that r15
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* is not in the register list).
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*/
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add r1, r0, #(4*REG_R13) /* R1=address of R13/R14 storage */
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ldmia r1, {r13, r14}^ /* Restore to user mode USER R13/R14 */
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ldmia r0, {r0-R12,r15}^ /* Return */
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.Lpabtleavesvc:
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#endif
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/* Life is simple when everything is SVC mode */
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ldmia r0, {r0-r15}^ /* Return */
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.Lpaborttmp:
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@ -437,15 +661,46 @@ arm_vectorundefinsn:
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sub sp, sp, #XCPTCONTEXT_SIZE
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stmia sp, {r0-r12} /* Save the SVC mode regs */
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/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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ldr r0, .Lundeftmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r3=lr_UND, r4=spsr_UND */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
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cmp r1, #PSR_MODE_USR /* User mode? */
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bne .Lundefentersvc /* Branch if not user mode */
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/* ldmia with ^ will return the user mode registers (provided that r15
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* is not in the register list).
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*/
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stmia r0, {r13, r14}^ /* Get user mode R13/R14 into scratch area */
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ldmia r0, {r1, r2} /* Then reload into R1 and R2 */
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b .Lundefcontinue
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.Lundefentersvc:
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/* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
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* and r2.
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*/
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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/* Get the values for r15(pc) and CPSR in r3 and r4 */
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.Lundefcontinue:
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ldr r0, .Lundeftmp /* Points to temp storage */
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ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
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#else
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/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
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add r1, sp, #XCPTCONTEXT_SIZE
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mov r2, r14
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#endif
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/* Save r13(sp), r14(lr), r15(pc), and the CPSR */
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add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
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stmia r0, {r1-r4}
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@ -470,7 +725,29 @@ arm_vectorundefinsn:
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/* Restore the CPSR, SVC mode registers and return */
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ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
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msr spsr_cxsf, r1
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msr spsr_cxsf, r1 /* Establish the return mode SPSR */
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#ifdef CONFIG_BUILD_KERNEL
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/* Did we enter from user mode? If so then we need get the values of
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* USER mode r13(sp) and r14(lr) in r1 and r2.
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*/
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and r2, r1, #PSR_MODE_MASK /* Interrupted mode */
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||||
cmp r2, #PSR_MODE_USR /* User mode? */
|
||||
bne .Lundefleavesvc /* Branch if not user mode */
|
||||
|
||||
/* ldmia with ^ will return the user mode registers (provided that r15
|
||||
* is not in the register list).
|
||||
*/
|
||||
|
||||
add r1, r0, #(4*REG_R13) /* R1=address of R13/R14 storage */
|
||||
ldmia r1, {r13, r14}^ /* Restore to user mode USER R13/R14 */
|
||||
ldmia r0, {r0-R12,r15}^ /* Return */
|
||||
|
||||
.Lundefleavesvc:
|
||||
#endif
|
||||
/* Life is simple when everything is SVC mode */
|
||||
|
||||
ldmia r0, {r0-r15}^ /* Return */
|
||||
|
||||
.Lundeftmp:
|
||||
@ -517,15 +794,46 @@ arm_vectorfiq:
|
||||
sub sp, sp, #XCPTCONTEXT_SIZE
|
||||
stmia sp, {r0-r12} /* Save the SVC mode regs */
|
||||
|
||||
/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
|
||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
||||
|
||||
ldr r0, .Lfiqtmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_SVC, r4=spsr_SVC */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
* USER mode r13(sp) and r14(lr) in r1 and r2.
|
||||
*/
|
||||
|
||||
and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
|
||||
cmp r1, #PSR_MODE_USR /* User mode? */
|
||||
bne .Lfiqentersvc /* Branch if not user mode */
|
||||
|
||||
/* ldmia with ^ will return the user mode registers (provided that r15
|
||||
* is not in the register list).
|
||||
*/
|
||||
|
||||
stmia r0, {r13, r14}^ /* Get user mode R13/R14 into scratch area */
|
||||
ldmia r0, {r1, r2} /* Then reload into R1 and R2 */
|
||||
b .Lfiqcontinue
|
||||
|
||||
.Lfiqentersvc:
|
||||
/* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
|
||||
* and r2.
|
||||
*/
|
||||
|
||||
add r1, sp, #XCPTCONTEXT_SIZE
|
||||
mov r2, r14
|
||||
|
||||
/* Get the values for r15(pc) and CPSR in r3 and r4 */
|
||||
.Lfiqcontinue:
|
||||
|
||||
ldr r0, .Lfiqtmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r1=lr_IRQ, r2=spsr_IRQ */
|
||||
#else
|
||||
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
|
||||
|
||||
add r1, sp, #XCPTCONTEXT_SIZE
|
||||
mov r2, r14
|
||||
#endif
|
||||
|
||||
/* Save r13(sp), r14(lr), r15(pc), and the CPSR */
|
||||
|
||||
add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
|
||||
stmia r0, {r1-r4}
|
||||
@ -558,7 +866,29 @@ arm_vectorfiq:
|
||||
/* Restore the CPSR, SVC mode registers and return */
|
||||
|
||||
ldr r1, [r0, #(4*REG_CPSR)] /* Setup the SVC mode SPSR */
|
||||
msr spsr, r1
|
||||
msr spsr, r1 /* Establish the return mode SPSR */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
* USER mode r13(sp) and r14(lr) in r1 and r2.
|
||||
*/
|
||||
|
||||
and r2, r1, #PSR_MODE_MASK /* Interrupted mode */
|
||||
cmp r2, #PSR_MODE_USR /* User mode? */
|
||||
bne .Lfiqleavesvc /* Branch if not user mode */
|
||||
|
||||
/* ldmia with ^ will return the user mode registers (provided that r15
|
||||
* is not in the register list).
|
||||
*/
|
||||
|
||||
add r1, r0, #(4*REG_R13) /* R1=address of R13/R14 storage */
|
||||
ldmia r1, {r13, r14}^ /* Restore to user mode USER R13/R14 */
|
||||
ldmia r0, {r0-R12,r15}^ /* Return */
|
||||
|
||||
.Lfiqleavesvc:
|
||||
#endif
|
||||
/* Life is simple when everything is SVC mode */
|
||||
|
||||
ldmia r0, {r0-r15}^ /* Return */
|
||||
|
||||
.Lfiqtmp:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user