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arch/arc/src: Remove all driver-specific logic to set the interrupt priority. There is no good reason to change the interrupt priority unless you just want to debug a difficult problem. OR is you want to use high priority interrupts. In that case the specific interrupt priorities will need to be set by board-specific logic.

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This commit is contained in:
Gregory Nutt 2018-12-06 13:33:58 -06:00
parent ca4ef377fb
commit 5832c150d7
37 changed files with 0 additions and 366 deletions
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9
arch/arm/src/efm32/efm32_usb.h
View File

@ -48,15 +48,6 @@
#if defined(CONFIG_EFM32_OTGFS)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#ifndef CONFIG_OTGFS_PRI
# define CONFIG_OTGFS_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Types
************************************************************************************/

6
arch/arm/src/efm32/efm32_usbdev.c
View File

@ -5507,12 +5507,6 @@ void up_usbinitialize(void)
/* Enable USB controller interrupts at the NVIC */
up_enable_irq(EFM32_IRQ_USB);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(EFM32_IRQ_USB, CONFIG_OTGFS_PRI);
#endif
return;
errout:

6
arch/arm/src/imxrt/imxrt_config.h
View File

@ -215,12 +215,6 @@
#define IMXRT_ENET_HAS_DBSWAP 1
/* EMAC Default Interrupt Priorities */
#ifndef CONFIG_IMXRT_ENET_PRIO
# define CONFIG_IMXRT_ENET_PRIO NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Functions
************************************************************************************/

6
arch/arm/src/imxrt/imxrt_enet.c
View File

@ -2478,12 +2478,6 @@ int imxrt_netinitialize(int intf)
putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXEN_OFFSET);
putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXERR_OFFSET);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set interrupt priority levels */
up_prioritize_irq(IMXRT_IRQ_ENET, CONFIG_IMXRT_ENET_PRIO);
#endif
/* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */
#if 0

7
arch/arm/src/lpc17xx/Kconfig
View File

@ -690,13 +690,6 @@ config LPC17_ETH_NRXDESC
---help---
Configured number of Rx descriptors. Default: 13
config LPC17_ETH_PRIORITY
int "Ethernet interrupt priority"
default 128
depends on ARCH_IRQPRIO && EXPERIMENTAL
---help---
Ethernet interrupt priority. The default is the default priority (128).
config LPC17_NET_WOL
bool "Wake-up on LAN"
default n

23
arch/arm/src/lpc17xx/lpc17_ethernet.c
View File

@ -126,14 +126,6 @@
# define CONFIG_LPC17_MULTICAST 1
#endif
/* If the user did not specify a priority for Ethernet interrupts, set the
* interrupt priority to the default.
*/
#ifndef CONFIG_LPC17_ETH_PRIORITY
# define CONFIG_LPC17_ETH_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT
#endif
#define PKTBUF_SIZE (MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE)
/* Debug Configuration *****************************************************/
@ -1648,21 +1640,6 @@ static int lpc17_ifup(struct net_driver_s *dev)
lpc17_putreg(0xffffffff, LPC17_ETH_INTCLR);
/* Configure interrupts. The Ethernet interrupt was attached during one-time
* initialization, so we only need to set the interrupt priority, configure
* interrupts, and enable them.
*/
/* Set the interrupt to the highest priority */
#ifdef CONFIG_ARCH_IRQPRIO
#if CONFIG_LPC17_NINTERFACES > 1
(void)up_prioritize_irq(priv->irq, CONFIG_LPC17_ETH_PRIORITY);
#else
(void)up_prioritize_irq(LPC17_IRQ_ETH, CONFIG_LPC17_ETH_PRIORITY);
#endif
#endif
/* Enable Ethernet interrupts. The way we do this depends on whether or
* not Wakeup on Lan (WoL) has been configured.
*/

6
arch/arm/src/lpc2378/lpc23xx_irq.c
View File

@ -276,12 +276,6 @@ void up_attach_vector(int irq, int vector, vic_vector_t handler)
vic_putreg((uint32_t)handler, VIC_VECTADDR0_OFFSET + offset);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(irq, PRIORITY_HIGHEST);
#endif
/* Enable the vectored interrupt */
uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET);

6
arch/arm/src/lpc2378/lpc23xx_serial.c
View File

@ -540,12 +540,6 @@ static int up_attach(struct uart_dev_s *dev)
* UART */
up_enable_irq(priv->irq);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the UART interrupt priority */
up_prioritize_irq(priv->irq, PRIORITY_HIGHEST);
#endif
}
return ret;

3
arch/arm/src/lpc2378/lpc23xx_timerisr.c
View File

@ -190,9 +190,6 @@ void arm_timer_initialize(void)
up_attach_vector(IRQ_SYSTIMER, ???, (vic_vector_t) lpc23xx_timerisr);
#else
(void)irq_attach(IRQ_SYSTIMER, (xcpt_t)lpc23xx_timerisr, NULL);
#ifdef CONFIG_ARCH_IRQPRIO
up_prioritize_irq(IRQ_SYSTIMER, PRIORITY_HIGHEST);
#endif
#endif
/* And enable the system timer interrupt */

10
arch/arm/src/sam34/sam_hsmci.c
View File

@ -107,10 +107,6 @@
# error "This driver requires CONFIG_SDIO_BLOCKSETUP"
#endif
/* Nested interrupts not supported */
#define SAM34_HSMCI_PRIO NVIC_SYSH_PRIORITY_DEFAULT
#ifndef CONFIG_DEBUG_MEMCARD_INFO
# undef CONFIG_SAM34_HSMCI_CMDDEBUG
# undef CONFIG_SAM34_HSMCI_XFRDEBUG
@ -1659,12 +1655,6 @@ static int sam_attach(FAR struct sdio_dev_s *dev)
*/
up_enable_irq(SAM_IRQ_HSMCI);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(SAM_IRQ_HSMCI, SAM34_HSMCI_PRIO);
#endif
}
return ret;

7
arch/arm/src/stm32/Kconfig
View File

@ -9029,13 +9029,6 @@ config STM32_SDIO_DMA
---help---
Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2.
config STM32_SDIO_PRI
hex "SDIO interrupt priority"
default 128
depends on ARCH_IRQPRIO && EXPERIMENTAL
---help---
Select SDIO interrupt priority. Default: 128.
config STM32_SDIO_DMAPRIO
hex "SDIO DMA priority"
default 0x00001000 if STM32_STM32F10XX

13
arch/arm/src/stm32/stm32_capture.c
View File

@ -747,19 +747,6 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, voi
}
#endif
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT);
# ifdef USE_ADVENCED_TIM
if (priv->irq_of)
{
up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT);
}
# endif
#endif
return OK;
}

10
arch/arm/src/stm32/stm32_dma_v1.c
View File

@ -69,10 +69,6 @@
# define DMA_NCHANNELS DMA1_NCHANNELS
#endif
#ifndef CONFIG_DMA_PRI
# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/* Convert the DMA channel base address to the DMA register block address */
#define DMA_BASE(ch) (ch & 0xfffffc00)
@ -363,12 +359,6 @@ void weak_function up_dma_initialize(void)
/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
up_enable_irq(dmach->irq);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI);
#endif
}
}

10
arch/arm/src/stm32/stm32_dma_v2.c
View File

@ -72,10 +72,6 @@
# define DMA_NSTREAMS DMA1_NSTREAMS
#endif
#ifndef CONFIG_DMA_PRI
# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/* Convert the DMA stream base address to the DMA register block address */
#define DMA_BASE(ch) (ch & 0xfffffc00)
@ -494,12 +490,6 @@ void weak_function up_dma_initialize(void)
/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
up_enable_irq(dmast->irq);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(dmast->irq, CONFIG_DMA_PRI);
#endif
}
}

9
arch/arm/src/stm32/stm32_otgfs.h
View File

@ -50,15 +50,6 @@
#if defined(CONFIG_STM32_OTGFS)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#ifndef CONFIG_OTGFS_PRI
# define CONFIG_OTGFS_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Functions
************************************************************************************/

6
arch/arm/src/stm32/stm32_otgfsdev.c
View File

@ -5523,12 +5523,6 @@ void up_usbinitialize(void)
/* Enable USB controller interrupts at the NVIC */
up_enable_irq(STM32_IRQ_OTGFS);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(STM32_IRQ_OTGFS, CONFIG_OTGFS_PRI);
#endif
return;
errout:

9
arch/arm/src/stm32/stm32_otghs.h
View File

@ -49,15 +49,6 @@
#if defined(CONFIG_STM32_OTGHS)
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#ifndef CONFIG_OTGHS_PRI
# define CONFIG_OTGHS_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Functions
************************************************************************************/

6
arch/arm/src/stm32/stm32_otghsdev.c
View File

@ -5462,12 +5462,6 @@ void up_usbinitialize(void)
/* Enable USB controller interrupts at the NVIC */
up_enable_irq(STM32_IRQ_OTGHS);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(STM32_IRQ_OTGHS, CONFIG_OTGHS_PRI);
#endif
return;
errout:

12
arch/arm/src/stm32/stm32_sdio.c
View File

@ -91,8 +91,6 @@
* CONFIG_STM32_SDIO_WIDTH_D1_ONLY - This may be selected to force the
* driver operate with only a single data line (the default is to use
* all 4 SD data lines).
* CONFIG_STM32_SDIO_PRI - SDIO interrupt priority. This setting is not very
* important since interrupt nesting is not currently supported.
* CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selecte if
* CONFIG_STM32_SDIO_DMA is enabled.
* CONFIG_SDIO_XFRDEBUG - Enables some very low-level debug output
@ -118,10 +116,6 @@
# error "Callback support requires CONFIG_SCHED_WORKQUEUE"
#endif
#ifndef CONFIG_STM32_SDIO_PRI
# define CONFIG_STM32_SDIO_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
#ifdef CONFIG_STM32_SDIO_DMA
# ifndef CONFIG_STM32_SDIO_DMAPRIO
# if defined(CONFIG_STM32_STM32F10XX)
@ -1851,12 +1845,6 @@ static int stm32_attach(FAR struct sdio_dev_s *dev)
*/
up_enable_irq(STM32_IRQ_SDIO);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(STM32_IRQ_SDIO, CONFIG_STM32_SDIO_PRI);
#endif
}
return ret;

6
arch/arm/src/stm32/stm32_tim.c
View File

@ -1656,12 +1656,6 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler,
irq_attach(vectorno, handler ,arg);
up_enable_irq(vectorno);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT);
#endif
return OK;
}

11
arch/arm/src/stm32/stm32_usbdev.c
View File

@ -81,10 +81,6 @@
# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE
#endif
#ifndef CONFIG_USB_PRI
# define CONFIG_USB_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/* USB Interrupts. Should be re-mapped if CAN is used. */
#ifdef CONFIG_STM32_STM32F30XX
@ -3866,13 +3862,6 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
up_enable_irq(STM32_IRQ_USBHP);
up_enable_irq(STM32_IRQ_USBLP);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(STM32_IRQ_USBHP, CONFIG_USB_PRI);
up_prioritize_irq(STM32_IRQ_USBLP, CONFIG_USB_PRI);
#endif
/* Enable pull-up to connect the device. The host should enumerate us
* some time after this
*/

10
arch/arm/src/stm32f0/stm32f0_usbdev.c
View File

@ -83,10 +83,6 @@
# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE
#endif
#ifndef CONFIG_USB_PRI
# define CONFIG_USB_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/* Extremely detailed register debug that you would normally never want
* enabled.
*/
@ -3800,12 +3796,6 @@ int usbdev_register(struct usbdevclass_driver_s *driver)
up_enable_irq(STM32F0_IRQ_USB);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(STM32F0_IRQ_USB, CONFIG_USB_PRI);
#endif
/* Enable pull-up to connect the device. The host should enumerate us
* some time after this
*/

14
arch/arm/src/stm32f7/Kconfig
View File

@ -2033,13 +2033,6 @@ config STM32F7_SDMMC_DMA
menu "SDMMC1 Configuration"
depends on STM32F7_SDMMC1
config STM32F7_SDMMC1_PRI
hex "SDMMC1 interrupt priority"
default 128
depends on ARCH_IRQPRIO && EXPERIMENTAL
---help---
Select SDMMC1 interrupt priority. Default: 128.
config STM32F7_SDMMC1_DMAPRIO
hex "SDMMC1 DMA priority"
default 0x00010000
@ -2076,13 +2069,6 @@ endmenu # "SDMMC1 Configuration"
menu "SDMMC2 Configuration"
depends on STM32F7_SDMMC2
config STM32F7_SDMMC2_PRI
hex "SDMMC2 interrupt priority"
default 128
depends on ARCH_IRQPRIO && EXPERIMENTAL
---help---
Select SDMMC2 interrupt priority. Default: 128.
config STM32F7_SDMMC2_DMAPRIO
hex "SDMMC2 DMA priority"
default 0x00010000

13
arch/arm/src/stm32f7/stm32_capture.c
View File

@ -746,19 +746,6 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, voi
}
#endif
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT);
# ifdef USE_ADVENCED_TIM
if (priv->irq_of)
{
up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT);
}
# endif
#endif
return OK;
}

10
arch/arm/src/stm32f7/stm32_dma.c
View File

@ -76,10 +76,6 @@
# define DMA_NSTREAMS DMA1_NSTREAMS
#endif
#ifndef CONFIG_DMA_PRI
# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/* Convert the DMA stream base address to the DMA register block address */
#define DMA_BASE(ch) ((ch) & 0xfffffc00)
@ -498,12 +494,6 @@ void weak_function up_dma_initialize(void)
/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
up_enable_irq(dmast->irq);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(dmast->irq, CONFIG_DMA_PRI);
#endif
}
}

4
arch/arm/src/stm32f7/stm32_otg.h
View File

@ -54,10 +54,6 @@
************************************************************************************/
/* Configuration ********************************************************************/
#ifndef CONFIG_OTG_PRI
# define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
#if defined(CONFIG_STM32F7_OTGFS)
# define STM32_IRQ_OTG STM32_IRQ_OTGFS
# define STM32_OTG_BASE STM32_USBOTGFS_BASE

6
arch/arm/src/stm32f7/stm32_otgdev.c
View File

@ -5579,12 +5579,6 @@ void up_usbinitialize(void)
/* Enable USB controller interrupts at the NVIC */
up_enable_irq(STM32_IRQ_OTG);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(STM32_IRQ_OTG, CONFIG_OTG_PRI);
#endif
return;
errout:

28
arch/arm/src/stm32f7/stm32_sdmmc.c
View File

@ -95,8 +95,6 @@
* CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver
* operate with only a single data line (the default is to use all
* 4 SD data lines).
* CONFIG_SDMMC_PRI - SDMMC interrupt priority. This setting is not very
* important since interrupt nesting is not currently supported.
* CONFIG_SDMMMC_DMAPRIO - SDMMC DMA priority. This can be selecte if
* CONFIG_STM32F7_SDMMC_DMA is enabled.
* CONFIG_CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug
@ -127,11 +125,6 @@
# error "Callback support requires CONFIG_SCHED_WORKQUEUE"
#endif
#ifdef CONFIG_STM32F7_SDMMC1
# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC1_PRI)
# define CONFIG_SDMMC1_PRI NVIC_SYSH_PRIORITY_DEFAULT
# endif
# ifdef CONFIG_STM32F7_SDMMC_DMA
# ifndef CONFIG_STM32F7_SDMMC1_DMAPRIO
# define CONFIG_STM32F7_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI
@ -144,11 +137,6 @@
# endif
#endif
#ifdef CONFIG_STM32F7_SDMMC2
# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC2_PRI)
# define CONFIG_SDMMC2_PRI NVIC_SYSH_PRIORITY_DEFAULT
# endif
# ifdef CONFIG_STM32F7_SDMMC_DMA
# ifndef CONFIG_STM32F7_SDMMC2_DMAPRIO
# define CONFIG_STM32F7_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI
@ -363,9 +351,6 @@ struct stm32_dev_s
/* STM32-specific extensions */
uint32_t base;
int nirq;
#ifdef CONFIG_ARCH_IRQPRIO
int irqprio;
#endif
#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
uint32_t d0_gpio;
#endif
@ -632,9 +617,6 @@ struct stm32_dev_s g_sdmmcdev1 =
},
.base = STM32_SDMMC1_BASE,
.nirq = STM32_IRQ_SDMMC1,
#ifdef CONFIG_SDMMC1_PRI
.irqprio = CONFIG_SDMMC1_PRI,
#endif
#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
.d0_gpio = GPIO_SDMMC1_D0,
#endif
@ -703,9 +685,6 @@ struct stm32_dev_s g_sdmmcdev2 =
},
.base = STM32_SDMMC2_BASE,
.nirq = STM32_IRQ_SDMMC2,
#ifdef CONFIG_SDMMC2_PRI
.irqprio = CONFIG_SDMMC2_PRI,
#endif
#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
.d0_gpio = GPIO_SDMMC2_D0,
#endif
@ -2129,13 +2108,6 @@ static int stm32_attach(FAR struct sdio_dev_s *dev)
*/
up_enable_irq(priv->nirq);
#if defined(CONFIG_ARCH_IRQPRIO) && (defined(CONFIG_STM32F7_SDMMC1_DMAPRIO) || \
defined(CONFIG_STM32F7_SDMMC2_DMAPRIO))
/* Set the interrupt priority */
up_prioritize_irq(priv->nirq, priv->irqprio);
#endif
}
return ret;

6
arch/arm/src/stm32f7/stm32_tim.c
View File

@ -586,12 +586,6 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
irq_attach(vectorno, handler, arg);
up_enable_irq(vectorno);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT);
#endif
return OK;
}

7
arch/arm/src/stm32l4/Kconfig
View File

@ -4070,13 +4070,6 @@ config STM32L4_SDMMC_DMA
menu "SDMMC1 Configuration"
depends on STM32L4_SDMMC1
config STM32L4_SDMMC1_PRI
hex "SDMMC1 interrupt priority"
default 128
depends on ARCH_IRQPRIO && EXPERIMENTAL
---help---
Select SDMMC1 interrupt priority. Default: 128.
config STM32L4_SDMMC1_DMAPRIO
hex "SDMMC1 DMA priority"
default 0x00001000

9
arch/arm/src/stm32l4/stm32l4_otgfs.h
View File

@ -57,15 +57,6 @@
# error "Unsupported STM32L4 chip"
#endif
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#ifndef CONFIG_OTGFS_PRI
# define CONFIG_OTGFS_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/************************************************************************************
* Public Functions
************************************************************************************/

6
arch/arm/src/stm32l4/stm32l4_otgfsdev.c
View File

@ -5593,12 +5593,6 @@ void up_usbinitialize(void)
/* Enable USB controller interrupts at the NVIC */
up_enable_irq(STM32L4_IRQ_OTGFS);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(STM32L4_IRQ_OTGFS, CONFIG_OTGFS_PRI);
#endif
return;
errout:

28
arch/arm/src/stm32l4/stm32l4_sdmmc.c
View File

@ -94,8 +94,6 @@
* CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver
* operate with only a single data line (the default is to use all
* 4 SD data lines).
* CONFIG_SDMMC_PRI - SDMMC interrupt priority. This setting is not very
* important since interrupt nesting is not currently supported.
* CONFIG_SDMMMC_DMAPRIO - SDMMC DMA priority. This can be selecte if
* CONFIG_STM32L4_SDMMC_DMA is enabled.
* CONFIG_CONFIG_STM32L4_SDMMC_XFRDEBUG - Enables some very low-level debug output
@ -117,11 +115,6 @@
# error "Callback support requires CONFIG_SCHED_WORKQUEUE"
#endif
#ifdef CONFIG_STM32L4_SDMMC1
# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC1_PRI)
# define CONFIG_SDMMC1_PRI NVIC_SYSH_PRIORITY_DEFAULT
# endif
# ifdef CONFIG_STM32L4_SDMMC_DMA
# ifndef CONFIG_STM32L4_SDMMC1_DMAPRIO
# define CONFIG_STM32L4_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI
@ -134,11 +127,6 @@
# endif
#endif
#ifdef CONFIG_STM32L4_SDMMC2
# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC2_PRI)
# define CONFIG_SDMMC2_PRI NVIC_SYSH_PRIORITY_DEFAULT
# endif
# ifdef CONFIG_STM32L4_SDMMC_DMA
# ifndef CONFIG_STM32L4_SDMMC2_DMAPRIO
# define CONFIG_STM32L4_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI
@ -342,9 +330,6 @@ struct stm32_dev_s
/* STM32-specific extensions */
uint32_t base;
int nirq;
#ifdef CONFIG_ARCH_IRQPRIO
int irqprio;
#endif
#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
uint32_t d0_gpio;
#endif
@ -594,9 +579,6 @@ struct stm32_dev_s g_sdmmcdev1 =
},
.base = STM32L4_SDMMC1_BASE,
.nirq = STM32L4_IRQ_SDMMC1,
#ifdef CONFIG_SDMMC1_PRI
.irqprio = CONFIG_SDMMC1_PRI,
#endif
#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
.d0_gpio = GPIO_SDMMC1_D0,
#endif
@ -650,9 +632,6 @@ struct stm32_dev_s g_sdmmcdev2 =
},
.base = STM32_SDMMC2_BASE,
.nirq = STM32_IRQ_SDMMC2,
#ifdef CONFIG_SDMMC2_PRI
.irqprio = CONFIG_SDMMC2_PRI,
#endif
#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
.d0_gpio = GPIO_SDMMC2_D0,
#endif
@ -1959,13 +1938,6 @@ static int stm32_attach(FAR struct sdio_dev_s *dev)
*/
up_enable_irq(priv->nirq);
#if defined(CONFIG_ARCH_IRQPRIO) && (defined(CONFIG_STM32L4_SDMMC1_DMAPRIO) || \
defined(CONFIG_STM32L4_SDMMC2_DMAPRIO))
/* Set the interrupt priority */
up_prioritize_irq(priv->nirq, priv->irqprio);
#endif
}
return ret;

6
arch/arm/src/stm32l4/stm32l4_tim.c
View File

@ -1451,12 +1451,6 @@ static int stm32l4_tim_setisr(FAR struct stm32l4_tim_dev_s *dev,
irq_attach(vectorno, handler, arg);
up_enable_irq(vectorno);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT);
#endif
return OK;
}

10
arch/arm/src/stm32l4/stm32l4x6xx_dma.c
View File

@ -70,10 +70,6 @@
# define DMA_NCHANNELS DMA1_NCHANNELS
#endif
#ifndef CONFIG_DMA_PRI
# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
#endif
/* Convert the DMA channel base address to the DMA register block address */
#define DMA_BASE(ch) (ch & 0xfffffc00)
@ -365,12 +361,6 @@ void weak_function up_dma_initialize(void)
/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
up_enable_irq(dmach->irq);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the interrupt priority */
up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI);
#endif
}
}

14
arch/arm/src/str71x/str71x_serial.c
View File

@ -80,14 +80,6 @@
# undef HAVE_CONSOLE
#endif
/* Did the user select a priority? */
#ifndef CONFIG_UART_PRI
# define CONFIG_UART_PRI 1
#elif CONFIG_UART_PRI <= 1 || CONFIG_UART_PRI > 15
# error "CONFIG_UART_PRI is out of range"
#endif
/* If we are not using the serial driver for the console, then we
* still must provide some minimal implementation of up_putc().
*/
@ -626,12 +618,6 @@ static int up_attach(struct uart_dev_s *dev)
*/
up_enable_irq(priv->irq);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the uart interrupt priority (the default value is one) */
up_prioritize_irq(priv->irq, CONFIG_UART_PRI);
#endif
}
return ret;

14
arch/arm/src/str71x/str71x_timerisr.c
View File

@ -58,14 +58,6 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration */
#ifndef CONFIG_TIM_PRI
# define CONFIG_TIM_PRI 1
#elif CONFIG_TIM_PRI <= 1 || CONFIG_TIM_PRI > 15
# error "CONFIG_TIM_PRI is out of range"
#endif
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
@ -196,12 +188,6 @@ void arm_timer_initialize(void)
putreg16(OCAR_VALUE, STR71X_TIMER0_OCAR);
putreg16(0xfffc, STR71X_TIMER0_CNTR);
#ifdef CONFIG_ARCH_IRQPRIO
/* Set the timer interrupt priority */
up_prioritize_irq(STR71X_IRQ_SYSTIMER, CONFIG_TIM_PRI);
#endif
/* Attach the timer interrupt vector */
(void)irq_attach(STR71X_IRQ_SYSTIMER, (xcpt_t)str71x_timerisr, NULL);