From 5832c150d7f39f51f795bbfab2f3febe7f21a067 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 6 Dec 2018 13:33:58 -0600 Subject: [PATCH] arch/arc/src: Remove all driver-specific logic to set the interrupt priority. There is no good reason to change the interrupt priority unless you just want to debug a difficult problem. OR is you want to use high priority interrupts. In that case the specific interrupt priorities will need to be set by board-specific logic. --- arch/arm/src/efm32/efm32_usb.h | 9 -------- arch/arm/src/efm32/efm32_usbdev.c | 6 ------ arch/arm/src/imxrt/imxrt_config.h | 6 ------ arch/arm/src/imxrt/imxrt_enet.c | 6 ------ arch/arm/src/lpc17xx/Kconfig | 7 ------- arch/arm/src/lpc17xx/lpc17_ethernet.c | 23 -------------------- arch/arm/src/lpc2378/lpc23xx_irq.c | 6 ------ arch/arm/src/lpc2378/lpc23xx_serial.c | 6 ------ arch/arm/src/lpc2378/lpc23xx_timerisr.c | 3 --- arch/arm/src/sam34/sam_hsmci.c | 10 --------- arch/arm/src/stm32/Kconfig | 7 ------- arch/arm/src/stm32/stm32_capture.c | 13 ------------ arch/arm/src/stm32/stm32_dma_v1.c | 10 --------- arch/arm/src/stm32/stm32_dma_v2.c | 10 --------- arch/arm/src/stm32/stm32_otgfs.h | 9 -------- arch/arm/src/stm32/stm32_otgfsdev.c | 6 ------ arch/arm/src/stm32/stm32_otghs.h | 9 -------- arch/arm/src/stm32/stm32_otghsdev.c | 6 ------ arch/arm/src/stm32/stm32_sdio.c | 12 ----------- arch/arm/src/stm32/stm32_tim.c | 6 ------ arch/arm/src/stm32/stm32_usbdev.c | 11 ---------- arch/arm/src/stm32f0/stm32f0_usbdev.c | 10 --------- arch/arm/src/stm32f7/Kconfig | 14 ------------- arch/arm/src/stm32f7/stm32_capture.c | 13 ------------ arch/arm/src/stm32f7/stm32_dma.c | 10 --------- arch/arm/src/stm32f7/stm32_otg.h | 4 ---- arch/arm/src/stm32f7/stm32_otgdev.c | 6 ------ arch/arm/src/stm32f7/stm32_sdmmc.c | 28 ------------------------- arch/arm/src/stm32f7/stm32_tim.c | 6 ------ arch/arm/src/stm32l4/Kconfig | 7 ------- arch/arm/src/stm32l4/stm32l4_otgfs.h | 9 -------- arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 6 ------ arch/arm/src/stm32l4/stm32l4_sdmmc.c | 28 ------------------------- arch/arm/src/stm32l4/stm32l4_tim.c | 6 ------ arch/arm/src/stm32l4/stm32l4x6xx_dma.c | 10 --------- arch/arm/src/str71x/str71x_serial.c | 14 ------------- arch/arm/src/str71x/str71x_timerisr.c | 14 ------------- 37 files changed, 366 deletions(-) diff --git a/arch/arm/src/efm32/efm32_usb.h b/arch/arm/src/efm32/efm32_usb.h index 7b31eb467a..4f0e25d8d9 100644 --- a/arch/arm/src/efm32/efm32_usb.h +++ b/arch/arm/src/efm32/efm32_usb.h @@ -48,15 +48,6 @@ #if defined(CONFIG_EFM32_OTGFS) -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ - -#ifndef CONFIG_OTGFS_PRI -# define CONFIG_OTGFS_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/efm32/efm32_usbdev.c b/arch/arm/src/efm32/efm32_usbdev.c index 742d233a7b..eedec628e9 100644 --- a/arch/arm/src/efm32/efm32_usbdev.c +++ b/arch/arm/src/efm32/efm32_usbdev.c @@ -5507,12 +5507,6 @@ void up_usbinitialize(void) /* Enable USB controller interrupts at the NVIC */ up_enable_irq(EFM32_IRQ_USB); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(EFM32_IRQ_USB, CONFIG_OTGFS_PRI); -#endif return; errout: diff --git a/arch/arm/src/imxrt/imxrt_config.h b/arch/arm/src/imxrt/imxrt_config.h index 129fcc25b6..7de1393097 100644 --- a/arch/arm/src/imxrt/imxrt_config.h +++ b/arch/arm/src/imxrt/imxrt_config.h @@ -215,12 +215,6 @@ #define IMXRT_ENET_HAS_DBSWAP 1 -/* EMAC Default Interrupt Priorities */ - -#ifndef CONFIG_IMXRT_ENET_PRIO -# define CONFIG_IMXRT_ENET_PRIO NVIC_SYSH_PRIORITY_DEFAULT -#endif - /************************************************************************************ * Public Functions ************************************************************************************/ diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index 959a90bfea..649ac5b0d9 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -2478,12 +2478,6 @@ int imxrt_netinitialize(int intf) putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXEN_OFFSET); putreg32(1, IMXRT_IOMUXC_BASE+IMXRT_INPUT_ENET_RXERR_OFFSET); -#ifdef CONFIG_ARCH_IRQPRIO - /* Set interrupt priority levels */ - - up_prioritize_irq(IMXRT_IRQ_ENET, CONFIG_IMXRT_ENET_PRIO); -#endif - /* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */ #if 0 diff --git a/arch/arm/src/lpc17xx/Kconfig b/arch/arm/src/lpc17xx/Kconfig index b021c08bca..eb67a50d47 100644 --- a/arch/arm/src/lpc17xx/Kconfig +++ b/arch/arm/src/lpc17xx/Kconfig @@ -690,13 +690,6 @@ config LPC17_ETH_NRXDESC ---help--- Configured number of Rx descriptors. Default: 13 -config LPC17_ETH_PRIORITY - int "Ethernet interrupt priority" - default 128 - depends on ARCH_IRQPRIO && EXPERIMENTAL - ---help--- - Ethernet interrupt priority. The default is the default priority (128). - config LPC17_NET_WOL bool "Wake-up on LAN" default n diff --git a/arch/arm/src/lpc17xx/lpc17_ethernet.c b/arch/arm/src/lpc17xx/lpc17_ethernet.c index 89fe89d6b0..49554ac80d 100644 --- a/arch/arm/src/lpc17xx/lpc17_ethernet.c +++ b/arch/arm/src/lpc17xx/lpc17_ethernet.c @@ -126,14 +126,6 @@ # define CONFIG_LPC17_MULTICAST 1 #endif -/* If the user did not specify a priority for Ethernet interrupts, set the - * interrupt priority to the default. - */ - -#ifndef CONFIG_LPC17_ETH_PRIORITY -# define CONFIG_LPC17_ETH_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT -#endif - #define PKTBUF_SIZE (MAX_NETDEV_PKTSIZE + CONFIG_NET_GUARDSIZE) /* Debug Configuration *****************************************************/ @@ -1648,21 +1640,6 @@ static int lpc17_ifup(struct net_driver_s *dev) lpc17_putreg(0xffffffff, LPC17_ETH_INTCLR); - /* Configure interrupts. The Ethernet interrupt was attached during one-time - * initialization, so we only need to set the interrupt priority, configure - * interrupts, and enable them. - */ - - /* Set the interrupt to the highest priority */ - -#ifdef CONFIG_ARCH_IRQPRIO -#if CONFIG_LPC17_NINTERFACES > 1 - (void)up_prioritize_irq(priv->irq, CONFIG_LPC17_ETH_PRIORITY); -#else - (void)up_prioritize_irq(LPC17_IRQ_ETH, CONFIG_LPC17_ETH_PRIORITY); -#endif -#endif - /* Enable Ethernet interrupts. The way we do this depends on whether or * not Wakeup on Lan (WoL) has been configured. */ diff --git a/arch/arm/src/lpc2378/lpc23xx_irq.c b/arch/arm/src/lpc2378/lpc23xx_irq.c index ba82aaf3b8..a17d63d691 100644 --- a/arch/arm/src/lpc2378/lpc23xx_irq.c +++ b/arch/arm/src/lpc2378/lpc23xx_irq.c @@ -276,12 +276,6 @@ void up_attach_vector(int irq, int vector, vic_vector_t handler) vic_putreg((uint32_t)handler, VIC_VECTADDR0_OFFSET + offset); -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(irq, PRIORITY_HIGHEST); -#endif - /* Enable the vectored interrupt */ uint32_t val = vic_getreg(VIC_INTENABLE_OFFSET); diff --git a/arch/arm/src/lpc2378/lpc23xx_serial.c b/arch/arm/src/lpc2378/lpc23xx_serial.c index c927b07a2c..d65e01af79 100644 --- a/arch/arm/src/lpc2378/lpc23xx_serial.c +++ b/arch/arm/src/lpc2378/lpc23xx_serial.c @@ -540,12 +540,6 @@ static int up_attach(struct uart_dev_s *dev) * UART */ up_enable_irq(priv->irq); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the UART interrupt priority */ - - up_prioritize_irq(priv->irq, PRIORITY_HIGHEST); -#endif } return ret; diff --git a/arch/arm/src/lpc2378/lpc23xx_timerisr.c b/arch/arm/src/lpc2378/lpc23xx_timerisr.c index 1cbd4b650d..02afab08d2 100644 --- a/arch/arm/src/lpc2378/lpc23xx_timerisr.c +++ b/arch/arm/src/lpc2378/lpc23xx_timerisr.c @@ -190,9 +190,6 @@ void arm_timer_initialize(void) up_attach_vector(IRQ_SYSTIMER, ???, (vic_vector_t) lpc23xx_timerisr); #else (void)irq_attach(IRQ_SYSTIMER, (xcpt_t)lpc23xx_timerisr, NULL); -#ifdef CONFIG_ARCH_IRQPRIO - up_prioritize_irq(IRQ_SYSTIMER, PRIORITY_HIGHEST); -#endif #endif /* And enable the system timer interrupt */ diff --git a/arch/arm/src/sam34/sam_hsmci.c b/arch/arm/src/sam34/sam_hsmci.c index 6543251c12..3e0a727687 100644 --- a/arch/arm/src/sam34/sam_hsmci.c +++ b/arch/arm/src/sam34/sam_hsmci.c @@ -107,10 +107,6 @@ # error "This driver requires CONFIG_SDIO_BLOCKSETUP" #endif -/* Nested interrupts not supported */ - -#define SAM34_HSMCI_PRIO NVIC_SYSH_PRIORITY_DEFAULT - #ifndef CONFIG_DEBUG_MEMCARD_INFO # undef CONFIG_SAM34_HSMCI_CMDDEBUG # undef CONFIG_SAM34_HSMCI_XFRDEBUG @@ -1659,12 +1655,6 @@ static int sam_attach(FAR struct sdio_dev_s *dev) */ up_enable_irq(SAM_IRQ_HSMCI); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(SAM_IRQ_HSMCI, SAM34_HSMCI_PRIO); -#endif } return ret; diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 1d409e6129..db703d0309 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -9029,13 +9029,6 @@ config STM32_SDIO_DMA ---help--- Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. -config STM32_SDIO_PRI - hex "SDIO interrupt priority" - default 128 - depends on ARCH_IRQPRIO && EXPERIMENTAL - ---help--- - Select SDIO interrupt priority. Default: 128. - config STM32_SDIO_DMAPRIO hex "SDIO DMA priority" default 0x00001000 if STM32_STM32F10XX diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c index c1d2dc9e4f..6532c35004 100644 --- a/arch/arm/src/stm32/stm32_capture.c +++ b/arch/arm/src/stm32/stm32_capture.c @@ -747,19 +747,6 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, voi } #endif -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT); - -# ifdef USE_ADVENCED_TIM - if (priv->irq_of) - { - up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT); - } -# endif -#endif - return OK; } diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/stm32/stm32_dma_v1.c index 9010523406..12d53f8f6b 100644 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ b/arch/arm/src/stm32/stm32_dma_v1.c @@ -69,10 +69,6 @@ # define DMA_NCHANNELS DMA1_NCHANNELS #endif -#ifndef CONFIG_DMA_PRI -# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /* Convert the DMA channel base address to the DMA register block address */ #define DMA_BASE(ch) (ch & 0xfffffc00) @@ -363,12 +359,6 @@ void weak_function up_dma_initialize(void) /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ up_enable_irq(dmach->irq); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI); -#endif } } diff --git a/arch/arm/src/stm32/stm32_dma_v2.c b/arch/arm/src/stm32/stm32_dma_v2.c index 0a68b474f7..67590fe38d 100644 --- a/arch/arm/src/stm32/stm32_dma_v2.c +++ b/arch/arm/src/stm32/stm32_dma_v2.c @@ -72,10 +72,6 @@ # define DMA_NSTREAMS DMA1_NSTREAMS #endif -#ifndef CONFIG_DMA_PRI -# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /* Convert the DMA stream base address to the DMA register block address */ #define DMA_BASE(ch) (ch & 0xfffffc00) @@ -494,12 +490,6 @@ void weak_function up_dma_initialize(void) /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ up_enable_irq(dmast->irq); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(dmast->irq, CONFIG_DMA_PRI); -#endif } } diff --git a/arch/arm/src/stm32/stm32_otgfs.h b/arch/arm/src/stm32/stm32_otgfs.h index ba3549379c..4860e7d004 100644 --- a/arch/arm/src/stm32/stm32_otgfs.h +++ b/arch/arm/src/stm32/stm32_otgfs.h @@ -50,15 +50,6 @@ #if defined(CONFIG_STM32_OTGFS) -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ - -#ifndef CONFIG_OTGFS_PRI -# define CONFIG_OTGFS_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /************************************************************************************ * Public Functions ************************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/stm32/stm32_otgfsdev.c index cdbb3729d5..bc07368367 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/stm32/stm32_otgfsdev.c @@ -5523,12 +5523,6 @@ void up_usbinitialize(void) /* Enable USB controller interrupts at the NVIC */ up_enable_irq(STM32_IRQ_OTGFS); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(STM32_IRQ_OTGFS, CONFIG_OTGFS_PRI); -#endif return; errout: diff --git a/arch/arm/src/stm32/stm32_otghs.h b/arch/arm/src/stm32/stm32_otghs.h index 2c36cb801f..d077bc2579 100644 --- a/arch/arm/src/stm32/stm32_otghs.h +++ b/arch/arm/src/stm32/stm32_otghs.h @@ -49,15 +49,6 @@ #if defined(CONFIG_STM32_OTGHS) -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ - -#ifndef CONFIG_OTGHS_PRI -# define CONFIG_OTGHS_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /************************************************************************************ * Public Functions ************************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/stm32/stm32_otghsdev.c index f22e8fd771..833839f0f6 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/stm32/stm32_otghsdev.c @@ -5462,12 +5462,6 @@ void up_usbinitialize(void) /* Enable USB controller interrupts at the NVIC */ up_enable_irq(STM32_IRQ_OTGHS); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(STM32_IRQ_OTGHS, CONFIG_OTGHS_PRI); -#endif return; errout: diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/stm32/stm32_sdio.c index 3ae446b574..9eabf1042d 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/stm32/stm32_sdio.c @@ -91,8 +91,6 @@ * CONFIG_STM32_SDIO_WIDTH_D1_ONLY - This may be selected to force the * driver operate with only a single data line (the default is to use * all 4 SD data lines). - * CONFIG_STM32_SDIO_PRI - SDIO interrupt priority. This setting is not very - * important since interrupt nesting is not currently supported. * CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selecte if * CONFIG_STM32_SDIO_DMA is enabled. * CONFIG_SDIO_XFRDEBUG - Enables some very low-level debug output @@ -118,10 +116,6 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE" #endif -#ifndef CONFIG_STM32_SDIO_PRI -# define CONFIG_STM32_SDIO_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - #ifdef CONFIG_STM32_SDIO_DMA # ifndef CONFIG_STM32_SDIO_DMAPRIO # if defined(CONFIG_STM32_STM32F10XX) @@ -1851,12 +1845,6 @@ static int stm32_attach(FAR struct sdio_dev_s *dev) */ up_enable_irq(STM32_IRQ_SDIO); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(STM32_IRQ_SDIO, CONFIG_STM32_SDIO_PRI); -#endif } return ret; diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index 2baf0967ea..8b1e5cebf6 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -1656,12 +1656,6 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, xcpt_t handler, irq_attach(vectorno, handler ,arg); up_enable_irq(vectorno); -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - return OK; } diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/stm32/stm32_usbdev.c index 55390e2721..15e856fb18 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/stm32/stm32_usbdev.c @@ -81,10 +81,6 @@ # define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE #endif -#ifndef CONFIG_USB_PRI -# define CONFIG_USB_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /* USB Interrupts. Should be re-mapped if CAN is used. */ #ifdef CONFIG_STM32_STM32F30XX @@ -3866,13 +3862,6 @@ int usbdev_register(struct usbdevclass_driver_s *driver) up_enable_irq(STM32_IRQ_USBHP); up_enable_irq(STM32_IRQ_USBLP); -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(STM32_IRQ_USBHP, CONFIG_USB_PRI); - up_prioritize_irq(STM32_IRQ_USBLP, CONFIG_USB_PRI); -#endif - /* Enable pull-up to connect the device. The host should enumerate us * some time after this */ diff --git a/arch/arm/src/stm32f0/stm32f0_usbdev.c b/arch/arm/src/stm32f0/stm32f0_usbdev.c index cf263a3573..018405397d 100644 --- a/arch/arm/src/stm32f0/stm32f0_usbdev.c +++ b/arch/arm/src/stm32f0/stm32f0_usbdev.c @@ -83,10 +83,6 @@ # define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE #endif -#ifndef CONFIG_USB_PRI -# define CONFIG_USB_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /* Extremely detailed register debug that you would normally never want * enabled. */ @@ -3800,12 +3796,6 @@ int usbdev_register(struct usbdevclass_driver_s *driver) up_enable_irq(STM32F0_IRQ_USB); -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(STM32F0_IRQ_USB, CONFIG_USB_PRI); -#endif - /* Enable pull-up to connect the device. The host should enumerate us * some time after this */ diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 27558745a7..5611efec40 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -2033,13 +2033,6 @@ config STM32F7_SDMMC_DMA menu "SDMMC1 Configuration" depends on STM32F7_SDMMC1 -config STM32F7_SDMMC1_PRI - hex "SDMMC1 interrupt priority" - default 128 - depends on ARCH_IRQPRIO && EXPERIMENTAL - ---help--- - Select SDMMC1 interrupt priority. Default: 128. - config STM32F7_SDMMC1_DMAPRIO hex "SDMMC1 DMA priority" default 0x00010000 @@ -2076,13 +2069,6 @@ endmenu # "SDMMC1 Configuration" menu "SDMMC2 Configuration" depends on STM32F7_SDMMC2 -config STM32F7_SDMMC2_PRI - hex "SDMMC2 interrupt priority" - default 128 - depends on ARCH_IRQPRIO && EXPERIMENTAL - ---help--- - Select SDMMC2 interrupt priority. Default: 128. - config STM32F7_SDMMC2_DMAPRIO hex "SDMMC2 DMA priority" default 0x00010000 diff --git a/arch/arm/src/stm32f7/stm32_capture.c b/arch/arm/src/stm32f7/stm32_capture.c index f5e2fa71a9..ed660a54bf 100644 --- a/arch/arm/src/stm32f7/stm32_capture.c +++ b/arch/arm/src/stm32f7/stm32_capture.c @@ -746,19 +746,6 @@ static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler, voi } #endif -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT); - -# ifdef USE_ADVENCED_TIM - if (priv->irq_of) - { - up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT); - } -# endif -#endif - return OK; } diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index b83e81ea20..fa1c61c7f8 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -76,10 +76,6 @@ # define DMA_NSTREAMS DMA1_NSTREAMS #endif -#ifndef CONFIG_DMA_PRI -# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /* Convert the DMA stream base address to the DMA register block address */ #define DMA_BASE(ch) ((ch) & 0xfffffc00) @@ -498,12 +494,6 @@ void weak_function up_dma_initialize(void) /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ up_enable_irq(dmast->irq); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(dmast->irq, CONFIG_DMA_PRI); -#endif } } diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h index 7eba65a61b..26ed5f824b 100644 --- a/arch/arm/src/stm32f7/stm32_otg.h +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -54,10 +54,6 @@ ************************************************************************************/ /* Configuration ********************************************************************/ -#ifndef CONFIG_OTG_PRI -# define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - #if defined(CONFIG_STM32F7_OTGFS) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_USBOTGFS_BASE diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index a12862af98..e71198f1a7 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -5579,12 +5579,6 @@ void up_usbinitialize(void) /* Enable USB controller interrupts at the NVIC */ up_enable_irq(STM32_IRQ_OTG); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(STM32_IRQ_OTG, CONFIG_OTG_PRI); -#endif return; errout: diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index c530241898..1f2cff372a 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -95,8 +95,6 @@ * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). - * CONFIG_SDMMC_PRI - SDMMC interrupt priority. This setting is not very - * important since interrupt nesting is not currently supported. * CONFIG_SDMMMC_DMAPRIO - SDMMC DMA priority. This can be selecte if * CONFIG_STM32F7_SDMMC_DMA is enabled. * CONFIG_CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug @@ -127,11 +125,6 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE" #endif -#ifdef CONFIG_STM32F7_SDMMC1 -# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC1_PRI) -# define CONFIG_SDMMC1_PRI NVIC_SYSH_PRIORITY_DEFAULT -# endif - # ifdef CONFIG_STM32F7_SDMMC_DMA # ifndef CONFIG_STM32F7_SDMMC1_DMAPRIO # define CONFIG_STM32F7_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI @@ -144,11 +137,6 @@ # endif #endif -#ifdef CONFIG_STM32F7_SDMMC2 -# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC2_PRI) -# define CONFIG_SDMMC2_PRI NVIC_SYSH_PRIORITY_DEFAULT -# endif - # ifdef CONFIG_STM32F7_SDMMC_DMA # ifndef CONFIG_STM32F7_SDMMC2_DMAPRIO # define CONFIG_STM32F7_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI @@ -363,9 +351,6 @@ struct stm32_dev_s /* STM32-specific extensions */ uint32_t base; int nirq; -#ifdef CONFIG_ARCH_IRQPRIO - int irqprio; -#endif #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif @@ -632,9 +617,6 @@ struct stm32_dev_s g_sdmmcdev1 = }, .base = STM32_SDMMC1_BASE, .nirq = STM32_IRQ_SDMMC1, -#ifdef CONFIG_SDMMC1_PRI - .irqprio = CONFIG_SDMMC1_PRI, -#endif #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC1_D0, #endif @@ -703,9 +685,6 @@ struct stm32_dev_s g_sdmmcdev2 = }, .base = STM32_SDMMC2_BASE, .nirq = STM32_IRQ_SDMMC2, -#ifdef CONFIG_SDMMC2_PRI - .irqprio = CONFIG_SDMMC2_PRI, -#endif #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC2_D0, #endif @@ -2129,13 +2108,6 @@ static int stm32_attach(FAR struct sdio_dev_s *dev) */ up_enable_irq(priv->nirq); - -#if defined(CONFIG_ARCH_IRQPRIO) && (defined(CONFIG_STM32F7_SDMMC1_DMAPRIO) || \ - defined(CONFIG_STM32F7_SDMMC2_DMAPRIO)) - /* Set the interrupt priority */ - - up_prioritize_irq(priv->nirq, priv->irqprio); -#endif } return ret; diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index 09a7c1f1d8..4eac6ab22a 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -586,12 +586,6 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, irq_attach(vectorno, handler, arg); up_enable_irq(vectorno); -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - return OK; } diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index ca46e3191e..2ca8b4d4fe 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -4070,13 +4070,6 @@ config STM32L4_SDMMC_DMA menu "SDMMC1 Configuration" depends on STM32L4_SDMMC1 -config STM32L4_SDMMC1_PRI - hex "SDMMC1 interrupt priority" - default 128 - depends on ARCH_IRQPRIO && EXPERIMENTAL - ---help--- - Select SDMMC1 interrupt priority. Default: 128. - config STM32L4_SDMMC1_DMAPRIO hex "SDMMC1 DMA priority" default 0x00001000 diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index d9945bdbd5..da4e6673cd 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -57,15 +57,6 @@ # error "Unsupported STM32L4 chip" #endif -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ - -#ifndef CONFIG_OTGFS_PRI -# define CONFIG_OTGFS_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /************************************************************************************ * Public Functions ************************************************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index 6bcfb14bb8..4cac257f9d 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -5593,12 +5593,6 @@ void up_usbinitialize(void) /* Enable USB controller interrupts at the NVIC */ up_enable_irq(STM32L4_IRQ_OTGFS); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(STM32L4_IRQ_OTGFS, CONFIG_OTGFS_PRI); -#endif return; errout: diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index 23a08b052e..0b076a774c 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -94,8 +94,6 @@ * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). - * CONFIG_SDMMC_PRI - SDMMC interrupt priority. This setting is not very - * important since interrupt nesting is not currently supported. * CONFIG_SDMMMC_DMAPRIO - SDMMC DMA priority. This can be selecte if * CONFIG_STM32L4_SDMMC_DMA is enabled. * CONFIG_CONFIG_STM32L4_SDMMC_XFRDEBUG - Enables some very low-level debug output @@ -117,11 +115,6 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE" #endif -#ifdef CONFIG_STM32L4_SDMMC1 -# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC1_PRI) -# define CONFIG_SDMMC1_PRI NVIC_SYSH_PRIORITY_DEFAULT -# endif - # ifdef CONFIG_STM32L4_SDMMC_DMA # ifndef CONFIG_STM32L4_SDMMC1_DMAPRIO # define CONFIG_STM32L4_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI @@ -134,11 +127,6 @@ # endif #endif -#ifdef CONFIG_STM32L4_SDMMC2 -# if defined(CONFIG_ARCH_IRQPRIO) && !defined(CONFIG_SDMMC2_PRI) -# define CONFIG_SDMMC2_PRI NVIC_SYSH_PRIORITY_DEFAULT -# endif - # ifdef CONFIG_STM32L4_SDMMC_DMA # ifndef CONFIG_STM32L4_SDMMC2_DMAPRIO # define CONFIG_STM32L4_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI @@ -342,9 +330,6 @@ struct stm32_dev_s /* STM32-specific extensions */ uint32_t base; int nirq; -#ifdef CONFIG_ARCH_IRQPRIO - int irqprio; -#endif #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif @@ -594,9 +579,6 @@ struct stm32_dev_s g_sdmmcdev1 = }, .base = STM32L4_SDMMC1_BASE, .nirq = STM32L4_IRQ_SDMMC1, -#ifdef CONFIG_SDMMC1_PRI - .irqprio = CONFIG_SDMMC1_PRI, -#endif #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC1_D0, #endif @@ -650,9 +632,6 @@ struct stm32_dev_s g_sdmmcdev2 = }, .base = STM32_SDMMC2_BASE, .nirq = STM32_IRQ_SDMMC2, -#ifdef CONFIG_SDMMC2_PRI - .irqprio = CONFIG_SDMMC2_PRI, -#endif #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC2_D0, #endif @@ -1959,13 +1938,6 @@ static int stm32_attach(FAR struct sdio_dev_s *dev) */ up_enable_irq(priv->nirq); - -#if defined(CONFIG_ARCH_IRQPRIO) && (defined(CONFIG_STM32L4_SDMMC1_DMAPRIO) || \ - defined(CONFIG_STM32L4_SDMMC2_DMAPRIO)) - /* Set the interrupt priority */ - - up_prioritize_irq(priv->nirq, priv->irqprio); -#endif } return ret; diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 78f937660f..0556916ff2 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -1451,12 +1451,6 @@ static int stm32l4_tim_setisr(FAR struct stm32l4_tim_dev_s *dev, irq_attach(vectorno, handler, arg); up_enable_irq(vectorno); -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index f60a619df0..8f7d05bcc6 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -70,10 +70,6 @@ # define DMA_NCHANNELS DMA1_NCHANNELS #endif -#ifndef CONFIG_DMA_PRI -# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT -#endif - /* Convert the DMA channel base address to the DMA register block address */ #define DMA_BASE(ch) (ch & 0xfffffc00) @@ -365,12 +361,6 @@ void weak_function up_dma_initialize(void) /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ up_enable_irq(dmach->irq); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI); -#endif } } diff --git a/arch/arm/src/str71x/str71x_serial.c b/arch/arm/src/str71x/str71x_serial.c index f1688ae383..6b89c83235 100644 --- a/arch/arm/src/str71x/str71x_serial.c +++ b/arch/arm/src/str71x/str71x_serial.c @@ -80,14 +80,6 @@ # undef HAVE_CONSOLE #endif -/* Did the user select a priority? */ - -#ifndef CONFIG_UART_PRI -# define CONFIG_UART_PRI 1 -#elif CONFIG_UART_PRI <= 1 || CONFIG_UART_PRI > 15 -# error "CONFIG_UART_PRI is out of range" -#endif - /* If we are not using the serial driver for the console, then we * still must provide some minimal implementation of up_putc(). */ @@ -626,12 +618,6 @@ static int up_attach(struct uart_dev_s *dev) */ up_enable_irq(priv->irq); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the uart interrupt priority (the default value is one) */ - - up_prioritize_irq(priv->irq, CONFIG_UART_PRI); -#endif } return ret; diff --git a/arch/arm/src/str71x/str71x_timerisr.c b/arch/arm/src/str71x/str71x_timerisr.c index 8fe2bda5aa..295c5acc25 100644 --- a/arch/arm/src/str71x/str71x_timerisr.c +++ b/arch/arm/src/str71x/str71x_timerisr.c @@ -58,14 +58,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* Configuration */ - -#ifndef CONFIG_TIM_PRI -# define CONFIG_TIM_PRI 1 -#elif CONFIG_TIM_PRI <= 1 || CONFIG_TIM_PRI > 15 -# error "CONFIG_TIM_PRI is out of range" -#endif - /* The desired timer interrupt frequency is provided by the definition * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of * system clock ticks per second. That value is a user configurable setting @@ -196,12 +188,6 @@ void arm_timer_initialize(void) putreg16(OCAR_VALUE, STR71X_TIMER0_OCAR); putreg16(0xfffc, STR71X_TIMER0_CNTR); -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the timer interrupt priority */ - - up_prioritize_irq(STR71X_IRQ_SYSTIMER, CONFIG_TIM_PRI); -#endif - /* Attach the timer interrupt vector */ (void)irq_attach(STR71X_IRQ_SYSTIMER, (xcpt_t)str71x_timerisr, NULL);