diff --git a/arch/arm/src/armv8-r/Kconfig b/arch/arm/src/armv8-r/Kconfig index 1ea1736185..8dc77ec88a 100644 --- a/arch/arm/src/armv8-r/Kconfig +++ b/arch/arm/src/armv8-r/Kconfig @@ -92,134 +92,136 @@ config ARMV8R_NONMASKABLE_FIQ default n config ARMV8R_HAVE_L2CC - bool - default n - ---help--- - Selected by the configuration tool if the architecture supports any - kind of L2 cache. + bool + default n + ---help--- + Selected by the configuration tool if the architecture supports any + kind of L2 cache. config ARMV8R_HAVE_L2CC_PL310 - bool - default n - select ARMV8R_HAVE_L2CC - ---help--- - Set by architecture-specific code if the hardware supports a PL310 - r3p2 L2 cache (only version r3p2 is supported). + bool + default n + select ARMV8R_HAVE_L2CC + ---help--- + Set by architecture-specific code if the hardware supports a PL310 + r3p2 L2 cache (only version r3p2 is supported). if ARMV8R_HAVE_L2CC menu "L2 Cache Configuration" config ARMV8R_L2CC_PL310 - bool "ARMv8-R L2CC P310 Support" - default n - depends on ARMV8R_HAVE_L2CC_PL310 - select ARCH_L2CACHE - ---help--- - Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM - multi-way cache macrocell, version r3p2. The addition of an on-chip - secondary cache, also referred to as a Level 2 or L2 cache, is a - method of improving the system performance when significant memory - traffic is generated by the processor. + bool "ARMv8-R L2CC P310 Support" + default n + depends on ARMV8R_HAVE_L2CC_PL310 + select ARCH_L2CACHE + ---help--- + Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM + multi-way cache macrocell, version r3p2. The addition of an on-chip + secondary cache, also referred to as a Level 2 or L2 cache, is a + method of improving the system performance when significant memory + traffic is generated by the processor. if ARCH_L2CACHE if ARMV8R_L2CC_PL310 config PL310_LOCKDOWN_BY_MASTER - bool "PL310 Lockdown by Master" - default n + bool "PL310 Lockdown by Master" + default n config PL310_LOCKDOWN_BY_LINE - bool "PL310 Lockdown by Line" - default n + bool "PL310 Lockdown by Line" + default n config PL310_ADDRESS_FILTERING - bool "PL310 Address Filtering by Line" - default n + bool "PL310 Address Filtering by Line" + default n config PL310_TRCR - bool "PL310 TRCR set by usr" - default n + bool "PL310 TRCR set by usr" + default n if PL310_TRCR config PL310_TRCR_TSETLAT - int "PL310 TRCR setup latency" - default 1 + int "PL310 TRCR setup latency" + default 1 config PL310_TRCR_TRDLAT - int "PL310 TRCR read access latency" - default 1 + int "PL310 TRCR read access latency" + default 1 config PL310_TRCR_TWRLAT - int "PL310 TRCR write access latency" - default 1 + int "PL310 TRCR write access latency" + default 1 + endif # PL310_TRCR config PL310_DRCR - bool "PL310 DRCR set by usr" - default n + bool "PL310 DRCR set by usr" + default n if PL310_DRCR config PL310_DRCR_DSETLAT - int "PL310 DRCR setup latency" - default 1 + int "PL310 DRCR setup latency" + default 1 config PL310_DRCR_DRDLAT - int "PL310 DRCR read access latency" - default 1 + int "PL310 DRCR read access latency" + default 1 config PL310_DRCR_DWRLAT - int "PL310 DRCR write access latency" - default 1 + int "PL310 DRCR write access latency" + default 1 + endif # PL310_DRCR endif # ARMV8R_L2CC_PL310 choice - prompt "L2 Cache Associativity" - default ARMV8R_ASSOCIATIVITY_8WAY - depends on ARCH_L2CACHE - ---help--- - This choice specifies the associativity of L2 cache in terms of the - number of ways. This value could be obtained by querying cache - configuration registers. However, by defining a configuration - setting instead, we can avoid using RAM memory to hold information - about properties of the memory. + prompt "L2 Cache Associativity" + default ARMV8R_ASSOCIATIVITY_8WAY + depends on ARCH_L2CACHE + ---help--- + This choice specifies the associativity of L2 cache in terms of the + number of ways. This value could be obtained by querying cache + configuration registers. However, by defining a configuration + setting instead, we can avoid using RAM memory to hold information + about properties of the memory. config ARMV8R_ASSOCIATIVITY_8WAY - bool "8-Way Associativity" + bool "8-Way Associativity" config ARMV8R_ASSOCIATIVITY_16WAY - bool "16-Way Associativity" + bool "16-Way Associativity" endchoice # L2 Cache Associativity choice - prompt "L2 Cache Way Size" - default ARMV8R_WAYSIZE_16KB - depends on ARCH_L2CACHE - ---help--- - This choice specifies size of each way. This value can be obtained - by querying cache configuration registers. However, by defining a - configuration setting instead, we can avoid using RAM memory to hold - information + prompt "L2 Cache Way Size" + default ARMV8R_WAYSIZE_16KB + depends on ARCH_L2CACHE + ---help--- + This choice specifies size of each way. This value can be obtained + by querying cache configuration registers. However, by defining a + configuration setting instead, we can avoid using RAM memory to hold + information config ARMV8R_WAYSIZE_16KB - bool "16 KiB" + bool "16 KiB" config ARMV8R_WAYSIZE_32KB - bool "32 KiB" + bool "32 KiB" config ARMV8R_WAYSIZE_64KB - bool "64 KiB" + bool "64 KiB" config ARMV8R_WAYSIZE_128KB - bool "128 KiB" + bool "128 KiB" config ARMV8R_WAYSIZE_256KB - bool "256 KiB" + bool "256 KiB" config ARMV8R_WAYSIZE_512KB - bool "512 KiB" + bool "512 KiB" endchoice # L2 Cache Way Size endif # ARCH_L2CACHE diff --git a/boards/Kconfig b/boards/Kconfig index 458150fa3b..bc5002fef1 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1112,9 +1112,9 @@ config ARCH_BOARD_MIZAR32A depends on ARCH_CHIP_AT32UC3A0512 select ARCH_HAVE_LEDS ---help--- - This is a port of NuttX for the Mizar32-A board designed by SimpleMachines, - Italy. The board is based on the AT32UC3A0512 MCU and uses avr32-gcc - version 4.4.7 for its build on GNU/Linux. + This is a port of NuttX for the Mizar32-A board designed by SimpleMachines, + Italy. The board is based on the AT32UC3A0512 MCU and uses avr32-gcc + version 4.4.7 for its build on GNU/Linux. config ARCH_BOARD_MOTEINO_MEGA bool "LowPowerLab MoteinoMEGA" diff --git a/boards/arm/csk6/csk6011a-nano/Kconfig b/boards/arm/csk6/csk6011a-nano/Kconfig index 6bc1f4e783..2694a73c27 100644 --- a/boards/arm/csk6/csk6011a-nano/Kconfig +++ b/boards/arm/csk6/csk6011a-nano/Kconfig @@ -8,10 +8,10 @@ choice prompt "Console Mode" default CSK6_CONSOLE_UART0 - config CSK6_CONSOLE_UART0 - bool "USART0 is a console port" - select USART0_SERIALDRIVER - +config CSK6_CONSOLE_UART0 + bool "USART0 is a console port" + select USART0_SERIALDRIVER + #TODO add support other port endchoice # USART0 Mode endif diff --git a/drivers/sensors/Kconfig b/drivers/sensors/Kconfig index a463873870..e9201a6c51 100644 --- a/drivers/sensors/Kconfig +++ b/drivers/sensors/Kconfig @@ -1534,7 +1534,7 @@ config SHT4X_I2C_FREQUENCY config SHT4X_I2C_ADDR hex "SHT4X I2C address" default 0x44 - range 0x44 0x46 + range 0x44 0x46 ---help--- Enables debug features for the SHT4X @@ -1718,34 +1718,34 @@ config SENSORS_LTR308_THREAD_STACKSIZE endif # SENSORS_LTR308 config SENSORS_AMG88XX - bool "AMG88xx infrared array sensor" - default n - select I2C - ---help--- - Enable driver support for AMG88xx infrared array sensor. + bool "AMG88xx infrared array sensor" + default n + select I2C + ---help--- + Enable driver support for AMG88xx infrared array sensor. if SENSORS_AMG88XX choice - prompt "AMG88xx AD_SELECT value" - default SENSOR_AMG88XX_AD_SELECT_0 - ---help--- - AD SELECT sets the amg88xx i2c address - AD_SELECT tied to GND -> sensor address 0x68 - AD_SELECT tied to VCC -> sensor address 0x69 + prompt "AMG88xx AD_SELECT value" + default SENSOR_AMG88XX_AD_SELECT_0 + ---help--- + AD SELECT sets the amg88xx i2c address + AD_SELECT tied to GND -> sensor address 0x68 + AD_SELECT tied to VCC -> sensor address 0x69 - config SENSOR_AMG88XX_AD_SELECT_0 - bool "AD_SELECT tied to GND" +config SENSOR_AMG88XX_AD_SELECT_0 + bool "AD_SELECT tied to GND" - config SENSOR_AMG88XX_AD_SELECT_1 - bool "AD_SELECT tied to VCC" +config SENSOR_AMG88XX_AD_SELECT_1 + bool "AD_SELECT tied to VCC" endchoice config SENSOR_AMG88XX_ADDR - hex - default 0x68 if SENSOR_AMG88XX_AD_SELECT_0 - default 0x69 if SENSOR_AMG88XX_AD_SELECT_1 + hex + default 0x68 if SENSOR_AMG88XX_AD_SELECT_0 + default 0x69 if SENSOR_AMG88XX_AD_SELECT_1 endif # SENSORS_AMG88XX diff --git a/fs/v9fs/Kconfig b/fs/v9fs/Kconfig index 1398f62359..3b0cba24ff 100644 --- a/fs/v9fs/Kconfig +++ b/fs/v9fs/Kconfig @@ -13,8 +13,8 @@ config FS_V9FS if FS_V9FS config V9FS_DEFAULT_MSIZE - int "V9FS Default message max size" - default 65536 + int "V9FS Default message max size" + default 65536 config V9FS_VIRTIO_9P bool "Virtio 9P support" diff --git a/sched/Kconfig b/sched/Kconfig index dce434f608..9ca5496a70 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -1979,7 +1979,7 @@ config PID_INITIAL_COUNT config SCHED_EVENTS bool "Schedule Event objects" default n - help - This option enables event objects. Threads may wait on event - objects for specific events, but both threads and ISRs may deliver - events to event objects. + ---help--- + This option enables event objects. Threads may wait on event + objects for specific events, but both threads and ISRs may deliver + events to event objects.