Add GPIO header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2691 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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196
arch/arm/src/lpc17xx/lpc17_gpio.h
Executable file
196
arch/arm/src/lpc17xx/lpc17_gpio.h
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/************************************************************************************
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* arch/arm/src/lpc17xx/lpc17_gpio.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H
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#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lp17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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/* GPIO block register offsets ******************************************************/
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#define LPC17_FIO0_OFFSET 0x0000
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#define LPC17_FIO1_OFFSET 0x0020
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#define LPC17_FIO2_OFFSET 0x0040
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#define LPC17_FIO3_OFFSET 0x0060
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#define LPC17_FIO4_OFFSET 0x0080
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#define LPC17_FIO_DIR_OFFSET 0x0000 /* Fast GPIO Port Direction control */
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#define LPC17_FIO_MASK_OFFSET 0x0010 /* Fast Mask register for ports */
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#define LPC17_FIO_PIN_OFFSET 0x0014 /* Fast Port Pin value registers */
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#define LPC17_FIO_SET_OFFSET 0x0018 /* Fast Port Output Set registers */
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#define LPC17_FIO_CLR_OFFSET 0x001c /* Fast Port Output Clear register */
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/* GPIO interrupt block register offsets ********************************************/
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#define LPC17_GPIOINT(n) (0x10*(n) + 0x80)
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#define LPC17_GPIOINT0_OFFSET 0x0080
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#define LPC17_GPIOINT2_OFFSET 0x00a0
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#define LPC17_GPIOINT_IOINTSTATUS_OFFSET 0x0000 /* GPIO overall Interrupt Status */
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#define LPC17_GPIOINT_INTSTATR_OFFSET 0x0004 /* GPIO Interrupt Status Rising edge */
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#define LPC17_GPIOINT_INTSTATF_OFFSET 0x0008 /* GPIO Interrupt Status Falling edge */
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#define LPC17_GPIOINT_INTCLR_OFFSET 0x000c /* GPIO Interrupt Clear */
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#define LPC17_GPIOINT_INTENR_OFFSET 0x0010 /* GPIO Interrupt Enable Rising edge */
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#define LPC17_GPIOINT_INTENF_OFFSET 0x0014 /* GPIO Interrupt Enable Falling edge */
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/* Register addresses ***************************************************************/
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/* GPIO block register addresses ****************************************************/
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#define LPC17X_FIO_BASE(n) (LPC17X_GPIO_BASE+LPC17_GPIOINT(n))
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#define LPC17X_FIO0_BASE (LPC17X_GPIO_BASE+LPC17_FIO0_OFFSET)
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#define LPC17X_FIO1_BASE (LPC17X_GPIO_BASE+LPC17_FIO1_OFFSET)
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#define LPC17X_FIO2_BASE (LPC17X_GPIO_BASE+LPC17_FIO2_OFFSET)
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#define LPC17X_FIO3_BASE (LPC17X_GPIO_BASE+LPC17_FIO3_OFFSET)
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#define LPC17X_FIO4_BASE (LPC17X_GPIO_BASE+LPC17_FIO4_OFFSET)
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#define LPC17_FIO_DIR(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO_MASK(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO_PIN(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO_SET(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO_CLR(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO0_DIR (LPC17X_FIO0_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO0_MASK (LPC17X_FIO0_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO0_PIN (LPC17X_FIO0_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO0_SET (LPC17X_FIO0_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO0_CLR (LPC17X_FIO0_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO1_DIR (LPC17X_FIO1_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO1_MASK (LPC17X_FIO1_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO1_PIN (LPC17X_FIO1_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO1_SET (LPC17X_FIO1_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO1_CLR (LPC17X_FIO1_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO2_DIR (LPC17X_FIO2_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO2_MASK (LPC17X_FIO2_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO2_PIN (LPC17X_FIO2_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO2_SET (LPC17X_FIO2_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO2_CLR (LPC17X_FIO2_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO3_DIR (LPC17X_FIO3_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO3_MASK (LPC17X_FIO3_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO3_PIN (LPC17X_FIO3_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO3_SET (LPC17X_FIO3_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO3_CLR (LPC17X_FIO3_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO4_DIR (LPC17X_FIO4_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO4_MASK (LPC17X_FIO4_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO4_PIN (LPC17X_FIO4_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO4_SET (LPC17X_FIO4_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO4_CLR (LPC17X_FIO4_BASE+LPC17_FIO_CLR_OFFSET)
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/* GPIO interrupt block register addresses ******************************************/
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#define LPC17_GPIOINT(n) (0x10*(n) + 0x80)
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#define LPC17_GPIOINT0_OFFSET 0x0080
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#define LPC17_GPIOINT2_OFFSET 0x00a0
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#define LPC17_GPIOINT_IOINTSTATUS (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_IOINTSTATUS_OFFSET)
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#define LPC17_GPIOINT_INTSTATR(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTSTATR_OFFSET)
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#define LPC17_GPIOINT_INTSTATF(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTSTATF_OFFSET)
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#define LPC17_GPIOINT_INTCLR(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTCLR_OFFSET)
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#define LPC17_GPIOINT_INTENR(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTENR_OFFSET)
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#define LPC17_GPIOINT_INTENF(n) (LPC17_GPIOINT(n)+LPC17_GPIOINT_INTENF_OFFSET)
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/* Pins P0.0-31 (P0.12-14 nad P0.31 are reserved) */
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#define LPC17_GPIOINT0_INTSTATR (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTSTATR_OFFSET)
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#define LPC17_GPIOINT0_INTSTATF (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTSTATF_OFFSET)
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#define LPC17_GPIOINT0_INTCLR (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTCLR_OFFSET)
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#define LPC17_GPIOINT0_INTENR (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTENR_OFFSET)
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#define LPC17_GPIOINT0_INTENF (LPC17_GPIOINT0_OFFSET+LPC17_GPIOINT_INTENF_OFFSET)
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/* Pins P2.0-13 (P0.14-31 are reserved) */
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#define LPC17_GPIOINT2_INTSTATR (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTSTATR_OFFSET)
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#define LPC17_GPIOINT2_INTSTATF (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTSTATF_OFFSET)
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#define LPC17_GPIOINT2_INTCLR (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTCLR_OFFSET)
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#define LPC17_GPIOINT2_INTENR (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTENR_OFFSET)
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#define LPC17_GPIOINT2_INTENF (LPC17_GPIOINT2_OFFSET+LPC17_GPIOINT_INTENF_OFFSET)
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/* Register bit definitions *********************************************************/
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/* GPIO block register bit definitions **********************************************/
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/* Fast GPIO Port Direction control registers (FIODIR) */
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/* Fast Mask register for ports (FIOMASK) */
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/* Fast Port Pin value registers using FIOMASK (FIOPIN) */
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/* Fast Port Output Set registers using FIOMASK (FIOSET) */
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/* Fast Port Output Clear register using FIOMASK (FIOCLR) */
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#define FIO(n) (1 << (n)) /* n=0,1,..31 */
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/* GPIO interrupt block register bit definitions ************************************/
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/* GPIO overall Interrupt Status (IOINTSTATUS) */
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#define GPIOINT_IOINTSTATUS_P0INT (1 << 0) /* Bit 0: Port 0 GPIO interrupt pending */
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/* Bit 1: Reserved */
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#define GPIOINT_IOINTSTATUS_P2INT (1 << 2) /* Bit 2: Port 2 GPIO interrupt pending */
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/* Bits 3-31: Reserved */
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/* GPIO Interrupt Status for Rising edge (INTSTATR)
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* GPIO Interrupt Status for Falling edge (INTSTATF)
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* GPIO Interrupt Clear (INTCLR)
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* GPIO Interrupt Enable for Rising edge (INTENR)
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* GPIO Interrupt Enable for Falling edge (INTENF)
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*/
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#define GPIOINT(n) (1 << (n)) /* n=0,1,..31 */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */
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