Get MAC address from USER registers
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1810 42af7a65-404d-4744-a932-0658087f49c3
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#include "lm3s_syscontrol.h" /* System control module */
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#include "lm3s_gpio.h" /* GPIO module */
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#include "lm3s_uart.h" /* UART peripherals */
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#include "lm3s_ethernet.h" /* Ethernet MAC and PHY */
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#include "lm3s_flash.h" /* FLASH */
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/************************************************************************************
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* Definitions
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129
arch/arm/src/lm3s/lm3s_flash.h
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129
arch/arm/src/lm3s/lm3s_flash.h
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/************************************************************************************
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* arch/arm/src/lm3s/lm3s_flash.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LM3S_LM3S_FLASH_H
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#define __ARCH_ARM_SRC_LM3S_LM3S_FLASH_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* FLASH register offsets ***********************************************************/
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/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
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* control base address of LM3S_FLASHCON_BASE.
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*/
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#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
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#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
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#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
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#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
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#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
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#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */
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/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
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* System Control base address of LM3S_SYSCON_BASE
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*/
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#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
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#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
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#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
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#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
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#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
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#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
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#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
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#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
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#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
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#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
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#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
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#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
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#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
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#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
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/* FLASH register addresses *********************************************************/
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/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
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* control base address of LM3S_FLASHCON_BASE.
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*/
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#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
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#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
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#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
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#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
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#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
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#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
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/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
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* System Control base address of LM3S_SYSCON_BASE
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*/
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#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
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#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
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#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
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#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
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#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
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#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
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#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
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#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
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#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
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#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
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#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
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#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
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#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
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#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
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/* FLASH register bit defitiions ****************************************************/
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/* To be provided */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LM3S_LM3S_FLASH_H */
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