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stm32/stm32_adc.c: add an option to configure SCAN mode for ADC IPv1

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This commit is contained in:
raiden00pl 2021-03-01 21:43:25 +01:00 committed by Alan Carvalho de Assis
parent e10a6647e9
commit 58a03302d2
2 changed files with 49 additions and 2 deletions
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18
arch/arm/src/stm32/Kconfig
View File

@ -8185,6 +8185,12 @@ config STM32_ADC1_DMA
DMA transfer, which is necessary if multiple channels are read
or if very high trigger frequencies are used.
config STM32_ADC1_SCAN
bool "ADC1 scan mode"
depends on STM32_ADC1 && STM32_HAVE_IP_ADC_V1
default y if STM32_ADC1_DMA
default n
config STM32_ADC1_DMA_CFG
int "ADC1 DMA configuration"
depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC
@ -8202,6 +8208,12 @@ config STM32_ADC2_DMA
DMA transfer, which is necessary if multiple channels are read
or if very high trigger frequencies are used.
config STM32_ADC2_SCAN
bool "ADC2 scan mode"
depends on STM32_ADC2 && STM32_HAVE_IP_ADC_V1
default y if STM32_ADC2_DMA
default n
config STM32_ADC2_DMA_CFG
int "ADC2 DMA configuration"
depends on STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC
@ -8219,6 +8231,12 @@ config STM32_ADC3_DMA
DMA transfer, which is necessary if multiple channels are read
or if very high trigger frequencies are used.
config STM32_ADC3_SCAN
bool "ADC3 scan mode"
depends on STM32_ADC3 && STM32_HAVE_IP_ADC_V1
default y if STM32_ADC3_DMA
default n
config STM32_ADC3_DMA_CFG
int "ADC3 DMA configuration"
depends on STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC

33
arch/arm/src/stm32/stm32_adc.c
View File

@ -350,6 +350,23 @@
# undef ADC_HAVE_DMACFG
#endif
/* ADC scan mode support - only for ADCv1 */
#ifdef CONFIG_STM32_HAVE_IP_ADC_V1
# define ADC_HAVE_SCAN 1
# ifndef CONFIG_STM32_ADC1_SCAN
# define CONFIG_STM32_ADC1_SCAN 0
# endif
# ifndef CONFIG_STM32_ADC2_SCAN
# define CONFIG_STM32_ADC2_SCAN 0
# endif
# ifndef CONFIG_STM32_ADC3_SCAN
# define CONFIG_STM32_ADC3_SCAN 0
# endif
#else
# undef ADC_HAVE_SCAN
#endif
/* We have to support ADC callbacks if default ADC interrupts or
* DMA transfer are enabled
*/
@ -409,6 +426,9 @@ struct stm32_dev_s
# endif
bool hasdma; /* True: This channel supports DMA */
#endif
#ifdef ADC_HAVE_SCAN
bool scan; /* True: Scan mode */
#endif
#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME
/* Sample time selection. These bits must be written only when ADON=0.
* REVISIT: this takes too much space. We need only 3 bits per channel.
@ -769,6 +789,9 @@ static struct stm32_dev_s g_adcpriv1 =
# endif
.hasdma = true,
#endif
#ifdef ADC_HAVE_SCAN
.scan = CONFIG_STM32_ADC1_SCAN,
#endif
};
static struct adc_dev_s g_adcdev1 =
@ -825,6 +848,9 @@ static struct stm32_dev_s g_adcpriv2 =
# endif
.hasdma = true,
#endif
#ifdef ADC_HAVE_SCAN
.scan = CONFIG_STM32_ADC2_SCAN,
#endif
};
static struct adc_dev_s g_adcdev2 =
@ -881,6 +907,9 @@ static struct stm32_dev_s g_adcpriv3 =
# endif
.hasdma = true,
#endif
#ifdef ADC_HAVE_SCAN
.scan = CONFIG_STM32_ADC3_SCAN,
#endif
};
static struct adc_dev_s g_adcdev3 =
@ -2401,8 +2430,8 @@ static void adc_mode_cfg(FAR struct stm32_dev_s *priv)
setbits |= ADC_CR1_IND;
#endif
#ifdef ADC_HAVE_DMA
if (priv->hasdma)
#ifdef ADC_HAVE_SCAN
if (priv->scan == true)
{
setbits |= ADC_CR1_SCAN;
}