From 58bd8737297efcf5c6f4f8961c88e86a3d5113c7 Mon Sep 17 00:00:00 2001
From: Lei Chen <lchen@bouffalolab.com>
Date: Thu, 17 Dec 2020 19:04:46 +0800
Subject: [PATCH] Add Basic support for BL602(UART timer CLIC)
---
arch/risc-v/Kconfig | 11 +-
arch/risc-v/include/bl602/chip.h | 36 +
arch/risc-v/include/bl602/irq.h | 242 +
arch/risc-v/src/bl602/Kconfig | 79 +
arch/risc-v/src/bl602/Make.defs | 59 +
arch/risc-v/src/bl602/bl602_allocateheap.c | 65 +
arch/risc-v/src/bl602/bl602_boot2.h | 172 +
arch/risc-v/src/bl602/bl602_config.h | 54 +
arch/risc-v/src/bl602/bl602_entry.S | 176 +
arch/risc-v/src/bl602/bl602_glb.c | 138 +
arch/risc-v/src/bl602/bl602_gpio.c | 184 +
arch/risc-v/src/bl602/bl602_hbn.c | 100 +
arch/risc-v/src/bl602/bl602_head.S | 162 +
arch/risc-v/src/bl602/bl602_idle.c | 67 +
arch/risc-v/src/bl602/bl602_irq.c | 253 +
arch/risc-v/src/bl602/bl602_irq_dispatch.c | 105 +
arch/risc-v/src/bl602/bl602_lowputc.c | 434 ++
arch/risc-v/src/bl602/bl602_lowputc.h | 73 +
.../src/bl602/bl602_oneshot_lowerhalf.c | 416 ++
.../src/bl602/bl602_oneshot_lowerhalf.h | 212 +
.../src/bl602/bl602_schedulesigaction.c | 195 +
arch/risc-v/src/bl602/bl602_serial.c | 984 +++
arch/risc-v/src/bl602/bl602_start.c | 142 +
arch/risc-v/src/bl602/bl602_tim.c | 802 +++
arch/risc-v/src/bl602/bl602_tim_lowerhalf.c | 447 ++
arch/risc-v/src/bl602/bl602_tim_lowerhalf.h | 38 +
arch/risc-v/src/bl602/bl602_timerisr.c | 156 +
arch/risc-v/src/bl602/bl602_vectors.S | 42 +
arch/risc-v/src/bl602/chip.h | 36 +
arch/risc-v/src/bl602/hardware/bl602_common.h | 231 +
arch/risc-v/src/bl602/hardware/bl602_glb.h | 5836 +++++++++++++++++
arch/risc-v/src/bl602/hardware/bl602_gpio.h | 507 ++
arch/risc-v/src/bl602/hardware/bl602_hbn.h | 1024 +++
arch/risc-v/src/bl602/hardware/bl602_timer.h | 664 ++
arch/risc-v/src/bl602/hardware/bl602_uart.h | 1010 +++
arch/risc-v/src/bl602/hardware/clic.h | 43 +
boards/Kconfig | 11 +
boards/risc-v/bl602/bl602evb/Kconfig | 8 +
boards/risc-v/bl602/bl602evb/README.txt | 28 +
.../bl602/bl602evb/configs/demo/defconfig | 1242 ++++
.../bl602/bl602evb/configs/nsh/defconfig | 75 +
boards/risc-v/bl602/bl602evb/include/board.h | 68 +
.../risc-v/bl602/bl602evb/scripts/Make.defs | 89 +
.../risc-v/bl602/bl602evb/scripts/ld.script | 279 +
boards/risc-v/bl602/bl602evb/src/Makefile | 29 +
.../risc-v/bl602/bl602evb/src/bl602_appinit.c | 69 +
boards/risc-v/bl602/bl602evb/src/bl602_boot.c | 64 +
.../risc-v/bl602/bl602evb/src/bl602_bringup.c | 113 +
boards/risc-v/bl602/bl602evb/src/bl602evb.h | 32 +
49 files changed, 17301 insertions(+), 1 deletion(-)
create mode 100644 arch/risc-v/include/bl602/chip.h
create mode 100644 arch/risc-v/include/bl602/irq.h
create mode 100644 arch/risc-v/src/bl602/Kconfig
create mode 100644 arch/risc-v/src/bl602/Make.defs
create mode 100644 arch/risc-v/src/bl602/bl602_allocateheap.c
create mode 100644 arch/risc-v/src/bl602/bl602_boot2.h
create mode 100644 arch/risc-v/src/bl602/bl602_config.h
create mode 100644 arch/risc-v/src/bl602/bl602_entry.S
create mode 100644 arch/risc-v/src/bl602/bl602_glb.c
create mode 100644 arch/risc-v/src/bl602/bl602_gpio.c
create mode 100644 arch/risc-v/src/bl602/bl602_hbn.c
create mode 100644 arch/risc-v/src/bl602/bl602_head.S
create mode 100644 arch/risc-v/src/bl602/bl602_idle.c
create mode 100644 arch/risc-v/src/bl602/bl602_irq.c
create mode 100644 arch/risc-v/src/bl602/bl602_irq_dispatch.c
create mode 100644 arch/risc-v/src/bl602/bl602_lowputc.c
create mode 100644 arch/risc-v/src/bl602/bl602_lowputc.h
create mode 100644 arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
create mode 100644 arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h
create mode 100644 arch/risc-v/src/bl602/bl602_schedulesigaction.c
create mode 100644 arch/risc-v/src/bl602/bl602_serial.c
create mode 100644 arch/risc-v/src/bl602/bl602_start.c
create mode 100644 arch/risc-v/src/bl602/bl602_tim.c
create mode 100644 arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
create mode 100644 arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
create mode 100644 arch/risc-v/src/bl602/bl602_timerisr.c
create mode 100644 arch/risc-v/src/bl602/bl602_vectors.S
create mode 100644 arch/risc-v/src/bl602/chip.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_common.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_glb.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_gpio.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_hbn.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_timer.h
create mode 100644 arch/risc-v/src/bl602/hardware/bl602_uart.h
create mode 100644 arch/risc-v/src/bl602/hardware/clic.h
create mode 100644 boards/risc-v/bl602/bl602evb/Kconfig
create mode 100644 boards/risc-v/bl602/bl602evb/README.txt
create mode 100644 boards/risc-v/bl602/bl602evb/configs/demo/defconfig
create mode 100644 boards/risc-v/bl602/bl602evb/configs/nsh/defconfig
create mode 100644 boards/risc-v/bl602/bl602evb/include/board.h
create mode 100644 boards/risc-v/bl602/bl602evb/scripts/Make.defs
create mode 100644 boards/risc-v/bl602/bl602evb/scripts/ld.script
create mode 100644 boards/risc-v/bl602/bl602evb/src/Makefile
create mode 100644 boards/risc-v/bl602/bl602evb/src/bl602_appinit.c
create mode 100644 boards/risc-v/bl602/bl602evb/src/bl602_boot.c
create mode 100644 boards/risc-v/bl602/bl602evb/src/bl602_bringup.c
create mode 100644 boards/risc-v/bl602/bl602evb/src/bl602evb.h
diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig
index 4617062f72..87e63f878e 100644
--- a/arch/risc-v/Kconfig
+++ b/arch/risc-v/Kconfig
@@ -44,6 +44,12 @@ config ARCH_CHIP_GAP8
GreenwavesTechnologies GAP8 features a 1+8-core RI5CY DSP-like
processor, which originally comes from the ETH PULP platform.
+config ARCH_CHIP_BL602
+ bool "BouffaloLab BL602"
+ select ARCH_RV32IM
+ ---help---
+ BouffaloLab BL602(rv32imfc)
+
config ARCH_CHIP_RISCV_CUSTOM
bool "Custom RISC-V chip"
select ARCH_CHIP_CUSTOM
@@ -80,6 +86,7 @@ config ARCH_CHIP
default "litex" if ARCH_CHIP_LITEX
default "nr5m100" if ARCH_CHIP_NR5
default "gap8" if ARCH_CHIP_GAP8
+ default "bl602" if ARCH_CHIP_BL602
config NR5_MPU
bool "MPU support"
@@ -112,5 +119,7 @@ endif
if ARCH_CHIP_GAP8
source arch/risc-v/src/gap8/Kconfig
endif
-
+if ARCH_CHIP_BL602
+source arch/risc-v/src/bl602/Kconfig
+endif
endif
diff --git a/arch/risc-v/include/bl602/chip.h b/arch/risc-v/include/bl602/chip.h
new file mode 100644
index 0000000000..e428757bde
--- /dev/null
+++ b/arch/risc-v/include/bl602/chip.h
@@ -0,0 +1,36 @@
+/****************************************************************************
+ * arch/risc-v/include/bl602/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_BL602_CHIP_H
+#define __ARCH_RISCV_INCLUDE_BL602_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <arch/irq.h>
+#include "riscv_internal.h"
+
+#endif /* __ARCH_RISCV_INCLUDE_BL602_CHIP_H */
diff --git a/arch/risc-v/include/bl602/irq.h b/arch/risc-v/include/bl602/irq.h
new file mode 100644
index 0000000000..b6eb9a1e69
--- /dev/null
+++ b/arch/risc-v/include/bl602/irq.h
@@ -0,0 +1,242 @@
+/****************************************************************************
+ * arch/risc-v/include/bl602/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_BL602_IRQ_H
+#define __ARCH_RISCV_INCLUDE_BL602_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <arch/irq.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* CLINT Base Address */
+
+#define CLIC_TIMER_ENABLE_ADDRESS (0x02800407)
+
+/* In mstatus register */
+
+#define MIE_MSIE (0x1 << 3) /* Machine Software Interrupt Enable */
+
+/* Map RISC-V exception code to NuttX IRQ */
+
+/* IRQ 0-15 : (exception:interrupt=0) */
+
+#define BL602_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
+#define BL602_IRQ_IAFAULT (1) /* Instruction Address Fault */
+#define BL602_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
+#define BL602_IRQ_BPOINT (3) /* Break Point */
+#define BL602_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
+#define BL602_IRQ_LAFAULT (5) /* Load Access Fault */
+#define BL602_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
+#define BL602_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
+#define BL602_IRQ_ECALLU (8) /* Environment Call from U-mode */
+ /* 9-10: Reserved */
+
+#define BL602_IRQ_ECALLM (11) /* Environment Call from M-mode */
+ /* 12-15: Reserved */
+
+/* IRQ 16- : (async event:interrupt=1) */
+
+#define BL602_IRQ_NUM_BASE (16)
+#define BL602_IRQ_ASYNC (16)
+#define BL602_IRQ_MSOFT (BL602_IRQ_ASYNC + 3) /* Machine Software Int */
+#define BL602_IRQ_MTIMER (BL602_IRQ_ASYNC + 7) /* Machine Timer Int */
+#define BL602_IRQ_MEXT (BL602_IRQ_ASYNC + 11) /* Machine External Int */
+
+/* Machine Global External Interrupt */
+
+#define BL602_IRQ_BMX_ERR \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 0) /* BMX Error Interrupt */
+#define BL602_IRQ_BMX_TO \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 1) /* BMX Timeout Interrupt */
+#define BL602_IRQ_L1C_BMX_ERR \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 2) /* L1C BMX Error Interrupt */
+#define BL602_IRQ_L1C_BMX_TO \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 3) /* L1C BMX Timeout Interrupt */
+#define BL602_IRQ_SEC_BMX_ERR \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 4) /* SEC BMX Error Interrupt */
+#define BL602_IRQ_RF_TOP_INT0 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 5) /* RF_TOP_INT0 Interrupt */
+#define BL602_IRQ_RF_TOP_INT1 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 6) /* RF_TOP_INT1 Interrupt */
+#define BL602_IRQ_SDIO \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 7) /* SDIO Interrupt */
+#define BL602_IRQ_DMA_BMX_ERR \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 8) /* DMA BMX Error Interrupt */
+#define BL602_IRQ_SEC_GMAC \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 9) /* SEC_ENG_GMAC_INT Interrupt */
+#define BL602_IRQ_SEC_CDET \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 10) /* SEC_ENG_CDET_INT Interrupt */
+#define BL602_IRQ_SEC_PKA \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 11) /* SEC_ENG_PKA_INT Interrupt */
+#define BL602_IRQ_SEC_TRNG \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 12) /* SEC_ENG_TRNG_INT Interrupt */
+#define BL602_IRQ_SEC_AES \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 13) /* SEC_ENG_AES_INT Interrupt */
+#define BL602_IRQ_SEC_SHA \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 14) /* SEC_ENG_SHA_INT Interrupt */
+#define BL602_IRQ_DMA_ALL \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 15) /* DMA ALL Interrupt */
+#define BL602_IRQ_RESERVED0 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 16) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED1 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 17) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED2 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 18) /* RESERVED Interrupt */
+#define BL602_IRQ_IRTX_IRQn \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 19) /* IR TX Interrupt */
+#define BL602_IRQ_IRRX_IRQn \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 20) /* IR RX Interrupt */
+#define BL602_IRQ_RESERVED3 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 21) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED4 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 22) /* RESERVED Interrupt */
+#define BL602_IRQ_SF_CTRL \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 23) /* SF_CTRL Interrupt */
+#define BL602_IRQ_RESERVED5 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 24) /* RESERVED Interrupt */
+#define BL602_IRQ_GPADC_DMA \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 25) /* GPADC_DMA Interrupt */
+#define BL602_IRQ_EFUSE \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 26) /* Efuse Interrupt */
+#define BL602_IRQ_SPI \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 27) /* SPI Interrupt */
+#define BL602_IRQ_RESERVED6 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 28) /* RESERVED Interrupt */
+#define BL602_IRQ_UART0 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 29) /* UART Interrupt */
+#define BL602_IRQ_UART1 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 30) /* UART1 Interrupt */
+#define BL602_IRQ_RESERVED7 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 31) /* RESERVED Interrupt */
+#define BL602_IRQ_I2C \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 32) /* I2C Interrupt */
+#define BL602_IRQ_RESERVED8 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 33) /* RESERVED Interrupt */
+#define BL602_IRQ_PWM \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 34) /* PWM Interrupt */
+#define BL602_IRQ_RESERVED9 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 35) /* RESERVED Interrupt */
+#define BL602_IRQ_TIMER_CH0 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 36) /* Timer Channel 0 Interrupt */
+#define BL602_IRQ_TIMER_CH1 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 37) /* Timer Channel 1 Interrupt */
+#define BL602_IRQ_TIMER_WDT \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 38) /* Timer Watch Dog Interrupt */
+#define BL602_IRQ_RESERVED10 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 39) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED11 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 40) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED12 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 41) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED13 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 42) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED14 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 43) /* RESERVED Interrupt */
+#define BL602_IRQ_GPIO_INT0 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 44) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED16 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 45) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED17 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 46) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED18 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 47) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED19 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 48) /* RESERVED Interrupt */
+#define BL602_IRQ_RESERVED20 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 49) /* RESERVED Interrupt */
+#define BL602_IRQ_PDS_WAKEUP \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 50) /* PDS Wakeup Interrupt */
+#define BL602_IRQ_HBN_OUT0 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 51) /* Hibernate out 0 Interrupt */
+#define BL602_IRQ_HBN_OUT1 \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 52) /* Hibernate out 1 Interrupt */
+#define BL602_IRQ_BOR \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 53) /* BOR Interrupt */
+#define BL602_IRQ_WIFI \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 54) /* WIFI To CPU Interrupt */
+#define BL602_IRQ_BZ_PHY \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 55) /* RESERVED Interrupt */
+#define BL602_IRQ_BLE \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 56) /* RESERVED Interrupt */
+#define BL602_IRQ_MAC_TXRX_TIMER \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
+ 57) /* mac_int_tx_rx_timer Interrupt */
+#define BL602_IRQ_MAC_TXRX_MISC \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
+ 58) /* mac_int_tx_rx_misc Interrupt */
+#define BL602_IRQ_MAC_RX_TRG \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
+ 59) /* mac_int_rx_trigger Interrupt */
+#define BL602_IRQ_MAC_TX_TRG \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
+ 60) /* mac_int_tx_trigger Interrupt */
+#define BL602_IRQ_MAC_GEN \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 61) /* mac_int_gen Interrupt */
+#define BL602_IRQ_MAC_PORT_TRG \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + \
+ 62) /* mac_int_port_trigger Interrupt */
+#define BL602_IRQ_WIFI_IPC_PUBLIC \
+ (BL602_IRQ_ASYNC + BL602_IRQ_NUM_BASE + 63) /* wifi IPC public Interrupt */
+
+/* Total number of IRQs */
+
+#define NR_IRQS (64 + 16)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+EXTERN irqstate_t up_irq_save(void);
+EXTERN void up_irq_restore(irqstate_t);
+EXTERN irqstate_t up_irq_enable(void);
+EXTERN void up_disable_irq(int irq);
+EXTERN void up_enable_irq(int irq);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_INCLUDE_BL602_IRQ_H */
diff --git a/arch/risc-v/src/bl602/Kconfig b/arch/risc-v/src/bl602/Kconfig
new file mode 100644
index 0000000000..d7d60e0144
--- /dev/null
+++ b/arch/risc-v/src/bl602/Kconfig
@@ -0,0 +1,79 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+comment "BL602 Configuration Options"
+
+menu "BL602 Peripheral Support"
+
+config BL602_HAVE_UART0
+ bool
+ default y
+ select UART0_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+
+config BL602_UART0
+ bool "UART0"
+ default y
+ select ARCH_HAVE_UART0
+
+config BL602_UART0_TX_PIN
+ int "UART0 tx pin num"
+ default 16
+ depends on BL602_UART0
+
+config BL602_UART0_RX_PIN
+ int "UART0 rx pin num"
+ default 7
+ depends on BL602_UART0
+
+config BL602_UART0_RTS_PIN
+ int "UART0 rts pin num"
+ default -1
+ depends on BL602_UART0
+
+config BL602_UART0_CTS_PIN
+ int "UART0 cts pin num"
+ default -1
+ depends on BL602_UART0
+
+config BL602_HAVE_UART1
+ bool
+ default y
+ select UART1_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+
+config BL602_UART1
+ bool "UART1"
+ default y
+ select ARCH_HAVE_UART1
+
+config BL602_UART1_TX_PIN
+ int "UART1 tx pin num"
+ default 4
+ depends on BL602_UART1
+
+config BL602_UART1_RX_PIN
+ int "UART1 rx pin num"
+ default 3
+ depends on BL602_UART1
+
+config BL602_UART1_RTS_PIN
+ int "UART1 rts pin num"
+ default -1
+ depends on BL602_UART1
+
+config BL602_UART1_CTS_PIN
+ int "UART1 cts pin num"
+ default -1
+ depends on BL602_UART1
+
+config BL602_TIMER0
+ bool "TIMER0"
+ default y
+
+config BL602_TIMER1
+ bool "TIMER1"
+ default y
+endmenu
diff --git a/arch/risc-v/src/bl602/Make.defs b/arch/risc-v/src/bl602/Make.defs
new file mode 100644
index 0000000000..37d272bfd0
--- /dev/null
+++ b/arch/risc-v/src/bl602/Make.defs
@@ -0,0 +1,59 @@
+############################################################################
+# arch/risc-v/src/bl602/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Specify our HEAD assembly file. This will be linked as
+# the first object file, so it will appear at address 0
+HEAD_ASRC = bl602_vectors.S
+
+# Specify our general Assembly files
+CHIP_ASRCS = bl602_head.S riscv_syscall.S bl602_entry.S
+
+# Specify C code within the common directory to be included
+CMN_CSRCS += riscv_initialize.c riscv_swint.c
+CMN_CSRCS += riscv_createstack.c riscv_exit.c
+CMN_CSRCS += riscv_assert.c riscv_blocktask.c riscv_copystate.c riscv_initialstate.c
+CMN_CSRCS += riscv_interruptcontext.c riscv_modifyreg32.c riscv_puts.c riscv_mdelay.c
+CMN_CSRCS += riscv_releasepending.c riscv_reprioritizertr.c
+CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c bl602_schedulesigaction.c
+CMN_CSRCS += riscv_sigdeliver.c riscv_udelay.c riscv_unblocktask.c riscv_usestack.c
+
+
+ifeq ($(CONFIG_STACK_COLORATION),y)
+CMN_CSRCS += riscv_checkstack.c
+endif
+
+ifeq ($(CONFIG_ARCH_HAVE_VFORK),y)
+CMN_CSRCS += riscv_vfork.c
+endif
+
+# Specify our C code within this directory to be included
+CHIP_CSRCS = bl602_allocateheap.c
+CHIP_CSRCS += bl602_idle.c bl602_irq.c bl602_irq_dispatch.c
+CHIP_CSRCS += bl602_serial.c bl602_lowputc.c
+CHIP_CSRCS += bl602_start.c bl602_timerisr.c
+
+ifeq ($(CONFIG_TIMER),y)
+CHIP_CSRCS += bl602_tim.c bl602_tim_lowerhalf.c bl602_oneshot_lowerhalf.c
+endif
+
+CHIP_CSRCS += bl602_glb.c bl602_gpio.c bl602_hbn.c
+
+# INCLUDES += ${shell $(INCDIR) "$(CC)" $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)hardware}
+
diff --git a/arch/risc-v/src/bl602/bl602_allocateheap.c b/arch/risc-v/src/bl602/bl602_allocateheap.c
new file mode 100644
index 0000000000..2a9c750986
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_allocateheap.c
@@ -0,0 +1,65 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_addregion
+ ****************************************************************************/
+
+void up_addregion(void)
+{
+}
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ * This function will be called to dynamically set aside the heap region.
+ *
+ * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
+ * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ * size of the unprotected, user-space heap.
+ *
+ * If a protected kernel-space heap is provided, the kernel heap must be
+ * allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ ****************************************************************************/
+
+extern uint8_t _heap_start;
+extern uint8_t _heap_size;
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+ *heap_start = (FAR void *)&_heap_start;
+ *heap_size = (size_t)&_heap_size;
+}
diff --git a/arch/risc-v/src/bl602/bl602_boot2.h b/arch/risc-v/src/bl602/bl602_boot2.h
new file mode 100644
index 0000000000..cc91ae2f2b
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_boot2.h
@@ -0,0 +1,172 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_boot2.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_BOOT2_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_BOOT2_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+/* Partition table error type definition */
+
+enum pt_table_error_e
+{
+ PT_ERROR_SUCCESS, /* Partition table error type:success */
+ PT_ERROR_TABLE_NOT_VALID, /* Partition table error type:entry not found */
+ PT_ERROR_ENTRY_NOT_FOUND, /* Partition table error type:entry not found */
+ PT_ERROR_ENTRY_UPDATE_FAIL, /* Partition table error type:entry update fail
+ */
+ PT_ERROR_CRC32, /* Partition table error type:crc32 error */
+ PT_ERROR_PARAMETER, /* Partition table error type:input parameter error */
+ PT_ERROR_FALSH_READ, /* Partition table error type:flash read error */
+ PT_ERROR_FALSH_WRITE, /* Partition table error type:flash write error */
+ PT_ERROR_FALSH_ERASE /* Partition table error type:flash erase error */
+};
+
+/* Partition id type definition */
+
+enum pt_table_id_e
+{
+ PT_TABLE_ID_0, /* Partition table ID 0 */
+ PT_TABLE_ID_1, /* Partition table ID 1 */
+ PT_TABLE_ID_INVALID, /* Partition table ID invalid */
+};
+
+/* Partition id type definition */
+
+enum pt_table_entry_type_e
+{
+ PT_ENTRY_FW_CPU0, /* Partition entry type:CPU0 firmware */
+ PT_ENTRY_FW_CPU1, /* Partition entry type:CPU1 firmware */
+ PT_ENTRY_MAX = 16, /* Partition entry type:Max */
+};
+
+/* Partition table config definition */
+
+struct pt_table_config_s
+{
+ uint32_t magic_code; /* Partition table magic code */
+ uint16_t version; /* Partition table verdion */
+ uint16_t entry_cnt; /* Partition table entry count */
+ uint32_t age; /* Partition table age */
+ uint32_t crc32; /* Partition table CRC32 value */
+};
+
+/* Partition table entry config definition */
+
+struct pt_table_entry_config_s
+{
+ uint8_t type; /* Partition entry type */
+ uint8_t device; /* Partition entry device */
+ uint8_t active_index; /* Partition entry active index */
+ uint8_t name[9]; /* Partition entry name */
+ uint32_t address[2]; /* Partition entry start address */
+ uint32_t max_len[2]; /* Partition entry max length */
+ uint32_t len; /* Partition entry length */
+ uint32_t age; /* Partition entry age */
+};
+
+/* Partition table stuff config definition */
+
+struct pt_table_stuff_config_s
+{
+ struct pt_table_config_s pt_table; /* Partition table */
+ struct pt_table_entry_config_s
+ pt_entries[PT_ENTRY_MAX]; /* Partition entries */
+ uint32_t crc32; /* Partition entries crc32 */
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: <Inline function name>
+ *
+ * Description:
+ * Description of the operation of the inline function.
+ *
+ * Input Parameters:
+ * A list of input parameters, one-per-line, appears here along with a
+ * description of each input parameter.
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: <Global function name>
+ *
+ * Description:
+ * Description of the operation of the function.
+ *
+ * Input Parameters:
+ * A list of input parameters, one-per-line, appears here along with a
+ * description of each input parameter.
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_BOOT2_H */
diff --git a/arch/risc-v/src/bl602/bl602_config.h b/arch/risc-v/src/bl602/bl602_config.h
new file mode 100644
index 0000000000..74c199c3c5
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_config.h
@@ -0,0 +1,54 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_config.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_BL602_CONFIG_H
+#define __ARCH_RISCV_SRC_BL602_BL602_CONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/chip/chip.h>
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#undef HAVE_UART_DEVICE
+#if defined(CONFIG_BL602_UART0) || defined(CONFIG_BL602_UART1)
+#define HAVE_UART_DEVICE 1
+#endif
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_BL602_UART0)
+#undef CONFIG_UART1_SERIAL_CONSOLE
+#define HAVE_SERIAL_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_BL602_UART1)
+#undef CONFIG_UART0_SERIAL_CONSOLE
+#define HAVE_SERIAL_CONSOLE 1
+#else
+#undef CONFIG_UART0_SERIAL_CONSOLE
+#undef CONFIG_UART1_SERIAL_CONSOLE
+#undef HAVE_SERIAL_CONSOLE
+#endif
+
+#endif /* __ARCH_RISCV_SRC_BL602_BL602_CONFIG_H */
diff --git a/arch/risc-v/src/bl602/bl602_entry.S b/arch/risc-v/src/bl602/bl602_entry.S
new file mode 100644
index 0000000000..f811682ff7
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_entry.S
@@ -0,0 +1,176 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_entry.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This is defined in sifive/platform.h, but that can't be included from
+ * assembly. */
+#define CLINT_CTRL_ADDR 0x02000000
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_MIE 0x00000008
+
+ .section .init
+ .globl bl602_start
+ .globl __start
+ .type bl602_start,@function
+
+__start:
+bl602_start:
+ .cfi_startproc
+ .cfi_undefined ra
+.option push
+.option norelax
+ /*disable IRQ*/
+ li t0, MSTATUS_MIE
+ csrc mstatus, t0
+
+ la gp, __global_pointer$
+.option pop
+ la sp, _sp_main
+
+
+#ifndef RUN_IN_RAM
+ /* Load boot2 partition address */
+ la a0, __boot2_pt_addr_src
+ la a1, __boot2_pt_addr_start
+ la a2, __boot2_pt_addr_end
+ bgeu a1, a2, 2f
+1:
+ lw t0, (a0)
+ sw t0, (a1)
+ addi a0, a0, 4
+ addi a1, a1, 4
+ bltu a1, a2, 1b
+2:
+
+
+ /* Load boot2 flashCfg address */
+ jal boot2_get_flash_addr
+ la a1, __boot2_flash_cfg_start
+ la a2, __boot2_flash_cfg_end
+ bgeu a1, a2, 2f
+1:
+ lw t0, (a0)
+ sw t0, (a1)
+ addi a0, a0, 4
+ addi a1, a1, 4
+ bltu a1, a2, 1b
+2:
+#endif
+
+ /* Load data section */
+ la a0, _data_load
+ la a1, _data_run
+ la a2, _data_run_end
+ bgeu a1, a2, 2f
+1:
+ lw t0, (a0)
+ sw t0, (a1)
+ addi a0, a0, 4
+ addi a1, a1, 4
+ bltu a1, a2, 1b
+2:
+
+ /* Clear bss section */
+ la a0, __bss_start
+ la a1, __bss_end
+ bgeu a0, a1, 3f
+1:
+ sw zero, (a0)
+ addi a0, a0, 4
+ bltu a0, a1, 1b
+
+ /* Clear bss section */
+ la a0, __wifi_bss_start
+ la a1, __wifi_bss_end
+ bgeu a0, a1, 3f
+1:
+ sw zero, (a0)
+ addi a0, a0, 4
+ bltu a0, a1, 1b
+
+3:
+
+ /* Call global constructors */
+#if 0
+ la a0, __libc_fini_array
+ call atexit
+ call __libc_init_array
+#endif
+
+#ifndef __riscv_float_abi_soft
+ /* Enable FPU */
+ li t0, MSTATUS_FS
+ csrs mstatus, t0
+ csrr t1, mstatus
+ and t1, t1, t0
+ beqz t1, 1f
+ fssr x0
+1:
+#endif
+
+#if defined(ENABLE_SMP)
+ smp_resume(t0, t1)
+
+ csrr a0, mhartid
+ bnez a0, 2f
+#endif
+
+ auipc ra, 0
+ addi sp, sp, -16
+#if __riscv_xlen == 32
+ sw ra, 8(sp)
+#else
+ sd ra, 8(sp)
+#endif
+
+ /* argc = argv = 0 */
+ li a0, 0
+ li a1, 0
+ call bfl_main
+#if 0
+ tail exit
+#endif
+1:
+ j 1b
+
+#if defined(ENABLE_SMP)
+2:
+ la t0, trap_entry
+ csrw mtvec, t0
+
+ csrr a0, mhartid
+ la t1, _sp_main
+ slli t0, a0, 10
+ sub sp, t1, t0
+
+ auipc ra, 0
+ addi sp, sp, -16
+#if __riscv_xlen == 32
+ sw ra, 8(sp)
+#else
+ sd ra, 8(sp)
+#endif
+
+ call secondary_main
+ tail exit
+
+1:
+ j 1b
+#endif
+ .cfi_endproc
diff --git a/arch/risc-v/src/bl602/bl602_glb.c b/arch/risc-v/src/bl602/bl602_glb.c
new file mode 100644
index 0000000000..8b876ecd87
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_glb.c
@@ -0,0 +1,138 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_glb.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hardware/bl602_glb.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: <Static function name>
+ *
+ * Description:
+ * Description of the operation of the static function.
+ *
+ * Input Parameters:
+ * A list of input parameters, one-per-line, appears here along with a
+ * description of each input parameter.
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: glb_uart_fun_sel
+ *
+ * Description:
+ * Select UART signal function.
+ *
+ * Input Parameters:
+ * sig: UART signal
+ * fun: UART function
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun)
+{
+ uint32_t sig_pos = 0;
+ uint32_t tmp_val = 0;
+
+ tmp_val = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0);
+ sig_pos = (sig * 4);
+
+ /* Clear original val */
+
+ tmp_val = tmp_val & (~(0xf << sig_pos));
+
+ /* Set new value */
+
+ tmp_val = tmp_val | (fun << sig_pos);
+ BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmp_val);
+}
+
+/****************************************************************************
+ * Name: glb_ahb_slave1_reset
+ *
+ * Description:
+ * Select UART signal function.
+ *
+ * Input Parameters:
+ * sig: UART signal
+ * fun: UART function
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void glb_ahb_slave1_reset(enum bl_ahb_slave1_e slave1)
+{
+ uint32_t tmp_val = 0;
+
+ tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+ tmp_val &= (~(1 << slave1));
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
+ BL_DRV_DUMMY;
+ tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+ tmp_val |= (1 << slave1);
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
+ BL_DRV_DUMMY;
+ tmp_val = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+ tmp_val &= (~(1 << slave1));
+ BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmp_val);
+}
+
diff --git a/arch/risc-v/src/bl602/bl602_gpio.c b/arch/risc-v/src/bl602/bl602_gpio.c
new file mode 100644
index 0000000000..116931aaaa
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_gpio.c
@@ -0,0 +1,184 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+#include "hardware/bl602_gpio.h"
+#include "hardware/bl602_glb.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: <Static function name>
+ *
+ * Description:
+ * Description of the operation of the static function.
+ *
+ * Input Parameters:
+ * A list of input parameters, one-per-line, appears here along with a
+ * description of each input parameter.
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: gpio_init
+ *
+ * Description:
+ * Init a gpio pin.
+ *
+ * Input Parameters:
+ * cfg: gpio configuration
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+void gpio_init(struct gpio_cfg_s *cfg)
+{
+ uint8_t gpio_pin = cfg->gpio_pin;
+ uint32_t *p_out;
+ uint32_t pos;
+ uint32_t tmp_out;
+ uint32_t tmp_val;
+
+ p_out = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET +
+ ((gpio_pin >> 5) << 2));
+ pos = gpio_pin % 32;
+ tmp_out = *p_out;
+
+ /* Disable output anyway */
+
+ tmp_out &= (~(1 << pos));
+ *p_out = tmp_out;
+
+ tmp_val = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4);
+
+ if (gpio_pin % 2 == 0)
+ {
+ /* Set input or output */
+
+ if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
+ {
+ tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE);
+ tmp_out |= (1 << pos);
+ }
+ else
+ {
+ tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_IE);
+ }
+
+ /* Set pull up or down */
+
+ tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU);
+ tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD);
+ if (cfg->pull_type == GPIO_PULL_UP)
+ {
+ tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PU);
+ }
+ else if (cfg->pull_type == GPIO_PULL_DOWN)
+ {
+ tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_0_PD);
+ }
+
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_DRV, cfg->drive);
+ tmp_val =
+ BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_SMT, cfg->smt_ctrl);
+ tmp_val =
+ BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpio_fun);
+ }
+ else
+ {
+ /* Set input or output */
+
+ if (cfg->gpio_mode == GPIO_MODE_OUTPUT)
+ {
+ tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE);
+ tmp_out |= (1 << pos);
+ }
+ else
+ {
+ tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_IE);
+ }
+
+ /* Set pull up or down */
+
+ tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU);
+ tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD);
+ if (cfg->pull_type == GPIO_PULL_UP)
+ {
+ tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PU);
+ }
+ else if (cfg->pull_type == GPIO_PULL_DOWN)
+ {
+ tmp_val = BL_SET_REG_BIT(tmp_val, GLB_REG_GPIO_1_PD);
+ }
+
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_DRV, cfg->drive);
+ tmp_val =
+ BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_SMT, cfg->smt_ctrl);
+ tmp_val =
+ BL_SET_REG_BITS_VAL(tmp_val, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpio_fun);
+ }
+
+ BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpio_pin / 2 * 4, tmp_val);
+
+ *p_out = tmp_out;
+}
diff --git a/arch/risc-v/src/bl602/bl602_hbn.c b/arch/risc-v/src/bl602/bl602_hbn.c
new file mode 100644
index 0000000000..f81a4add78
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_hbn.c
@@ -0,0 +1,100 @@
+/****************************************************************************
+ * <Relative path to the file>
+ * <Optional one line file description>
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hardware/bl602_hbn.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: <Static function name>
+ *
+ * Description:
+ * Description of the operation of the static function.
+ *
+ * Input Parameters:
+ * A list of input parameters, one-per-line, appears here along with a
+ * description of each input parameter.
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: hbn_set_uart_clk_sel
+ *
+ * Description:
+ * Select uart clock source.
+ *
+ * Input Parameters:
+ * clk_sel: uart clock type selection
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+void hbn_set_uart_clk_sel(enum hbn_uart_clk_type_e clk_sel)
+{
+ uint32_t tmp_val;
+
+ tmp_val = BL_RD_REG(HBN_BASE, HBN_GLB);
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_UART_CLK_SEL, clk_sel);
+ BL_WR_REG(HBN_BASE, HBN_GLB, tmp_val);
+}
diff --git a/arch/risc-v/src/bl602/bl602_head.S b/arch/risc-v/src/bl602/bl602_head.S
new file mode 100644
index 0000000000..33b1703782
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_head.S
@@ -0,0 +1,162 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_head.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/rv32im/irq.h>
+
+/****************************************************************************
+ * Public Symbols
+ ****************************************************************************/
+
+ .global exception_common
+
+/****************************************************************************
+ * Name: exception_common
+ ****************************************************************************/
+.align 8
+exception_common:
+
+ addi sp, sp, -XCPTCONTEXT_SIZE
+
+ sw x1, 1*4(sp) /* ra */
+ sw x3, 3*4(sp) /* gp */
+ sw x4, 4*4(sp) /* tp */
+ sw x5, 5*4(sp) /* t0 */
+ sw x6, 6*4(sp) /* t1 */
+ sw x7, 7*4(sp) /* t2 */
+ sw x8, 8*4(sp) /* s0 */
+ sw x9, 9*4(sp) /* s1 */
+ sw x10, 10*4(sp) /* a0 */
+ sw x11, 11*4(sp) /* a1 */
+ sw x12, 12*4(sp) /* a2 */
+ sw x13, 13*4(sp) /* a3 */
+ sw x14, 14*4(sp) /* a4 */
+ sw x15, 15*4(sp) /* a5 */
+ sw x16, 16*4(sp) /* a6 */
+ sw x17, 17*4(sp) /* a7 */
+ sw x18, 18*4(sp) /* s2 */
+ sw x19, 19*4(sp) /* s3 */
+ sw x20, 20*4(sp) /* s4 */
+ sw x21, 21*4(sp) /* s5 */
+ sw x22, 22*4(sp) /* s6 */
+ sw x23, 23*4(sp) /* s7 */
+ sw x24, 24*4(sp) /* s8 */
+ sw x25, 25*4(sp) /* s9 */
+ sw x26, 26*4(sp) /* s10 */
+ sw x27, 27*4(sp) /* s11 */
+ sw x28, 28*4(sp) /* t3 */
+ sw x29, 29*4(sp) /* t4 */
+ sw x30, 30*4(sp) /* t5 */
+ sw x31, 31*4(sp) /* t6 */
+
+ csrr s0, mstatus
+ sw s0, 32*4(sp) /* mstatus */
+
+ addi s0, sp, XCPTCONTEXT_SIZE
+ sw s0, 2*4(sp) /* original SP */
+
+ /* Setup arg0(exception cause), arg1(context) */
+
+ csrr a0, mcause /* exception cause */
+ csrr s0, mepc
+ sw s0, 0(sp) /* exception PC */
+
+ mv a1, sp /* context = sp */
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+ /* Switch to interrupt stack */
+
+ lui sp, %hi(g_intstackbase)
+ addi sp, sp, %lo(g_intstackbase)
+#endif
+
+ /* Call interrupt handler in C */
+
+ jal x1, bl602_dispatch_irq
+
+ /* If context switch is needed, return a new sp */
+
+ mv sp, a0
+ lw s0, 0(sp) /* restore mepc */
+ csrw mepc, s0
+
+ lw s0, 32*4(sp) /* restore mstatus */
+ csrw mstatus, s0
+
+ lw x3, 3*4(sp) /* gp */
+ lw x4, 4*4(sp) /* tp */
+ lw x5, 5*4(sp) /* t0 */
+ lw x6, 6*4(sp) /* t1 */
+ lw x7, 7*4(sp) /* t2 */
+ lw x8, 8*4(sp) /* s0 */
+ lw x9, 9*4(sp) /* s1 */
+ lw x10, 10*4(sp) /* a0 */
+ lw x11, 11*4(sp) /* a1 */
+ lw x12, 12*4(sp) /* a2 */
+ lw x13, 13*4(sp) /* a3 */
+ lw x14, 14*4(sp) /* a4 */
+ lw x15, 15*4(sp) /* a5 */
+ lw x16, 16*4(sp) /* a6 */
+ lw x17, 17*4(sp) /* a7 */
+ lw x18, 18*4(sp) /* s2 */
+ lw x19, 19*4(sp) /* s3 */
+ lw x20, 20*4(sp) /* s4 */
+ lw x21, 21*4(sp) /* s5 */
+ lw x22, 22*4(sp) /* s6 */
+ lw x23, 23*4(sp) /* s7 */
+ lw x24, 24*4(sp) /* s8 */
+ lw x25, 25*4(sp) /* s9 */
+ lw x26, 26*4(sp) /* s10 */
+ lw x27, 27*4(sp) /* s11 */
+ lw x28, 28*4(sp) /* t3 */
+ lw x29, 29*4(sp) /* t4 */
+ lw x30, 30*4(sp) /* t5 */
+ lw x31, 31*4(sp) /* t6 */
+
+ lw x1, 1*4(sp) /* ra */
+
+ lw sp, 2*4(sp) /* restore original sp */
+
+ /* Return from Machine Interrupt */
+
+ mret
+
+/************************************************************************************
+ * Name: g_intstackalloc and g_intstackbase
+ ************************************************************************************/
+
+#if CONFIG_ARCH_INTERRUPTSTACK > 3
+ .bss
+ .align 4
+ .global g_intstackalloc
+ .global g_intstackbase
+ .type g_intstackalloc, object
+ .type g_intstackbase, object
+g_intstackalloc:
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3))
+g_intstackbase:
+ .skip 4
+ .size g_intstackbase, 4
+ .size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
+#endif
diff --git a/arch/risc-v/src/bl602/bl602_idle.c b/arch/risc-v/src/bl602/bl602_idle.c
new file mode 100644
index 0000000000..f8607732d6
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_idle.c
@@ -0,0 +1,67 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_idle.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "riscv_internal.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ * up_idle() is the logic that will be executed when their is no other
+ * ready-to-run task. This is processor idle time and will continue until
+ * some interrupt occurs to cause a context switch from the idle task.
+ *
+ * Processing in this state may be processor-specific. e.g., this is where
+ * power management operations might be performed.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+ /* If the system is idle and there are no timer interrupts, then process
+ * "fake" timer interrupts. Hopefully, something will wake up.
+ */
+
+ nxsched_process_timer();
+#else
+
+ /* This would be an appropriate place to put some MCU-specific logic to
+ * sleep in a reduced power mode until an interrupt occurs to save power
+ */
+
+ asm("WFI");
+
+#endif
+}
diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c
new file mode 100644
index 0000000000..235603c983
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_irq.c
@@ -0,0 +1,253 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdio.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "riscv_internal.h"
+#include "riscv_arch.h"
+
+#include "hardware/clic.h"
+
+#include "chip.h"
+
+void bl_irq_enable(unsigned int source)
+{
+ *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1;
+}
+
+void bl_irq_disable(unsigned int source)
+{
+ *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0;
+}
+
+void bl_irq_pending_set(unsigned int source)
+{
+ *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1;
+}
+
+void bl_irq_pending_clear(unsigned int source)
+{
+ *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+ /* Disable Machine interrupts */
+
+ up_irq_save();
+
+#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
+ /* Colorize the interrupt stack for debug purposes */
+
+ size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
+ up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
+ intstack_size);
+#endif
+
+ /* currents_regs is non-NULL only while processing an interrupt */
+
+ g_current_regs = NULL;
+
+ /* Attach the ecall interrupt handler */
+
+ irq_attach(BL602_IRQ_ECALLM, up_swint, NULL);
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+
+ /* And finally, enable interrupts */
+
+ up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ uint32_t oldstat;
+
+ if (irq == BL602_IRQ_MSOFT)
+ {
+ /* Read mstatus & clear machine software interrupt enable in mie */
+
+ asm volatile("csrrc %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE));
+ }
+ else if (irq == BL602_IRQ_MTIMER)
+ {
+ *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 0;
+
+ /* Read mstatus & clear machine timer interrupt enable in mie */
+
+ asm volatile("csrrc %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MTIE));
+ }
+ else
+ {
+ ASSERT(irq < 64 + 16 + BL602_IRQ_ASYNC);
+ bl_irq_disable(irq - BL602_IRQ_ASYNC);
+ }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ * Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+ uint32_t oldstat;
+
+ if (irq == BL602_IRQ_MSOFT)
+ {
+ /* Read mstatus & set machine software interrupt enable in mie */
+
+ asm volatile("csrrs %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MSIE));
+ }
+ else if (irq == BL602_IRQ_MTIMER)
+ {
+ *(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 1;
+
+ /* Read mstatus & set machine timer interrupt enable in mie */
+
+ asm volatile("csrrs %0, mie, %1"
+ : "=r"(oldstat)
+ : "r"(MIE_MTIE | 0x1 << 11));
+ }
+ else
+ {
+ ASSERT(irq < 64 + 16 + BL602_IRQ_ASYNC);
+ bl_irq_enable(irq - BL602_IRQ_ASYNC);
+ }
+}
+
+/****************************************************************************
+ * Name: up_get_newintctx
+ *
+ * Description:
+ * Return initial mstatus when a task is created.
+ *
+ ****************************************************************************/
+
+uint32_t up_get_newintctx(void)
+{
+ /* Set machine previous privilege mode to machine mode.
+ * Also set machine previous interrupt enable
+ */
+
+ return (MSTATUS_MPPM | MSTATUS_MPIE);
+}
+
+/****************************************************************************
+ * Name: up_ack_irq
+ *
+ * Description:
+ * Acknowledge the IRQ
+ *
+ ****************************************************************************/
+
+void up_ack_irq(int irq)
+{
+}
+
+/****************************************************************************
+ * Name: up_irq_save
+ *
+ * Description:
+ * Return the current interrupt state and disable interrupts
+ *
+ ****************************************************************************/
+
+irqstate_t up_irq_save(void)
+{
+ uint32_t oldstat;
+
+ /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */
+
+ asm volatile("csrrc %0, mstatus, %1" : "=r"(oldstat) : "r"(MSTATUS_MIE));
+ return oldstat;
+}
+
+/****************************************************************************
+ * Name: up_irq_restore
+ *
+ * Description:
+ * Restore previous IRQ mask state
+ *
+ ****************************************************************************/
+
+void up_irq_restore(irqstate_t flags)
+{
+ /* Write flags to mstatus */
+
+ asm volatile("csrw mstatus, %0"
+ : /* no output */
+ : "r"(flags));
+}
+
+/****************************************************************************
+ * Name: up_irq_enable
+ *
+ * Description:
+ * Return the current interrupt state and enable interrupts
+ *
+ ****************************************************************************/
+
+irqstate_t up_irq_enable(void)
+{
+ uint32_t oldstat;
+
+ /* Enable MEIE (machine external interrupt enable) */
+
+ asm volatile("csrrs %0, mie, %1" : "=r"(oldstat) : "r"(MIE_MEIE));
+
+ /* Read mstatus & set machine interrupt enable (MIE) in mstatus */
+
+ asm volatile("csrrs %0, mstatus, %1" : "=r"(oldstat) : "r"(MSTATUS_MIE));
+ return oldstat;
+}
diff --git a/arch/risc-v/src/bl602/bl602_irq_dispatch.c b/arch/risc-v/src/bl602/bl602_irq_dispatch.c
new file mode 100644
index 0000000000..ba6c0f77dd
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_irq_dispatch.c
@@ -0,0 +1,105 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_irq_dispatch.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "riscv_arch.h"
+#include "riscv_internal.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+volatile uint32_t *g_current_regs;
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * bl602_dispatch_irq
+ ****************************************************************************/
+
+void *bl602_dispatch_irq(uint32_t vector, uint32_t *regs)
+{
+ uint32_t irq = vector & 0x3ff; /* E24 [9:0] */
+ uint32_t *mepc = regs;
+
+ /* If current is interrupt */
+
+ if (vector & 0x80000000u)
+ {
+ irq += BL602_IRQ_ASYNC;
+ }
+
+ /* NOTE: In case of ecall, we need to adjust mepc in the context */
+
+ if (BL602_IRQ_ECALLM == irq)
+ {
+ *mepc += 4;
+ }
+
+ /* Acknowledge the interrupt */
+
+ up_ack_irq(irq);
+
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+ PANIC();
+#else
+ /* Current regs non-zero indicates that we are processing an interrupt;
+ * g_current_regs is also used to manage interrupt level context switches.
+ *
+ * Nested interrupts are not supported
+ */
+
+ DEBUGASSERT(g_current_regs == NULL);
+ g_current_regs = regs;
+
+ /* Deliver the IRQ */
+
+ irq_dispatch(irq, regs);
+
+#endif
+
+ /* If a context switch occurred while processing the interrupt then
+ * g_current_regs may have change value. If we return any value different
+ * from the input regs, then the lower level will know that a context
+ * switch occurred during interrupt processing.
+ */
+
+ regs = (uint32_t *)g_current_regs;
+ g_current_regs = NULL;
+
+ return regs;
+}
diff --git a/arch/risc-v/src/bl602/bl602_lowputc.c b/arch/risc-v/src/bl602/bl602_lowputc.c
new file mode 100644
index 0000000000..8305cbf56a
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_lowputc.c
@@ -0,0 +1,434 @@
+/****************************************************************************
+ * boards/risc-v/bl602/evb/src/bl602_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+
+#include <arch/board/board.h>
+
+#include "hardware/bl602_gpio.h"
+#include "hardware/bl602_glb.h"
+#include "hardware/bl602_hbn.h"
+#include "hardware/bl602_uart.h"
+
+#include "bl602_lowputc.h"
+#include "riscv_arch.h"
+#include "riscv_internal.h"
+
+#include "bl602_config.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Select UART parameters for the selected console */
+#ifdef HAVE_SERIAL_CONSOLE
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#define BL602_CONSOLE_IDX 0
+#define BL602_CONSOLE_BASE UART0_BASE
+#define BL602_CONSOLE_BAUD CONFIG_UART0_BAUD
+#define BL602_CONSOLE_BITS CONFIG_UART0_BITS
+#define BL602_CONSOLE_PARITY CONFIG_UART0_PARITY
+#define BL602_CONSOLE_2STOP CONFIG_UART0_2STOP
+#ifdef UART0_IFLOWCONTROL
+#define BL602_CONSOLE_IFLOWCTL UART0_IFLOWCONTROL
+#else
+#define BL602_CONSOLE_IFLOWCTL 0
+#endif
+#ifdef UART0_OFLOWCONTROL
+#define BL602_CONSOLE_OFLOWCTL UART0_OFLOWCONTROL
+#else
+#define BL602_CONSOLE_OFLOWCTL 0
+#endif
+#define BL602_CONSOLE_TX_PIN CONFIG_BL602_UART0_TX_PIN
+#define BL602_CONSOLE_RX_PIN CONFIG_BL602_UART0_RX_PIN
+#define BL602_CONSOLE_RTS_PIN CONFIG_BL602_UART0_RTS_PIN
+#define BL602_CONSOLE_CTS_PIN CONFIG_BL602_UART0_CTS_PIN
+#define HAVE_UART
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#define BL602_CONSOLE_IDX 1
+#define BL602_CONSOLE_BASE UART1_BASE
+#define BL602_CONSOLE_BAUD CONFIG_UART1_BAUD
+#define BL602_CONSOLE_BITS CONFIG_UART1_BITS
+#define BL602_CONSOLE_PARITY CONFIG_UART1_PARITY
+#define BL602_CONSOLE_2STOP CONFIG_UART1_2STOP
+#ifdef UART1_IFLOWCONTROL
+#define BL602_CONSOLE_IFLOWCTL UART1_IFLOWCONTROL
+#else
+#define BL602_CONSOLE_IFLOWCTL 0
+#endif
+#ifdef UART1_OFLOWCONTROL
+#define BL602_CONSOLE_OFLOWCTL UART1_OFLOWCONTROL
+#else
+#define BL602_CONSOLE_OFLOWCTL 0
+#endif
+#define BL602_CONSOLE_TX_PIN CONFIG_BL602_UART1_TX_PIN
+#define BL602_CONSOLE_RX_PIN CONFIG_BL602_UART1_RX_PIN
+#define BL602_CONSOLE_RTS_PIN CONFIG_BL602_UART1_RTS_PIN
+#define BL602_CONSOLE_CTS_PIN CONFIG_BL602_UART1_CTS_PIN
+#define HAVE_UART
+#endif
+#endif /* HAVE_CONSOLE */
+
+#define _BL602_UART_CLOCK (160 * 1000 * 1000UL) /* UART clock */
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_SERIAL_CONSOLE
+static const struct uart_config_s g_bl602_console_config =
+{
+ .idx = BL602_CONSOLE_IDX,
+ .baud = BL602_CONSOLE_BAUD,
+ .parity = BL602_CONSOLE_PARITY,
+ .data_bits = BL602_CONSOLE_BITS,
+ .stop_bits = BL602_CONSOLE_2STOP,
+#ifdef BL602_CONSOLE_IFLOWCTL
+ .iflow_ctl = BL602_CONSOLE_IFLOWCTL,
+#else
+ .iflow_ctl = 0,
+#endif
+
+#ifdef BL602_CONSOLE_OFLOWCTL
+ .oflow_ctl = BL602_CONSOLE_OFLOWCTL,
+#else
+ .oflow_ctl = 0,
+#endif
+ .tx_pin = BL602_CONSOLE_TX_PIN,
+ .rx_pin = BL602_CONSOLE_RX_PIN,
+ .rts_pin = BL602_CONSOLE_RTS_PIN,
+ .cts_pin = BL602_CONSOLE_CTS_PIN,
+};
+#endif /* HAVE_SERIAL_CONSOLE */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static void uart_gpio_init(uint8_t id,
+ uint8_t tx_pin,
+ uint8_t rx_pin,
+ uint8_t cts_pin,
+ uint8_t rts_pin)
+{
+ struct gpio_cfg_s cfg;
+ enum glb_uart_sig_fun_e tx_sigfun;
+ enum glb_uart_sig_fun_e rx_sigfun;
+
+ cfg.drive = 1;
+ cfg.smt_ctrl = 1;
+ cfg.gpio_fun = 7;
+
+ cfg.gpio_pin = rx_pin;
+ cfg.gpio_mode = GPIO_MODE_AF;
+ cfg.pull_type = GPIO_PULL_UP;
+ gpio_init(&cfg);
+
+ cfg.gpio_pin = tx_pin;
+ cfg.gpio_mode = GPIO_MODE_AF;
+ cfg.pull_type = GPIO_PULL_UP;
+ gpio_init(&cfg);
+
+ /* select uart gpio function */
+
+ if (id == 0)
+ {
+ tx_sigfun = GLB_UART_SIG_FUN_UART0_TXD;
+ rx_sigfun = GLB_UART_SIG_FUN_UART0_RXD;
+ }
+ else
+ {
+ tx_sigfun = GLB_UART_SIG_FUN_UART1_TXD;
+ rx_sigfun = GLB_UART_SIG_FUN_UART1_RXD;
+ }
+
+ glb_uart_fun_sel(tx_pin % 8, tx_sigfun);
+ glb_uart_fun_sel(rx_pin % 8, rx_sigfun);
+}
+
+static void bl602_enable_uart_clk(uint8_t enable,
+ enum hbn_uart_clk_type_e clk_sel,
+ uint8_t div)
+{
+ uint32_t tmp_val;
+
+ /* disable UART clock first */
+
+ tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+ tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN);
+ BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
+
+ /* Set div */
+
+ tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, GLB_UART_CLK_DIV, div);
+ BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
+
+ /* Select clock source for uart */
+
+ hbn_set_uart_clk_sel(clk_sel);
+
+ /* Set enable or disable */
+
+ tmp_val = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+ if (enable)
+ {
+ tmp_val = BL_SET_REG_BIT(tmp_val, GLB_UART_CLK_EN);
+ }
+ else
+ {
+ tmp_val = BL_CLR_REG_BIT(tmp_val, GLB_UART_CLK_EN);
+ }
+
+ BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmp_val);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void bl602_uart_configure(uint32_t uartbase,
+ const struct uart_config_s *config)
+{
+ uint32_t tmp_val;
+ uint32_t div = 0;
+ uint32_t fraction = 0;
+ uint32_t tmp_tx_cfg = 0;
+ uint32_t tmp_rx_cfg = 0;
+ enum uart_databits_e data_bits;
+ enum uart_stopbits_e stop_bits;
+
+ bl602_enable_uart_clk(1, HBN_UART_CLK_160M, 3);
+
+ uart_gpio_init(config->idx,
+ config->tx_pin,
+ config->rx_pin,
+ config->cts_pin,
+ config->rts_pin);
+
+ /* Disable all interrupt */
+
+ tmp_val = BL_RD_REG(uartbase, UART_INT_MASK);
+ tmp_val |= 0xff;
+ BL_WR_REG(uartbase, UART_INT_MASK, tmp_val);
+
+ /* Disable uart before config */
+
+ tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
+ BL_WR_REG(
+ uartbase, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN));
+ tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG);
+ BL_WR_REG(
+ uartbase, UART_URX_CONFIG, BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN));
+
+ /* cal the baud rate divisor */
+
+ fraction = (_BL602_UART_CLOCK / (3 + 1)) * 10 / config->baud % 10;
+ div = (_BL602_UART_CLOCK / (3 + 1)) / config->baud;
+ if (fraction >= 5)
+ {
+ ++div;
+ }
+
+ /* set the baud rate register value */
+
+ BL_WR_REG(
+ uartbase, UART_BIT_PRD, ((div - 1) << 0x10) | ((div - 1) & 0xffff));
+
+ /* configure parity type */
+
+ tmp_tx_cfg = BL_RD_REG(uartbase, UART_UTX_CONFIG);
+ tmp_rx_cfg = BL_RD_REG(uartbase, UART_URX_CONFIG);
+
+ switch (config->parity)
+ {
+ case UART_PARITY_NONE:
+ tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
+ tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
+ break;
+ case UART_PARITY_ODD:
+ tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
+ tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL);
+ tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
+ tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL);
+ break;
+ case UART_PARITY_EVEN:
+ tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_EN);
+ tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_PRT_SEL);
+ tmp_rx_cfg = BL_SET_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_EN);
+ tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_PRT_SEL);
+ break;
+ default:
+ break;
+ }
+
+ if (config->data_bits == 5)
+ {
+ data_bits = UART_DATABITS_5;
+ }
+ else if (config->data_bits == 6)
+ {
+ data_bits = UART_DATABITS_6;
+ }
+ else if (config->data_bits == 7)
+ {
+ data_bits = UART_DATABITS_7;
+ }
+ else
+ {
+ data_bits = UART_DATABITS_8;
+ }
+
+ if (config->stop_bits == 1)
+ {
+ stop_bits = UART_STOPBITS_2;
+ }
+ else
+ {
+ stop_bits = UART_STOPBITS_1;
+ }
+
+ /* Configure data bits */
+
+ tmp_tx_cfg =
+ BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_D, (data_bits + 4));
+ tmp_rx_cfg =
+ BL_SET_REG_BITS_VAL(tmp_rx_cfg, UART_CR_URX_BIT_CNT_D, (data_bits + 4));
+
+ /* Configure tx stop bits */
+
+ tmp_tx_cfg =
+ BL_SET_REG_BITS_VAL(tmp_tx_cfg, UART_CR_UTX_BIT_CNT_P, (stop_bits + 1));
+
+ /* Configure tx cts flow control function */
+
+ if (config->oflow_ctl)
+ {
+ tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN);
+ }
+ else
+ {
+ tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UTX_CTS_EN);
+ }
+
+ /* Disable rx input de-glitch function */
+
+ tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_DEG_EN);
+
+ if (config->iflow_ctl)
+ {
+ tmp_tx_cfg = BL_SET_REG_BIT(tmp_tx_cfg, UART_CR_URX_RTS_SW_MODE);
+ }
+ else
+ {
+ tmp_rx_cfg = BL_CLR_REG_BIT(tmp_rx_cfg, UART_CR_URX_RTS_SW_MODE);
+ }
+
+ /* Write back */
+
+ BL_WR_REG(uartbase, UART_UTX_CONFIG, tmp_tx_cfg);
+ BL_WR_REG(uartbase, UART_URX_CONFIG, tmp_rx_cfg);
+
+ /* Configure LSB-first */
+
+ tmp_tx_cfg = BL_RD_REG(uartbase, UART_DATA_CONFIG);
+ tmp_tx_cfg = BL_CLR_REG_BIT(tmp_tx_cfg, UART_CR_UART_BIT_INV);
+ BL_WR_REG(uartbase, UART_DATA_CONFIG, tmp_tx_cfg);
+
+ /* Enable tx free run mode */
+
+ tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
+ BL_WR_REG(
+ uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_FRM_EN));
+
+ /* Deal with uart fifo configure register */
+
+ tmp_val = BL_RD_REG(uartbase, UART_FIFO_CONFIG_1);
+
+ /* Configure dma tx fifo threshold */
+
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_TX_FIFO_TH, 0x10 - 1);
+
+ /* Configure dma rx fifo threshold */
+
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, UART_RX_FIFO_TH, 0x10 - 1);
+ BL_WR_REG(uartbase, UART_FIFO_CONFIG_1, tmp_val);
+
+ /* Enable UART tx rx unit */
+
+ tmp_val = BL_RD_REG(uartbase, UART_UTX_CONFIG);
+ BL_WR_REG(
+ uartbase, UART_UTX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_UTX_EN));
+ tmp_val = BL_RD_REG(uartbase, UART_URX_CONFIG);
+ BL_WR_REG(
+ uartbase, UART_URX_CONFIG, BL_SET_REG_BIT(tmp_val, UART_CR_URX_EN));
+}
+
+/****************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ * Output one byte on the serial console
+ *
+ ****************************************************************************/
+
+void up_lowputc(char ch)
+{
+#ifdef HAVE_SERIAL_CONSOLE
+ /* Wait for FIFO */
+
+ while (
+ BL_GET_REG_BITS_VAL(BL_RD_REG(BL602_CONSOLE_BASE, UART_FIFO_CONFIG_1),
+ UART_TX_FIFO_CNT) == 0)
+ ;
+
+ BL_WR_BYTE(BL602_CONSOLE_BASE + UART_FIFO_WDATA_OFFSET, ch);
+#endif /* HAVE_CONSOLE */
+}
+
+void bl602_lowsetup(void)
+{
+#ifdef HAVE_SERIAL_CONSOLE
+ /* Configure the console UART (if any) */
+
+ bl602_uart_configure(BL602_CONSOLE_BASE, &g_bl602_console_config);
+
+ up_lowputc('A');
+ up_lowputc('\r');
+ up_lowputc('\n');
+#endif /* HAVE_SERIAL_CONSOLE */
+}
+
diff --git a/arch/risc-v/src/bl602/bl602_lowputc.h b/arch/risc-v/src/bl602/bl602_lowputc.h
new file mode 100644
index 0000000000..07e728bd70
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_lowputc.h
@@ -0,0 +1,73 @@
+/**
+ * incubator-nuttx/arch/risc-v/src/bl602/bl602_lowputc.h
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARCH_RISCV_SRC_BL602_LOWPUTC_H
+#define __ARCH_RISCV_SRC_BL602_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+struct uart_config_s
+{
+ uint8_t idx; /* Uart idx */
+ uint32_t baud; /* Configured baud */
+ uint8_t iflow_ctl; /* Input flow control supported */
+ uint8_t oflow_ctl; /* Output flow control supported. */
+ uint8_t data_bits; /* Number of bits per word */
+ bool stop_bits; /* true=2 stop bits; false=1 stop bit */
+ uint8_t parity; /* Parity selection: 0=none, 1=odd, 2=even */
+ uint8_t tx_pin; /* TX pin */
+ uint8_t rx_pin; /* RX pin */
+ uint8_t cts_pin; /* CTS pin */
+ uint8_t rts_pin; /* RTS pin */
+};
+
+/****************************************************************************
+ * Name: bl602_lowsetup
+ ****************************************************************************/
+
+EXTERN void bl602_lowsetup(void);
+
+EXTERN void bl602_uart_configure(uint32_t base_addr,
+ const struct uart_config_s *config);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_LOWPUTC_H */
diff --git a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
new file mode 100644
index 0000000000..23184776d4
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.c
@@ -0,0 +1,416 @@
+/****************************************************************************
+ * arch/arm/src/bl602/bl602_oneshot_lowerhalf.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/kmalloc.h>
+#include <nuttx/timers/oneshot.h>
+
+#include <hardware/bl602_timer.h>
+#include "bl602_oneshot_lowerhalf.h"
+
+#define TIMER_MAX_VALUE (0xFFFFFFFF)
+#define TIMER_CLK_DIV (160)
+#define TIMER_CLK_FREQ (160000000UL / (TIMER_CLK_DIV))
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* This structure describes the state of the oneshot timer lower-half driver
+ */
+
+struct bl602_oneshot_lowerhalf_s
+{
+ /* This is the part of the lower half driver that is visible to the upper-
+ * half client of the driver. This must be the first thing in this
+ * structure so that pointers to struct oneshot_lowerhalf_s are cast
+ * compatible to struct bl602_oneshot_lowerhalf_s and vice versa.
+ */
+
+ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */
+
+ uint32_t freq;
+
+ /* Private lower half data follows */
+
+ oneshot_callback_t callback; /* Internal handler that receives callback */
+ FAR void * arg; /* Argument that is passed to the handler */
+ uint8_t tim; /* timer tim 0,1 */
+ uint8_t irq; /* IRQ associated with this UART */
+ bool started; /* True: Timer has been started */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int bl602_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec * ts);
+static int bl602_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback,
+ FAR void * arg,
+ FAR const struct timespec * ts);
+static int bl602_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec * ts);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Lower half operations */
+
+static const struct oneshot_operations_s g_oneshot_ops =
+{
+ .max_delay = bl602_max_delay,
+ .start = bl602_start,
+ .cancel = bl602_cancel,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_oneshot_handler
+ *
+ * Description:
+ * Timer expiration handler
+ *
+ * Input Parameters:
+ * arg - Should be the same argument provided when bl602_oneshot_start()
+ * was called.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static int bl602_oneshot_handler(int irq, FAR void *context, FAR void *arg)
+{
+ FAR struct bl602_oneshot_lowerhalf_s *priv =
+ (FAR struct bl602_oneshot_lowerhalf_s *)arg;
+
+ oneshot_callback_t callback;
+ FAR void * cbarg;
+
+ /* Clear Interrupt Bits */
+
+ uint32_t int_id;
+ uint32_t tmp_val;
+ uint32_t tmp_addr;
+
+ int_id = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
+ tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
+ tmp_val = BL_RD_WORD(tmp_addr);
+
+ /* Comparator 0 match interrupt */
+
+ if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0))
+ {
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0));
+ callback = priv->callback;
+ cbarg = priv->arg;
+
+ if (callback)
+ {
+ callback(&priv->lh, cbarg);
+ }
+ }
+
+ /* Comparator 1 match interrupt */
+
+ if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1))
+ {
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1));
+ }
+
+ /* Comparator 2 match interrupt */
+
+ if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2))
+ {
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2));
+ }
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: bl602_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the maximum delay.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int bl602_max_delay(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec * ts)
+{
+ FAR struct bl602_oneshot_lowerhalf_s *priv =
+ (FAR struct bl602_oneshot_lowerhalf_s *)lower;
+ uint64_t usecs;
+
+ DEBUGASSERT(priv != NULL && ts != NULL);
+ usecs = (uint64_t)(UINT32_MAX / priv->freq) * (uint64_t)USEC_PER_SEC;
+
+ uint64_t sec = usecs / 1000000;
+ usecs -= 1000000 * sec;
+
+ ts->tv_sec = (time_t)sec;
+ ts->tv_nsec = (long)(usecs * 1000);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: bl602_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * lower An instance of the lower-half oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+static int bl602_start(FAR struct oneshot_lowerhalf_s *lower,
+ oneshot_callback_t callback,
+ FAR void * arg,
+ FAR const struct timespec * ts)
+{
+ FAR struct bl602_oneshot_lowerhalf_s *priv =
+ (FAR struct bl602_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+ uint64_t usec;
+
+ DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL);
+
+ if (priv->started == true)
+ {
+ /* Yes.. then cancel it */
+
+ tmrinfo("Already running... cancelling\n");
+ bl602_cancel(lower, NULL);
+ }
+
+ /* Save the callback information and start the timer */
+
+ flags = enter_critical_section();
+ priv->callback = callback;
+ priv->arg = arg;
+
+ /* Express the delay in microseconds */
+
+ usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
+ (uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
+
+ timer_setcompvalue(
+ priv->tim, TIMER_COMP_ID_0, usec / (TIMER_CLK_FREQ / priv->freq));
+
+ timer_setpreloadvalue(priv->tim, 0);
+ irq_attach(priv->irq, bl602_oneshot_handler, (void *)priv);
+ up_enable_irq(priv->irq);
+ timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
+ timer_enable(priv->tim);
+ priv->started = true;
+
+ leave_critical_section(flags);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: bl602_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * lower Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+static int bl602_cancel(FAR struct oneshot_lowerhalf_s *lower,
+ FAR struct timespec * ts)
+{
+ FAR struct bl602_oneshot_lowerhalf_s *priv =
+ (FAR struct bl602_oneshot_lowerhalf_s *)lower;
+ irqstate_t flags;
+
+ DEBUGASSERT(priv != NULL);
+
+ /* Cancel the timer */
+
+ if (priv->started)
+ {
+ flags = enter_critical_section();
+
+ timer_disable(priv->tim);
+ priv->started = false;
+ up_disable_irq(priv->irq);
+ timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
+ priv->callback = NULL;
+ priv->arg = NULL;
+
+ leave_critical_section(flags);
+ return OK;
+ }
+
+ return -ENODEV;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer and return a oneshot lower half driver
+ * instance.
+ *
+ * Input Parameters:
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * On success, a non-NULL instance of the oneshot lower-half driver is
+ * returned. NULL is return on any failure.
+ *
+ ****************************************************************************/
+
+FAR struct oneshot_lowerhalf_s *oneshot_initialize(int chan,
+ uint16_t resolution)
+{
+ FAR struct bl602_oneshot_lowerhalf_s *priv;
+ timer_cfg_t timstr;
+
+ /* Allocate an instance of the lower half driver */
+
+ priv = (FAR struct bl602_oneshot_lowerhalf_s *)kmm_zalloc(
+ sizeof(struct bl602_oneshot_lowerhalf_s));
+
+ if (priv == NULL)
+ {
+ tmrerr("ERROR: Failed to initialized state structure\n");
+ return NULL;
+ }
+
+ /* Initialize the lower-half driver structure */
+
+ priv->started = false;
+ priv->lh.ops = &g_oneshot_ops;
+ priv->freq = TIMER_CLK_FREQ / resolution;
+ priv->tim = chan;
+ if (priv->tim == 0)
+ {
+ priv->irq = BL602_IRQ_TIMER_CH0;
+ }
+ else
+ {
+ priv->irq = BL602_IRQ_TIMER_CH1;
+ }
+
+ /* Initialize the contained BL602 oneshot timer */
+
+ timstr.timer_ch = chan; /* Timer channel */
+ timstr.clk_src = TIMER_CLKSRC_FCLK; /* Timer clock source */
+ timstr.pl_trig_src =
+ TIMER_PRELOAD_TRIG_COMP0; /* Timer count register preload trigger source
+ * slelect */
+ timstr.count_mode = TIMER_COUNT_PRELOAD; /* Timer count mode */
+ timstr.clock_division =
+ (TIMER_CLK_DIV * resolution) - 1; /* Timer clock divison value */
+ timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
+ timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
+ timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
+ timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */
+
+ timer_intmask(chan, TIMER_INT_ALL, 1);
+
+ /* timer disable */
+
+ timer_disable(chan);
+
+ timer_init(&timstr);
+
+ return &priv->lh;
+}
+
diff --git a/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h
new file mode 100644
index 0000000000..3388d59bd4
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_oneshot_lowerhalf.h
@@ -0,0 +1,212 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_oneshot.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_BL602_ONESHOT_H
+#define __ARCH_ARM_SRC_BL602_ONESHOT_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+
+#include <nuttx/irq.h>
+
+#include "bl602_tim_lowerhalf.h"
+
+#ifdef CONFIG_BL602_ONESHOT
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if !defined(CONFIG_BL602_ONESHOT_MAXTIMERS) || \
+ CONFIG_BL602_ONESHOT_MAXTIMERS < 1
+#undef CONFIG_BL602_ONESHOT_MAXTIMERS
+#define CONFIG_BL602_ONESHOT_MAXTIMERS 1
+#endif
+
+#if CONFIG_BL602_ONESHOT_MAXTIMERS > 8
+#warning Additional logic required to handle more than 8 timers
+#undef CONFIG_BL602_ONESHOT_MAXTIMERS
+#define CONFIG_BL602_ONESHOT_MAXTIMERS 8
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* This describes the callback function that will be invoked when the oneshot
+ * timer expires. The oneshot fires, the client will receive:
+ *
+ * arg - The opaque argument provided when the interrupt was registered
+ */
+
+typedef void (*oneshot_handler_t)(void *arg);
+
+/* The oneshot client must allocate an instance of this structure and called
+ * bl602_oneshot_initialize() before using the oneshot facilities. The
+ * client should not access the contents of this structure directly since
+ * the contents are subject to change.
+ */
+
+struct bl602_oneshot_s
+{
+ uint8_t chan; /* The timer/counter in use */
+#if CONFIG_BL602_ONESHOT_MAXTIMERS > 1
+ uint8_t cbndx; /* Timer callback handler index */
+#endif
+ volatile bool running; /* True: the timer is running */
+ FAR struct bl602_tim_dev_s *tch; /* Pointer returned by
+ * bl602_tim_init() */
+ volatile oneshot_handler_t handler; /* Oneshot expiration callback */
+ volatile void * arg; /* The argument that will accompany
+ * the callback */
+ uint32_t frequency;
+ uint32_t period;
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_oneshot_initialize
+ *
+ * Description:
+ * Initialize the oneshot timer wrapper
+ *
+ * Input Parameters:
+ * oneshot Caller allocated instance of the oneshot state structure
+ * chan Timer counter channel to be used.
+ * resolution The required resolution of the timer in units of
+ * microseconds. NOTE that the range is restricted to the
+ * range of uint16_t (excluding zero).
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int bl602_oneshot_initialize(struct bl602_oneshot_s *oneshot,
+ int chan,
+ uint16_t resolution);
+
+/****************************************************************************
+ * Name: bl602_oneshot_max_delay
+ *
+ * Description:
+ * Determine the maximum delay of the one-shot timer (in microseconds)
+ *
+ ****************************************************************************/
+
+int bl602_oneshot_max_delay(struct bl602_oneshot_s *oneshot, uint64_t *usec);
+
+/****************************************************************************
+ * Name: bl602_oneshot_start
+ *
+ * Description:
+ * Start the oneshot timer
+ *
+ * Input Parameters:
+ * oneshot Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * bl602_oneshot_initialize();
+ * handler The function to call when when the oneshot timer expires.
+ * arg An opaque argument that will accompany the callback.
+ * ts Provides the duration of the one shot timer.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned
+ * on failure.
+ *
+ ****************************************************************************/
+
+int bl602_oneshot_start(struct bl602_oneshot_s *oneshot,
+ oneshot_handler_t handler,
+ void * arg,
+ const struct timespec * ts);
+
+/****************************************************************************
+ * Name: bl602_oneshot_cancel
+ *
+ * Description:
+ * Cancel the oneshot timer and return the time remaining on the timer.
+ *
+ * NOTE: This function may execute at a high rate with no timer running (as
+ * when pre-emption is enabled and disabled).
+ *
+ * Input Parameters:
+ * oneshot Caller allocated instance of the oneshot state structure. This
+ * structure must have been previously initialized via a call to
+ * bl602_oneshot_initialize();
+ * ts The location in which to return the time remaining on the
+ * oneshot timer. A time of zero is returned if the timer is
+ * not running.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A call to up_timer_cancel() when
+ * the timer is not active should also return success; a negated errno
+ * value is returned on any failure.
+ *
+ ****************************************************************************/
+
+int bl602_oneshot_cancel(struct bl602_oneshot_s *oneshot,
+ struct timespec * ts);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CONFIG_BL602_ONESHOT */
+#endif /* __ARCH_ARM_SRC_BL602_ONESHOT_H */
diff --git a/arch/risc-v/src/bl602/bl602_schedulesigaction.c b/arch/risc-v/src/bl602/bl602_schedulesigaction.c
new file mode 100644
index 0000000000..efa5275a2f
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_schedulesigaction.c
@@ -0,0 +1,195 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_schedulesigaction.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <sched.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <arch/bl602/irq.h>
+
+#include "sched/sched.h"
+#include "riscv_internal.h"
+#include "riscv_arch.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_schedule_sigaction
+ *
+ * Description:
+ * This function is called by the OS when one or more
+ * signal handling actions have been queued for execution.
+ * The architecture specific code must configure things so
+ * that the 'igdeliver' callback is executed on the thread
+ * specified by 'tcb' as soon as possible.
+ *
+ * This function may be called from interrupt handling logic.
+ *
+ * This operation should not cause the task to be unblocked
+ * nor should it cause any immediate execution of sigdeliver.
+ * Typically, a few cases need to be considered:
+ *
+ * (1) This function may be called from an interrupt handler
+ * During interrupt processing, all xcptcontext structures
+ * should be valid for all tasks. That structure should
+ * be modified to invoke sigdeliver() either on return
+ * from (this) interrupt or on some subsequent context
+ * switch to the recipient task.
+ * (2) If not in an interrupt handler and the tcb is NOT
+ * the currently executing task, then again just modify
+ * the saved xcptcontext structure for the recipient
+ * task so it will invoke sigdeliver when that task is
+ * later resumed.
+ * (3) If not in an interrupt handler and the tcb IS the
+ * currently executing task -- just call the signal
+ * handler now.
+ *
+ ****************************************************************************/
+
+void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
+{
+ irqstate_t flags;
+ uint32_t int_ctx;
+
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+
+ /* Make sure that interrupts are disabled */
+
+ flags = enter_critical_section();
+
+ /* Refuse to handle nested signal actions */
+
+ if (!tcb->xcp.sigdeliver)
+ {
+ /* First, handle some special cases when the signal is
+ * being delivered to the currently executing task.
+ */
+
+ sinfo("rtcb=0x%p g_current_regs=0x%p\n", this_task(), g_current_regs);
+
+ if (tcb == this_task())
+ {
+ /* CASE 1: We are not in an interrupt handler and
+ * a task is signalling itself for some reason.
+ */
+
+ if (!g_current_regs)
+ {
+ /* In this case just deliver the signal now. */
+
+ sigdeliver(tcb);
+ }
+
+ /* CASE 2: We are in an interrupt handler AND the
+ * interrupted task is the same as the one that
+ * must receive the signal, then we will have to modify
+ * the return state as well as the state in the TCB.
+ *
+ * Hmmm... there looks like a latent bug here: The following
+ * logic would fail in the strange case where we are in an
+ * interrupt handler, the thread is signalling itself, but
+ * a context switch to another task has occurred so that
+ * g_current_regs does not refer to the thread of this_task()!
+ */
+
+ else
+ {
+ /* Save the return EPC and STATUS registers. These will be
+ * restored by the signal trampoline after the signals have
+ * been delivered.
+ */
+
+ tcb->xcp.sigdeliver = sigdeliver;
+ tcb->xcp.saved_epc = g_current_regs[REG_EPC];
+ tcb->xcp.saved_int_ctx = g_current_regs[REG_INT_CTX];
+
+ /* Then set up to vector to the trampoline with interrupts
+ * disabled
+ */
+
+ g_current_regs[REG_EPC] = (uint32_t)up_sigdeliver;
+
+ int_ctx = g_current_regs[REG_INT_CTX];
+ int_ctx &= ~MSTATUS_MIE;
+
+ g_current_regs[REG_INT_CTX] = int_ctx;
+
+ /* And make sure that the saved context in the TCB
+ * is the same as the interrupt return context.
+ */
+
+ up_savestate(tcb->xcp.regs);
+
+ sinfo("PC/STATUS Saved: %08lx/%08lx New: %08lx/%08lx\n",
+ tcb->xcp.saved_epc,
+ tcb->xcp.saved_int_ctx,
+ g_current_regs[REG_EPC],
+ g_current_regs[REG_INT_CTX]);
+ }
+ }
+
+ /* Otherwise, we are (1) signaling a task is not running
+ * from an interrupt handler or (2) we are not in an
+ * interrupt handler and the running task is signalling
+ * some non-running task.
+ */
+
+ else
+ {
+ /* Save the return EPC and STATUS registers. These will be
+ * restored by the signal trampoline after the signals have
+ * been delivered.
+ */
+
+ tcb->xcp.sigdeliver = sigdeliver;
+ tcb->xcp.saved_epc = tcb->xcp.regs[REG_EPC];
+ tcb->xcp.saved_int_ctx = tcb->xcp.regs[REG_INT_CTX];
+
+ /* Then set up to vector to the trampoline with interrupts
+ * disabled
+ */
+
+ tcb->xcp.regs[REG_EPC] = (uint32_t)up_sigdeliver;
+
+ int_ctx = tcb->xcp.regs[REG_INT_CTX];
+ int_ctx &= ~MSTATUS_MIE;
+
+ tcb->xcp.regs[REG_INT_CTX] = int_ctx;
+
+ sinfo("PC/STATUS Saved: %08lx/%08lx New: %08lx/%08lx\n",
+ tcb->xcp.saved_epc,
+ tcb->xcp.saved_int_ctx,
+ tcb->xcp.regs[REG_EPC],
+ tcb->xcp.regs[REG_INT_CTX]);
+ }
+ }
+
+ leave_critical_section(flags);
+}
diff --git a/arch/risc-v/src/bl602/bl602_serial.c b/arch/risc-v/src/bl602/bl602_serial.c
new file mode 100644
index 0000000000..b539c687a8
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_serial.c
@@ -0,0 +1,984 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+
+#include <arch/board/board.h>
+
+#include "bl602_lowputc.h"
+
+#include "hardware/bl602_gpio.h"
+#include "hardware/bl602_uart.h"
+#include "hardware/bl602_glb.h"
+
+#include "riscv_arch.h"
+#include "riscv_internal.h"
+
+#include "bl602_config.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Select UART parameters for the selected console */
+
+#ifdef HAVE_SERIAL_CONSOLE
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#define BL602_CONSOLE_IDX 0
+#define BL602_CONSOLE_BAUD CONFIG_UART0_BAUD
+#define BL602_CONSOLE_BITS CONFIG_UART0_BITS
+#define BL602_CONSOLE_PARITY CONFIG_UART0_PARITY
+#define BL602_CONSOLE_2STOP CONFIG_UART0_2STOP
+#define BL602_CONSOLE_TX GPIO_UART0_TX
+#define BL602_CONSOLE_RX GPIO_UART0_RX
+#define HAVE_UART
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#define BL602_CONSOLE_IDX 1
+#define BL602_CONSOLE_BAUD CONFIG_UART1_BAUD
+#define BL602_CONSOLE_BITS CONFIG_UART1_BITS
+#define BL602_CONSOLE_PARITY CONFIG_UART1_PARITY
+#define BL602_CONSOLE_2STOP CONFIG_UART1_2STOP
+#define BL602_CONSOLE_TX GPIO_UART1_TX
+#define BL602_CONSOLE_RX GPIO_UART1_RX
+#define HAVE_UART
+#endif
+#endif /* HAVE_CONSOLE */
+/* If we are not using the serial driver for the console, then we still must
+ * provide some minimal implementation of up_putc.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? The console will always
+ * be ttyS0. If there is no console then will use the lowest numbered UART.
+ */
+
+#ifdef HAVE_SERIAL_CONSOLE
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#define CONSOLE_DEV g_uart0port /* UART0 is console */
+#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
+#undef TTYS1_DEV /* No ttyS1 */
+#define SERIAL_CONSOLE 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#define CONSOLE_DEV g_uart1port /* UART0 is console */
+#error "I'm confused... Do we have a serial console or not?"
+#endif
+#else
+#undef CONSOLE_DEV /* No console */
+#undef CONFIG_UART0_SERIAL_CONSOLE
+#if defined(CONFIG_BL602_UART0)
+#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */
+#undef TTYS1_DEV /* No ttyS1 */
+#define SERIAL_CONSOLE 1
+#else
+#undef TTYS0_DEV
+#undef TTYS1_DEV
+#endif
+#endif
+
+/* Common initialization logic will not not know that the all of the UARTs
+ * have been disabled. So, as a result, we may still have to provide
+ * stub implementations of up_earlyserialinit(), up_serialinit(), and
+ * up_putc().
+ */
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct up_dev_s
+{
+ const uint32_t uartbase; /* Base address of UART registers */
+ uint8_t irq; /* IRQ associated with this UART */
+ struct uart_config_s config;
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* Serial driver methods */
+
+static int up_setup(struct uart_dev_s *dev);
+static void up_shutdown(struct uart_dev_s *dev);
+static int up_attach(struct uart_dev_s *dev);
+static void up_detach(struct uart_dev_s *dev);
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
+static int up_receive(struct uart_dev_s *dev, unsigned int *status);
+static void up_rxint(struct uart_dev_s *dev, bool enable);
+static bool up_rxavailable(struct uart_dev_s *dev);
+static void up_send(struct uart_dev_s *dev, int ch);
+static void up_txint(struct uart_dev_s *dev, bool enable);
+static bool up_txready(struct uart_dev_s *dev);
+static bool up_txempty(struct uart_dev_s *dev);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct uart_ops_s g_uart_ops =
+{
+ .setup = up_setup,
+ .shutdown = up_shutdown,
+ .attach = up_attach,
+ .detach = up_detach,
+ .ioctl = up_ioctl,
+ .receive = up_receive,
+ .rxint = up_rxint,
+ .rxavailable = up_rxavailable,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = NULL,
+#endif
+ .send = up_send,
+ .txint = up_txint,
+ .txready = up_txready,
+ .txempty = up_txempty,
+};
+
+/* I/O buffers */
+
+#ifdef CONFIG_BL602_UART0
+static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+static struct up_dev_s g_uart0priv =
+{
+ .uartbase = UART0_BASE,
+ .irq = BL602_IRQ_UART0,
+
+ .config =
+ {
+ .idx = 0,
+ .baud = CONFIG_UART0_BAUD,
+ .parity = CONFIG_UART0_PARITY,
+ .data_bits = CONFIG_UART0_BITS,
+ .stop_bits = CONFIG_UART0_2STOP,
+ .tx_pin = CONFIG_BL602_UART0_TX_PIN,
+ .rx_pin = CONFIG_BL602_UART0_RX_PIN,
+ .rts_pin = CONFIG_BL602_UART0_RTS_PIN,
+ .cts_pin = CONFIG_BL602_UART0_CTS_PIN,
+
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow_ctl = CONFIG_UART0_IFLOWCONTROL,
+#else
+ .iflow_ctl = 0,
+#endif
+
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow_ctl = CONFIG_UART0_OFLOWCONTROL,
+#else
+ .oflow_ctl = 0,
+#endif
+ },
+};
+
+static uart_dev_t g_uart0port =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = 1,
+#endif
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0rxbuffer,
+ },
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0txbuffer,
+ },
+ .ops = &g_uart_ops,
+ .priv = (void *)&g_uart0priv,
+};
+#endif
+
+#ifdef CONFIG_BL602_UART1
+static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+static struct up_dev_s g_uart1priv =
+{
+ .uartbase = UART1_BASE,
+ .irq = BL602_IRQ_UART1,
+
+ .config =
+ {
+ .idx = 1,
+ .baud = CONFIG_UART1_BAUD,
+ .parity = CONFIG_UART1_PARITY,
+ .data_bits = CONFIG_UART1_BITS,
+ .stop_bits = CONFIG_UART1_2STOP,
+ .tx_pin = CONFIG_BL602_UART1_TX_PIN,
+ .rx_pin = CONFIG_BL602_UART1_RX_PIN,
+ .rts_pin = CONFIG_BL602_UART1_RTS_PIN,
+ .cts_pin = CONFIG_BL602_UART1_CTS_PIN,
+
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow_ctl = CONFIG_UART1_IFLOWCONTROL,
+#else
+ .iflow_ctl = 0,
+#endif
+
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow_ctl = CONFIG_UART1_OFLOWCONTROL,
+#else
+ .oflow_ctl = 0,
+#endif
+ },
+};
+
+static uart_dev_t g_uart1port =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = 1,
+#endif
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1rxbuffer,
+ },
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1txbuffer,
+ },
+ .ops = &g_uart_ops,
+ .priv = (void *)&g_uart1priv,
+};
+#endif
+
+static struct uart_dev_s *const g_uart_devs[] =
+{
+#ifdef CONFIG_BL602_UART0
+ [0] = &g_uart0port,
+#endif
+#ifdef CONFIG_BL602_UART1
+ [1] = &g_uart1port
+#endif
+};
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt received on the 'irq' It should call uart_transmitchars or
+ * uart_receivechar to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int __uart_interrupt(int irq, FAR void *context, FAR void *arg)
+{
+ uart_dev_t * dev = (uart_dev_t *)arg;
+ struct up_dev_s *uart_priv = dev->priv;
+ uint32_t tmp_val = 0;
+ uint32_t mask_val = 0;
+
+ tmp_val = BL_RD_REG(uart_priv->uartbase, UART_INT_STS);
+ mask_val = BL_RD_REG(uart_priv->uartbase, UART_INT_MASK);
+
+ /* Length of uart rx data transfer arrived interrupt */
+
+ if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_END_INT) &&
+ !BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_END_MASK))
+ {
+ BL_WR_REG(uart_priv->uartbase, UART_INT_CLEAR, 0x2);
+
+ /* Receive Data ready */
+
+ uart_recvchars(dev);
+ }
+
+ /* Tx fifo ready interrupt,auto-cleared when data is pushed */
+
+ if (BL_IS_REG_BIT_SET(tmp_val, UART_UTX_FIFO_INT) &&
+ !BL_IS_REG_BIT_SET(mask_val, UART_CR_UTX_FIFO_MASK))
+ {
+ /* Transmit data request interrupt */
+
+ uart_xmitchars(dev);
+ }
+
+ /* Rx fifo ready interrupt,auto-cleared when data is popped */
+
+ if (BL_IS_REG_BIT_SET(tmp_val, UART_URX_FIFO_INT) &&
+ !BL_IS_REG_BIT_SET(mask_val, UART_CR_URX_FIFO_MASK))
+ {
+ /* Receive Data ready */
+
+ uart_recvchars(dev);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, etc. This method is called the
+ * first time that the serial port is opened.
+ *
+ ****************************************************************************/
+
+static int up_setup(struct uart_dev_s *dev)
+{
+ struct up_dev_s *uart_priv = (struct up_dev_s *)dev->priv;
+
+ bl602_uart_configure(uart_priv->uartbase, &uart_priv->config);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: up_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial
+ * port is closed
+ *
+ ****************************************************************************/
+
+static void up_shutdown(struct uart_dev_s *dev)
+{
+ uint32_t tmp_val;
+ struct up_dev_s *uart_priv = (struct up_dev_s *)dev->priv;
+
+ /* Disable uart before config */
+
+ tmp_val = BL_RD_REG(uart_priv->uartbase, UART_UTX_CONFIG);
+ BL_WR_REG(uart_priv->uartbase,
+ UART_UTX_CONFIG,
+ BL_CLR_REG_BIT(tmp_val, UART_CR_UTX_EN));
+
+ tmp_val = BL_RD_REG(uart_priv->uartbase, UART_URX_CONFIG);
+ BL_WR_REG(uart_priv->uartbase,
+ UART_URX_CONFIG,
+ BL_CLR_REG_BIT(tmp_val, UART_CR_URX_EN));
+}
+
+/****************************************************************************
+ * Name: up_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled by the attach method (unless the
+ * hardware supports multiple levels of interrupt enabling). The RX and TX
+ * interrupts are not enabled until the txint() and rxint() are called.
+ *
+ ****************************************************************************/
+
+static int up_attach(struct uart_dev_s *dev)
+{
+ int ret;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ ret = irq_attach(priv->irq, __uart_interrupt, (void *)dev);
+ if (ret == OK)
+ {
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: up_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ ****************************************************************************/
+
+static void up_detach(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ /* Disable interrupts */
+
+ up_disable_irq(priv->irq);
+
+ /* Detach from the interrupt */
+
+ irq_detach(priv->irq);
+}
+
+/****************************************************************************
+ * Name: up_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method
+ *
+ ****************************************************************************/
+
+static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode * inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TERMIOS
+ case TCGETS:
+ do
+ {
+ struct termios * termiosp = (struct termios *)arg;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+ termiosp->c_cflag = 0;
+
+ /* Return parity */
+
+ termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) |
+ ((priv->parity == 1) ? PARODD : 0);
+
+ /* Return stop bits */
+
+ termiosp->c_cflag |= (priv->stop_bits) ? CSTOPB : 0;
+
+ /* Return flow control */
+
+ termiosp->c_cflag |= (priv->iflow_ctl) ? CRTS_IFLOW : 0;
+ termiosp->c_cflag |= (priv->oflow_ctl) ? CCTS_OFLOW : 0;
+
+ /* Return baud */
+
+ cfsetispeed(termiosp, priv->baud);
+
+ /* Return number of bits */
+
+ switch (priv->data_bits)
+ {
+ case 5:
+ termiosp->c_cflag |= CS5;
+ break;
+
+ case 6:
+ termiosp->c_cflag |= CS6;
+ break;
+
+ case 7:
+ termiosp->c_cflag |= CS7;
+ break;
+
+ default:
+ case 8:
+ termiosp->c_cflag |= CS8;
+ break;
+ }
+ }
+ while (0);
+ break;
+
+ case TCSETS:
+ do
+ {
+ struct termios * termiosp = (struct termios *)arg;
+ struct up_dev_s * priv = (struct up_dev_s *)dev->priv;
+ struct uart_config_s config;
+ uint32_t tmp_val;
+
+ if (!termiosp)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Decode baud. */
+
+ ret = OK;
+ config.baud = cfgetispeed(termiosp);
+
+ /* Decode number of bits */
+
+ switch (termiosp->c_cflag & CSIZE)
+ {
+ case CS5:
+ config.data_bits = 5;
+ break;
+
+ case CS6:
+ config.data_bits = 6;
+ break;
+
+ case CS7:
+ config.data_bits = 7;
+ break;
+
+ case CS8:
+ config.data_bits = 8;
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Decode parity */
+
+ if ((termiosp->c_cflag & PARENB) != 0)
+ {
+ config.parity = (termiosp->c_cflag & PARODD) ? 1 : 2;
+ }
+ else
+ {
+ config.parity = 0;
+ }
+
+ /* Decode stop bits */
+
+ config.stop_bits = (termiosp->c_cflag & CSTOPB) != 0;
+
+ /* Decode flow control */
+
+ if (priv->idx == 0)
+ {
+#if CONFIG_UART0_IFLOWCONTROL
+ config.iflow_ctl = (termiosp->c_cflag & CRTS_IFLOW) != 0;
+#endif
+#if CONFIG_UART0_OFLOWCONTROL
+ config.oflow_ctl = (termiosp->c_cflag & CCTS_OFLOW) != 0;
+#endif
+ }
+ else
+ {
+#if CONFIG_UART1_IFLOWCONTROL
+ config.iflow_ctl = (termiosp->c_cflag & CRTS_IFLOW) != 0;
+#endif
+#if CONFIG_UART1_OFLOWCONTROL
+ config.oflow_ctl = (termiosp->c_cflag & CCTS_OFLOW) != 0;
+#endif
+ }
+
+ /* Verify that all settings are valid before committing */
+
+ if (ret == OK)
+ {
+ /* Commit */
+
+ memcpy(&priv->config, &config, sizeof(config));
+
+ /* effect the changes immediately - note that we do not
+ * implement TCSADRAIN / TCSAFLUSH
+ */
+
+ tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ bl602_uart_configure(priv->uartbase, &config);
+ BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+ }
+ }
+ while (0);
+ break;
+#endif /* CONFIG_SERIAL_TERMIOS */
+
+ default:
+ ret = -ENOTTY;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: up_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+static int up_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ int rxdata;
+
+ /* Return status information */
+
+ if (status)
+ {
+ *status = 0; /* We are not yet tracking serial errors */
+ }
+
+ /* if uart fifo cnts > 0 */
+
+ if (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1),
+ UART_RX_FIFO_CNT) > 0)
+ {
+ rxdata = BL_RD_BYTE(priv->uartbase + UART_FIFO_RDATA_OFFSET);
+ }
+ else
+ {
+ rxdata = -1;
+ }
+ return rxdata;
+}
+
+/****************************************************************************
+ * Name: up_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+static void up_rxint(struct uart_dev_s *dev, bool enable)
+{
+ uint32_t tmp_val;
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ irqstate_t flags = enter_critical_section();
+
+ if (enable)
+ {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ tmp_val &= ~(1 << UART_INT_RX_FIFO_REQ);
+ tmp_val &= ~(1 << UART_INT_RX_END);
+ BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+#endif
+ }
+ else
+ {
+ tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ tmp_val |= (1 << UART_INT_RX_FIFO_REQ);
+ tmp_val |= (1 << UART_INT_RX_END);
+ BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_rxavailable
+ *
+ * Description:
+ * Return true if the receive register is not empty
+ *
+ ****************************************************************************/
+
+static bool up_rxavailable(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ /* Return true is data is available in the receive data buffer */
+
+ uint32_t rxcnt = BL_GET_REG_BITS_VAL(
+ BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT);
+
+ return rxcnt != 0;
+}
+
+/****************************************************************************
+ * Name: up_send
+ *
+ * Description:
+ * This method will send one byte on the UART.
+ *
+ ****************************************************************************/
+
+static void up_send(struct uart_dev_s *dev, int ch)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ /* Wait for FIFO */
+
+ while (BL_GET_REG_BITS_VAL(BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1),
+ UART_TX_FIFO_CNT) == 0)
+ ;
+
+ BL_WR_BYTE(priv->uartbase + UART_FIFO_WDATA_OFFSET, ch);
+}
+
+/****************************************************************************
+ * Name: up_txint
+ *
+ * Description:
+ * Call to enable or disable TX interrupts
+ *
+ ****************************************************************************/
+
+static void up_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ irqstate_t flags;
+ uint32_t tmp_val;
+
+ flags = enter_critical_section();
+
+ if (enable)
+ {
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ /* Enable the TX interrupt */
+
+ tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ tmp_val &= ~(1 << UART_INT_TX_FIFO_REQ);
+ BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+
+ /* Fake a TX interrupt here by just calling uart_xmitchars() with
+ * interrupts disabled (note this may recurse).
+ */
+
+ uart_xmitchars(dev);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ tmp_val = BL_RD_REG(priv->uartbase, UART_INT_MASK);
+ tmp_val |= (1 << UART_INT_TX_FIFO_REQ);
+ BL_WR_REG(priv->uartbase, UART_INT_MASK, tmp_val);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: up_txready
+ *
+ * Description:
+ * Return true if the tranmsit data register is not full
+ *
+ ****************************************************************************/
+
+static bool up_txready(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ /* Return TRUE if the TX FIFO is not full */
+
+ uint32_t txcnt = BL_GET_REG_BITS_VAL(
+ BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
+
+ return (txcnt != 0);
+}
+
+/****************************************************************************
+ * Name: up_txempty
+ *
+ * Description:
+ * Return true if the tranmsit data register is empty
+ *
+ ****************************************************************************/
+
+static bool up_txempty(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ /* Return TRUE if the TX is pending */
+
+ uint32_t txcnt = BL_GET_REG_BITS_VAL(
+ BL_RD_REG(priv->uartbase, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT);
+
+ return (txcnt == 0);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef USE_EARLYSERIALINIT
+
+/****************************************************************************
+ * Name: up_earlyserialinit
+ *
+ * Description:
+ * Performs the low level UART initialization early in debug so that the
+ * serial console will be available during bootup. This must be called
+ * before up_serialinit. NOTE: This function depends on GPIO pin
+ * configuration performed in up_consoleinit() and main clock iniialization
+ * performed in up_clkinitialize().
+ *
+ ****************************************************************************/
+
+void up_earlyserialinit(void)
+{
+#ifdef HAVE_SERIAL_CONSOLE
+ /* Configuration whichever one is the console */
+
+ CONSOLE_DEV.isconsole = true;
+ up_setup(&CONSOLE_DEV);
+#endif
+}
+#endif
+
+/****************************************************************************
+ * Name: up_serialinit
+ *
+ * Description:
+ * Register serial console and serial ports. This assumes
+ * that up_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void up_serialinit(void)
+{
+ int i;
+ char devname[16];
+
+#ifdef HAVE_SERIAL_CONSOLE
+ /* Register the console */
+
+ uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+
+ /* Register all UARTs */
+
+ strcpy(devname, "/dev/ttySx");
+ for (i = 0; i < sizeof(g_uart_devs) / sizeof(g_uart_devs[0]); i++)
+ {
+ if (g_uart_devs[i] == 0)
+ {
+ continue;
+ }
+
+ /* Don't create a device for the console - we did that above */
+
+ if (g_uart_devs[i]->isconsole)
+ {
+ continue;
+ }
+
+ /* Register USARTs as devices in increasing order */
+
+ devname[9] = '0' + i;
+ uart_register(devname, g_uart_devs[i]);
+ }
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ * Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_SERIAL_CONSOLE
+ struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
+ (void)priv;
+
+ irqstate_t flags = enter_critical_section();
+
+ /* Check for LF */
+
+ if (ch == '\n')
+ {
+ /* Add CR */
+
+ up_lowputc('\r');
+ }
+
+ up_lowputc(ch);
+ leave_critical_section(flags);
+#endif
+ return ch;
+}
+
+/****************************************************************************
+ * Name: up_earlyserialinit, up_serialinit, and up_putc
+ *
+ * Description:
+ * stubs that may be needed. These stubs would be used if all UARTs are
+ * disabled. In that case, the logic in common/up_initialize() is not
+ * smart enough to know that there are not UARTs and will still expect
+ * these interfaces to be provided.
+ *
+ ****************************************************************************/
+
+#else /* HAVE_UART_DEVICE */
+void up_earlyserialinit(void)
+{
+}
+
+void up_serialinit(void)
+{
+}
+
+int up_putc(int ch)
+{
+ return ch;
+}
+
+#endif /* HAVE_UART_DEVICE */
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ * Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef HAVE_SERIAL_CONSOLE
+ /* Check for LF */
+
+ if (ch == '\n')
+ {
+ /* Add CR */
+
+ up_lowputc('\r');
+ }
+
+ up_lowputc(ch);
+#endif
+ return ch;
+}
+
+#endif /* USE_SERIALDRIVER */
diff --git a/arch/risc-v/src/bl602/bl602_start.c b/arch/risc-v/src/bl602/bl602_start.c
new file mode 100644
index 0000000000..5ec82e10ff
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_start.c
@@ -0,0 +1,142 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_init.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+#include <nuttx/config.h>
+
+#include <arch/board/board.h>
+
+#include "bl602_boot2.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FEATURES
+#define showprogress(c) up_lowputc(c)
+#else
+#define showprogress(c)
+#endif
+
+#define PARTITION_BOOT2_RAM_ADDR_ACTIVE (0x42049C00)
+#define PARTITION_HEADER_BOOT2_RAM_ADDR (0x42049C04)
+#define PARTITION_BOOT2_FLASH_HEADER (0x42049d14)
+#define PARTITION_BOOT2_FLASH_CONFIG (0x42049d18)
+#define PARTITION_MAGIC (0x54504642)
+#define PARTITION_FW_PART_NAME "FW"
+#define PARTITION_FW_PART_HEADER_SIZE (0x1000)
+
+/* TODO use header file from project */
+
+#define FW_XIP_ADDRESS (0x23000000)
+
+#define BL602_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
+ * linker script. _ebss lies at the end of the BSS region. The idle task
+ * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
+ * The IDLE thread is the thread that the system boots on and, eventually,
+ * becomes the IDLE, do nothing task that runs only when there is nothing
+ * else to run. The heap continues from there until the end of memory.
+ * g_idle_topstack is a read-only variable the provides this computed
+ * address.
+ */
+
+static uint8_t idle_stack[BL602_IDLESTACK_SIZE];
+
+/* Dont change the name of varaible, since we refer this
+ * boot2_partition_table in linker script
+ */
+
+static struct
+{
+ uint8_t partition_active_idx;
+ uint8_t pad[3];
+ struct pt_table_stuff_config_s table;
+} boot2_partition_table;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+uint32_t g_idle_topstack = (uintptr_t)idle_stack + BL602_IDLESTACK_SIZE;
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+extern void bl602_lowsetup(void);
+extern void exception_common(void);
+extern void bl602_boardinitialize(void);
+
+/****************************************************************************
+ * Name: boot2_get_flash_addr
+ ****************************************************************************/
+
+uint32_t boot2_get_flash_addr(void)
+{
+ extern uint8_t __boot2_flash_cfg_src;
+
+ return (uint32_t)(&__boot2_flash_cfg_src +
+ (sizeof(boot2_partition_table.table.pt_entries[0]) *
+ boot2_partition_table.table.pt_table.entry_cnt));
+}
+
+/****************************************************************************
+ * Name: bfl_main
+ ****************************************************************************/
+
+void bfl_main(void)
+{
+ /* set interrupt vector */
+
+ asm volatile("csrw mtvec, %0" ::"r"((uintptr_t)exception_common + 2));
+
+ /* Configure the UART so we can get debug output */
+
+ bl602_lowsetup();
+
+#ifdef USE_EARLYSERIALINIT
+ up_earlyserialinit();
+#endif
+
+ /* Do board initialization */
+
+ bl602_boardinitialize();
+
+ /* Call nx_start() */
+
+ nx_start();
+
+ /* Shouldn't get here */
+
+ while (1)
+ ;
+}
diff --git a/arch/risc-v/src/bl602/bl602_tim.c b/arch/risc-v/src/bl602/bl602_tim.c
new file mode 100644
index 0000000000..53c4812478
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_tim.c
@@ -0,0 +1,802 @@
+/****************************************************************************
+ * boards/risc-v/bl602/evb/src/bl602_tim.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/bl602_timer.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define TIMER_MAX_MATCH 3
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: timer_getcompvalue
+ *
+ * Description:
+ * Get the specified channel and match comparator value.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * cmp_no - TIMER comparator ID type.
+ *
+ * Returned Value:
+ * Match comapre register value
+ *
+ ****************************************************************************/
+
+uint32_t timer_getcompvalue(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
+{
+ uint32_t tmp_val;
+
+ tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET +
+ 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no));
+ return tmp_val;
+}
+
+/****************************************************************************
+ * Name: timer_setcompvalue
+ *
+ * Description:
+ * TIMER set specified channel and comparator compare value
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * cmp_no - TIMER comparator ID type.
+ * val - TIMER match comapre register value.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void timer_setcompvalue(timer_chan_t timer_ch,
+ timer_comp_id_t cmp_no,
+ uint32_t val)
+{
+ BL_WR_WORD(TIMER_BASE + TIMER_TMR2_0_OFFSET +
+ 4 * (TIMER_MAX_MATCH * timer_ch + cmp_no),
+ val);
+}
+
+/****************************************************************************
+ * Name: timer_getcountervalue
+ *
+ * Description:
+ * TIMER get the specified channel count value.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type
+ *
+ * Returned Value:
+ * TIMER count register value
+ *
+ ****************************************************************************/
+
+uint32_t timer_getcountervalue(timer_chan_t timer_ch)
+{
+ uint32_t tmp_val;
+ uint32_t tmp_addr;
+
+ /* TO avoid risk of reading, don't read TCVWR directly
+ * request for read
+ */
+
+ tmp_addr = TIMER_BASE + TIMER_TCVWR2_OFFSET + 4 * timer_ch;
+ BL_WR_WORD(tmp_addr, 1);
+
+ /* Need wait */
+
+ tmp_val = BL_RD_WORD(tmp_addr);
+ tmp_val = BL_RD_WORD(tmp_addr);
+ tmp_val = BL_RD_WORD(tmp_addr);
+
+ return tmp_val;
+}
+
+/****************************************************************************
+ * Name: timer_getmatchstatus
+ *
+ * Description:
+ * TIMER get specified channel and comparator match status
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * cmp_no - TIMER comparator ID type.
+ *
+ * Returned Value:
+ * 0 or 1
+ *
+ ****************************************************************************/
+
+uint32_t timer_getmatchstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
+{
+ uint32_t tmp_val;
+ uint32_t bit_status = 0;
+
+ tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * timer_ch);
+ switch (cmp_no)
+ {
+ case TIMER_COMP_ID_0:
+ bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_0) ? 1 : 0;
+ break;
+ case TIMER_COMP_ID_1:
+ bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_1) ? 1 : 0;
+ break;
+ case TIMER_COMP_ID_2:
+ bit_status = BL_IS_REG_BIT_SET(tmp_val, TIMER_TMSR_2) ? 1 : 0;
+ break;
+ default:
+ break;
+ }
+
+ return bit_status;
+}
+
+/****************************************************************************
+ * Name: timer_getpreloadvalue
+ *
+ * Description:
+ * TIMER get specified channel preload value
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ *
+ * Returned Value:
+ * Preload register value.
+ *
+ ****************************************************************************/
+
+uint32_t timer_getpreloadvalue(timer_chan_t timer_ch)
+{
+ uint32_t tmp_val;
+ tmp_val = BL_RD_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch);
+
+ return tmp_val;
+}
+
+/****************************************************************************
+ * Name: timer_setpreloadvalue
+ *
+ * Description:
+ * TIMER set preload register low 32bits value
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * val - Preload register low 32bits value.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val)
+{
+ BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_ch, val);
+}
+
+/****************************************************************************
+ * Name: timer_setpreloadtrigsrc
+ *
+ * Description:
+ * TIMER set preload trigger source,COMP0,COMP1,COMP2 or None
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * pl_src - TIMER preload source type.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void timer_setpreloadtrigsrc(timer_chan_t timer_ch,
+ timer_preload_trig_t pl_src)
+{
+ BL_WR_WORD(TIMER_BASE + TIMER_TPLCR2_OFFSET + 4 * timer_ch, pl_src);
+}
+
+/****************************************************************************
+ * Name: timer_setcountmode
+ *
+ * Description:
+ * TIMER set count mode:preload or free run
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * count_mode - TIMER count mode: TIMER_COUNT_PRELOAD or
+ *TIMER_COUNT_FREERUN.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void timer_setcountmode(timer_chan_t timer_ch, timer_countmode_t count_mode)
+{
+ uint32_t tmpval;
+
+ tmpval = BL_RD_WORD(TIMER_BASE + TIMER_TCMR_OFFSET);
+ tmpval &= (~(1 << (timer_ch + 1)));
+ tmpval |= (count_mode << (timer_ch + 1));
+
+ BL_WR_WORD(TIMER_BASE + TIMER_TCMR_OFFSET, tmpval);
+}
+
+/****************************************************************************
+ * Name: timer_clearintstatus
+ *
+ * Description:
+ * TIMER clear interrupt status
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * cmp_no - TIMER macth comparator ID type.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void timer_clearintstatus(timer_chan_t timer_ch, timer_comp_id_t cmp_no)
+{
+ uint32_t tmp_addr;
+ uint32_t tmp_val;
+
+ tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * timer_ch;
+
+ tmp_val = BL_RD_WORD(tmp_addr);
+ tmp_val |= (1 << cmp_no);
+
+ BL_WR_WORD(tmp_addr, tmp_val);
+}
+
+/****************************************************************************
+ * Name: timer_init
+ *
+ * Description:
+ * TIMER initialization function.
+ *
+ * Input Parameters:
+ * timer_cfg - TIMER configuration structure pointer.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void timer_init(timer_cfg_t *timer_cfg)
+{
+ timer_chan_t timer_ch = timer_cfg->timer_ch;
+ uint32_t tmp_val;
+
+ /* Configure timer clock source */
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+ if (timer_ch == TIMER_CH0)
+ {
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_1, timer_cfg->clk_src);
+ }
+ else
+ {
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_2, timer_cfg->clk_src);
+ }
+
+ BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp_val);
+
+ /* Configure timer clock division */
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+ if (timer_ch == TIMER_CH0)
+ {
+ tmp_val =
+ BL_SET_REG_BITS_VAL(tmp_val, TIMER_TCDR2, timer_cfg->clock_division);
+ }
+ else
+ {
+ tmp_val =
+ BL_SET_REG_BITS_VAL(tmp_val, TIMER_TCDR3, timer_cfg->clock_division);
+ }
+
+ BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp_val);
+
+ /* Configure timer count mode: preload or free run */
+
+ timer_setcountmode(timer_ch, timer_cfg->count_mode);
+
+ /* Configure timer preload trigger src */
+
+ timer_setpreloadtrigsrc(timer_ch, timer_cfg->pl_trig_src);
+
+ if (timer_cfg->count_mode == TIMER_COUNT_PRELOAD)
+ {
+ /* Configure timer preload value */
+
+ timer_setpreloadvalue(timer_ch, timer_cfg->pre_load_val);
+ }
+
+ /* Configure match compare values */
+
+ timer_setcompvalue(timer_ch, TIMER_COMP_ID_0, timer_cfg->match_val0);
+ timer_setcompvalue(timer_ch, TIMER_COMP_ID_1, timer_cfg->match_val1);
+ timer_setcompvalue(timer_ch, TIMER_COMP_ID_2, timer_cfg->match_val2);
+}
+
+/****************************************************************************
+ * Name: timer_enable
+ *
+ * Description:
+ * TIMER enable one channel function.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void timer_enable(timer_chan_t timer_ch)
+{
+ uint32_t tmp_val;
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCER);
+ tmp_val |= (1 << (timer_ch + 1));
+
+ BL_WR_REG(TIMER_BASE, TIMER_TCER, tmp_val);
+}
+
+/****************************************************************************
+ * Name: timer_disable
+ *
+ * Description:
+ * TIMER disable one channel function.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void timer_disable(timer_chan_t timer_ch)
+{
+ uint32_t tmp_val;
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCER);
+ tmp_val &= (~(1 << (timer_ch + 1)));
+
+ BL_WR_REG(TIMER_BASE, TIMER_TCER, tmp_val);
+}
+
+/****************************************************************************
+ * Name: timer_intmask
+ *
+ * Description:
+ * TIMER mask or unmask certain or all interrupt.
+ *
+ * Input Parameters:
+ * timer_ch - TIMER channel type.
+ * int_type - TIMER interrupt type.
+ * int_mask - TIMER interrupt mask value:1:disbale interrupt.0:enable
+ *interrupt.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void timer_intmask(timer_chan_t timer_ch,
+ timer_int_t int_type,
+ uint32_t int_mask)
+{
+ uint32_t tmp_addr;
+ uint32_t tmp_val;
+
+ tmp_addr = TIMER_BASE + TIMER_TIER2_OFFSET + 4 * timer_ch;
+ tmp_val = BL_RD_WORD(tmp_addr);
+
+ switch (int_type)
+ {
+ case TIMER_INT_COMP_0:
+ if (int_mask == 0)
+ {
+ /* Enable this interrupt */
+
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_0));
+ }
+ else
+ {
+ /* Disable this interrupt */
+
+ BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_0));
+ }
+
+ break;
+
+ case TIMER_INT_COMP_1:
+ if (int_mask == 0)
+ {
+ /* Enable this interrupt */
+
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_1));
+ }
+ else
+ {
+ /* Disable this interrupt */
+
+ BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_1));
+ }
+
+ break;
+
+ case TIMER_INT_COMP_2:
+ if (int_mask == 0)
+ {
+ /* Enable this interrupt */
+
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_2));
+ }
+ else
+ {
+ /* Disable this interrupt */
+
+ BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_2));
+ }
+
+ break;
+
+ case TIMER_INT_ALL:
+ if (int_mask == 0)
+ {
+ /* Enable this interrupt */
+
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_0));
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_1));
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TIER_2));
+ }
+ else
+ {
+ /* Disable this interrupt */
+
+ BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_0));
+ BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_1));
+ BL_WR_WORD(tmp_addr, BL_CLR_REG_BIT(tmp_val, TIMER_TIER_2));
+ }
+
+ break;
+
+ default:
+ break;
+ }
+}
+
+/****************************************************************************
+ * Name: wdt_set_clock
+ *
+ * Description:
+ * TIMER set watchdog clock source and clock division.
+ *
+ * Input Parameters:
+ * clk_src - Watchdog timer clock source type.
+ * div - Watchdog timer clock division value.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void wdt_set_clock(timer_clksrc_t clk_src, uint8_t div)
+{
+ uint32_t tmp_val;
+
+ /* Configure watchdog timer clock source */
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_CS_WDT, clk_src);
+ BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp_val);
+
+ /* Configure watchdog timer clock divison */
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TIMER_WCDR, div);
+ BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp_val);
+}
+
+/****************************************************************************
+ * Name: wdt_getmatchvalue
+ *
+ * Description:
+ * TIMER get watchdog match compare value.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Watchdog match comapre register value.
+ *
+ ****************************************************************************/
+
+uint32_t wdt_getmatchvalue(void)
+{
+ uint32_t tmp_val;
+
+ WDT_ENABLE_ACCESS();
+
+ /* Get watchdog timer match register value */
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMR);
+
+ return tmp_val;
+}
+
+/****************************************************************************
+ * Name: wdt_setcompvalue
+ *
+ * Description:
+ * TIMER set watchdog match compare value.
+ *
+ * Input Parameters:
+ * val - Watchdog match compare value
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void wdt_setcompvalue(uint16_t val)
+{
+ WDT_ENABLE_ACCESS();
+
+ /* Set watchdog timer match register value */
+
+ BL_WR_REG(TIMER_BASE, TIMER_WMR, val);
+}
+
+/****************************************************************************
+ * Name: wdt_getcountervalue
+ *
+ * Description:
+ * TIMER get watchdog count register value.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * Watchdog count register value.
+ *
+ ****************************************************************************/
+
+uint16_t wdt_getcountervalue(void)
+{
+ uint32_t tmp_val;
+
+ WDT_ENABLE_ACCESS();
+
+ /* Get watchdog timer count register value */
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WVR);
+
+ return tmp_val;
+}
+
+/****************************************************************************
+ * Name: wdt_resetcountervalue
+ *
+ * Description:
+ * TIMER reset watchdog count register value.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void wdt_resetcountervalue(void)
+{
+ uint32_t tmp_val;
+
+ /* Reset watchdog timer count register value */
+
+ WDT_ENABLE_ACCESS();
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WCR);
+
+ /* Set watchdog counter reset register bit0 to 1 */
+
+ BL_WR_REG(TIMER_BASE, TIMER_WCR, BL_SET_REG_BIT(tmp_val, TIMER_WCR));
+}
+
+/****************************************************************************
+ * Name: wdt_getresetstatus
+ *
+ * Description:
+ * TIMER get watchdog reset status.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * 0 or 1.
+ *
+ ****************************************************************************/
+
+uint32_t wdt_getresetstatus(void)
+{
+ uint32_t tmp_val;
+ uint32_t ret;
+
+ WDT_ENABLE_ACCESS();
+
+ /* Get watchdog status register */
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WSR);
+
+ ret = (BL_IS_REG_BIT_SET(tmp_val, TIMER_WTS)) ? 1 : 0;
+ return ret;
+}
+
+/****************************************************************************
+ * Name: wdt_clearresetstatus
+ *
+ * Description:
+ * TIMER clear watchdog reset status.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void wdt_clearresetstatus(void)
+{
+ uint32_t tmp_val;
+
+ WDT_ENABLE_ACCESS();
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WSR);
+
+ /* Set watchdog status register */
+
+ BL_WR_REG(TIMER_BASE, TIMER_WSR, BL_CLR_REG_BIT(tmp_val, TIMER_WTS));
+}
+
+/****************************************************************************
+ * Name: wdt_enable
+ *
+ * Description:
+ * TIMER enable watchdog function.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void wdt_enable(void)
+{
+ uint32_t tmp_val;
+
+ WDT_ENABLE_ACCESS();
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+
+ BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmp_val, TIMER_WE));
+}
+
+/****************************************************************************
+ * Name: wdt_disable
+ *
+ * Description:
+ * Watchdog timer disable function.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void wdt_disable(void)
+{
+ uint32_t tmp_val;
+
+ WDT_ENABLE_ACCESS();
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+
+ BL_WR_REG(TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmp_val, TIMER_WE));
+}
+
+/****************************************************************************
+ * Name: wdt_intmask
+ *
+ * Description:
+ * Watchdog timer mask or unmask certain or all interrupt.
+ *
+ * Input Parameters:
+ * int_type - Watchdog interrupt type.
+ * int_mask - Watchdog interrupt mask value:BL_STD_MASK:disbale
+ *interrupt.BL_STD_UNMASK:enable interrupt.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void wdt_intmask(wdt_int_t int_type, uint32_t int_mask)
+{
+ uint32_t tmp_val;
+
+ WDT_ENABLE_ACCESS();
+
+ /* Deal with watchdog match/interrupt enable register,WRIE:watchdog
+ * reset/interrupt enable
+ */
+
+ tmp_val = BL_RD_REG(TIMER_BASE, TIMER_WMER);
+
+ switch (int_type)
+ {
+ case WDT_INT:
+ if (int_mask == 0)
+ {
+ /* Enable this interrupt */
+
+ /* 0 means generates a watchdog interrupt,a watchdog timer reset is
+ * not generated
+ */
+
+ BL_WR_REG(
+ TIMER_BASE, TIMER_WMER, BL_CLR_REG_BIT(tmp_val, TIMER_WRIE));
+ }
+ else
+ {
+ /* Disable this interrupt */
+
+ /* 1 means generates a watchdog timer reset,a watchdog interrupt is
+ * not generated
+ */
+
+ BL_WR_REG(
+ TIMER_BASE, TIMER_WMER, BL_SET_REG_BIT(tmp_val, TIMER_WRIE));
+ }
+
+ break;
+ default:
+ break;
+ }
+}
+
diff --git a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
new file mode 100644
index 0000000000..e0b9da3587
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.c
@@ -0,0 +1,447 @@
+/****************************************************************************
+ * boards/risc-v/bl602/evb/src/bl602_lowerhalf.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <errno.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/timers/timer.h>
+
+#include <arch/board/board.h>
+
+#include <hardware/bl602_glb.h>
+#include <hardware/bl602_timer.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define TIMER_MAX_VALUE (0xFFFFFFFF)
+#define TIMER_CLK_DIV (159)
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct bl602_lowerhalf_s
+{
+ FAR const struct timer_ops_s *ops; /* Lower half operations */
+ tccb_t callback; /* Current upper half interrupt callback */
+ FAR void *arg; /* Argument passed to upper half callback */
+ bool started; /* True: Timer has been started */
+ uint8_t irq; /* IRQ associated with this UART */
+ uint8_t tim; /* timer tim 0,1 */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int bl602_timer_handler(int irq, void *context, void *arg);
+
+/* "Lower half" driver methods */
+
+static int bl602_start(FAR struct timer_lowerhalf_s *lower);
+static int bl602_stop(FAR struct timer_lowerhalf_s *lower);
+static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
+ FAR struct timer_status_s * status);
+static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
+ uint32_t timeout);
+static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
+ tccb_t callback,
+ FAR void * arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* "Lower half" driver methods */
+
+static const struct timer_ops_s g_timer_ops =
+{
+ .start = bl602_start,
+ .stop = bl602_stop,
+ .getstatus = bl602_getstatus,
+ .settimeout = bl602_settimeout,
+ .setcallback = bl602_setcallback,
+ .ioctl = NULL,
+};
+
+#ifdef CONFIG_BL602_TIMER0
+static struct bl602_lowerhalf_s g_tim1_lowerhalf =
+{
+ .ops = &g_timer_ops,
+ .irq = BL602_IRQ_TIMER_CH0,
+ .tim = TIMER_CH0,
+};
+#endif
+
+#ifdef CONFIG_BL602_TIMER1
+static struct bl602_lowerhalf_s g_tim2_lowerhalf =
+{
+ .ops = &g_timer_ops,
+ .irq = BL602_IRQ_TIMER_CH1,
+ .tim = TIMER_CH1,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_timer_handler
+ *
+ * Description:
+ * Timer interrupt handler
+ *
+ * Input Parameters:
+ *
+ * Returned Value:
+ *
+ ****************************************************************************/
+
+static int bl602_timer_handler(int irq, void *context, void *arg)
+{
+ FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)arg;
+ uint32_t next_interval_us = 0;
+
+ /* Clear Interrupt Bits */
+
+ uint32_t int_id;
+ uint32_t tmp_val;
+ uint32_t tmp_addr;
+
+ int_id = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * priv->tim);
+ tmp_addr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * priv->tim;
+ tmp_val = BL_RD_WORD(tmp_addr);
+
+ /* Comparator 0 match interrupt */
+
+ if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_0))
+ {
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_0));
+ if (priv->callback(&next_interval_us, priv->arg))
+ {
+ if (next_interval_us > 0)
+ {
+ /* Set a value to the alarm */
+
+ timer_disable(priv->tim);
+ timer_setcompvalue(
+ priv->tim, TIMER_COMP_ID_0, next_interval_us);
+ timer_setpreloadvalue(priv->tim, 0);
+ timer_enable(priv->tim);
+ }
+ }
+ else
+ {
+ timer_disable(priv->tim);
+ timer_setpreloadvalue(priv->tim, 0);
+ }
+ }
+
+ /* Comparator 1 match interrupt */
+
+ if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_1))
+ {
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_1));
+ }
+
+ /* Comparator 2 match interrupt */
+
+ if (BL_IS_REG_BIT_SET(int_id, TIMER_TMSR_2))
+ {
+ BL_WR_WORD(tmp_addr, BL_SET_REG_BIT(tmp_val, TIMER_TCLR_2));
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: bl602_start
+ *
+ * Description:
+ * Start the timer, resetting the time to the current timeout,
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int bl602_start(FAR struct timer_lowerhalf_s *lower)
+{
+ FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+
+ if (!priv->started)
+ {
+ if (priv->callback == NULL)
+ {
+ return -EPERM;
+ }
+
+ timer_setpreloadvalue(priv->tim, 0);
+ irq_attach(priv->irq, bl602_timer_handler, (void *)priv);
+ up_enable_irq(priv->irq);
+ timer_intmask(priv->tim, TIMER_INT_COMP_0, 0);
+ timer_enable(priv->tim);
+ priv->started = true;
+ return OK;
+ }
+
+ /* Return EBUSY to indicate that the timer was already running */
+
+ return -EBUSY;
+}
+
+/****************************************************************************
+ * Name: bl602_stop
+ *
+ * Description:
+ * Stop the timer
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the
+ * "lower-half" driver state structure.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int bl602_stop(FAR struct timer_lowerhalf_s *lower)
+{
+ FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+
+ /* timer disable */
+
+ if (priv->started)
+ {
+ timer_disable(priv->tim);
+ priv->started = false;
+ up_disable_irq(priv->irq);
+ timer_intmask(priv->tim, TIMER_INT_COMP_0, 1);
+ return OK;
+ }
+
+ /* Return ENODEV to indicate that the timer was not running */
+
+ return -ENODEV;
+}
+
+/****************************************************************************
+ * Name: bl602_getstatus
+ *
+ * Description:
+ * get timer status
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the "lower-
+ * half" driver state structure.
+ * status - The location to return the status information.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int bl602_getstatus(FAR struct timer_lowerhalf_s *lower,
+ FAR struct timer_status_s * status)
+{
+ FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+ uint32_t current_count;
+
+ status->timeout = timer_getcompvalue(priv->tim, TIMER_COMP_ID_0);
+ current_count = timer_getcountervalue(priv->tim);
+ if (current_count < status->timeout)
+ {
+ status->timeleft = status->timeout - current_count;
+ }
+ else
+ {
+ status->timeleft = 0;
+ }
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: bl602_settimeout
+ *
+ * Description:
+ * Set a new timeout value (and reset the timer)
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the
+ *"lower-half" driver state structure. timeout - The new timeout value in
+ *microseconds.
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+static int bl602_settimeout(FAR struct timer_lowerhalf_s *lower,
+ uint32_t timeout)
+{
+ FAR struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+
+ timer_setcompvalue(priv->tim, TIMER_COMP_ID_0, timeout);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: bl602_setcallback
+ *
+ * Description:
+ * Call this user provided timeout handler.
+ *
+ * Input Parameters:
+ * lower - A pointer the publicly visible representation of the
+ *"lower-half" driver state structure. callback - The new timer expiration
+ *function pointer. If this function pointer is NULL, then the
+ *reset-on-expiration behavior is restored, arg - Argument that will be
+ *provided in the callback
+ *
+ * Returned Value:
+ * The previous timer expiration function pointer or NULL is there was
+ * no previous function pointer.
+ *
+ ****************************************************************************/
+
+static void bl602_setcallback(FAR struct timer_lowerhalf_s *lower,
+ tccb_t callback,
+ FAR void * arg)
+{
+ struct bl602_lowerhalf_s *priv = (FAR struct bl602_lowerhalf_s *)lower;
+ irqstate_t flags = enter_critical_section();
+
+ /* Save the new callback */
+
+ priv->callback = callback;
+ priv->arg = arg;
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_timer_initialize
+ *
+ * Description:
+ * Bind the configuration timer to a timer lower half instance and
+ * register the timer drivers at 'devpath'
+ *
+ * Input Parameters:
+ * devpath - The full path to the timer device. This should be of the
+ * form /dev/timer0
+ * timer - the timer's number.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+int bl602_timer_initialize(FAR const char *devpath, int timer)
+{
+ FAR struct bl602_lowerhalf_s *lower;
+ timer_cfg_t timstr;
+
+ switch (timer)
+ {
+ case 0:
+#ifdef CONFIG_BL602_TIMER0
+ lower = &g_tim1_lowerhalf;
+#endif
+ break;
+ case 1:
+#ifdef CONFIG_BL602_TIMER1
+ lower = &g_tim2_lowerhalf;
+#endif
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ timstr.timer_ch = lower->tim; /* Timer channel */
+ timstr.clk_src = TIMER_CLKSRC_FCLK; /* Timer clock source */
+ timstr.pl_trig_src =
+ TIMER_PRELOAD_TRIG_COMP0; /* Timer count register preload trigger source
+ slelect */
+ timstr.count_mode = TIMER_COUNT_PRELOAD; /* Timer count mode */
+ timstr.clock_division = TIMER_CLK_DIV; /* Timer clock divison value */
+ timstr.match_val0 = TIMER_MAX_VALUE; /* Timer match 0 value 0 */
+ timstr.match_val1 = TIMER_MAX_VALUE; /* Timer match 1 value 0 */
+ timstr.match_val2 = TIMER_MAX_VALUE; /* Timer match 2 value 0 */
+ timstr.pre_load_val = TIMER_MAX_VALUE; /* Timer preload value */
+
+ glb_ahb_slave1_reset(BL_AHB_SLAVE1_TMR);
+
+ timer_intmask(lower->tim, TIMER_INT_ALL, 1);
+
+ /* timer disable */
+
+ timer_disable(lower->tim);
+
+ timer_init(&timstr);
+
+ /* Initialize the elements of lower half state structure */
+
+ lower->started = false;
+ lower->callback = NULL;
+
+ /* Register the timer driver as /dev/timerX. The returned value from
+ * timer_register is a handle that could be used with timer_unregister().
+ * REVISIT: The returned handle is discard here.
+ */
+
+ FAR void *drvr =
+ timer_register(devpath, (FAR struct timer_lowerhalf_s *)lower);
+ if (drvr == NULL)
+ {
+ /* The actual cause of the failure may have been a failure to allocate
+ * perhaps a failure to register the timer driver (such as if the
+ * 'depath' were not unique). We know here but we return EEXIST to
+ * indicate the failure (implying the non-unique devpath).
+ */
+
+ return -EEXIST;
+ }
+
+ return OK;
+}
diff --git a/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
new file mode 100644
index 0000000000..9b9eaea55d
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_tim_lowerhalf.h
@@ -0,0 +1,38 @@
+/**
+ * incubator-nuttx/arch/risc-v/src/bl602/bl602_lowerhalf.h
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARCH_RISCV_SRC_BL602_TIM_LOWERHALF_H
+#define __ARCH_RISCV_SRC_BL602_TIM_LOWERHALF_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <bl602_tim_lowerhalf.h>
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_timer_initialize
+ ****************************************************************************/
+
+int bl602_timer_initialize(FAR const char *devpath, uint8_t timer);
+
+#endif /* __ARCH_RISCV_SRC_BL602_TIM_LOWERHALF_H */
diff --git a/arch/risc-v/src/bl602/bl602_timerisr.c b/arch/risc-v/src/bl602/bl602_timerisr.c
new file mode 100644
index 0000000000..592681d9ef
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_timerisr.c
@@ -0,0 +1,156 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_timerisr.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/clock.h>
+#include <arch/board/board.h>
+
+#include "riscv_arch.h"
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define TICK_COUNT (160 * 1000 * 1000 / TICK_PER_SEC)
+#define CLINT_BASE_ADDRESS 0x02000000
+
+#define getreg64(a) (*(volatile uint64_t *)(a))
+#define putreg64(v, a) (*(volatile uint64_t *)(a) = (v))
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static bool _b_tick_started = false;
+
+#define MTIMER_HIGH (CLINT_BASE_ADDRESS + 0xBFFC)
+#define MTIMER_LOW (CLINT_BASE_ADDRESS + 0xBFF8)
+#define MTIMER_CMP (CLINT_BASE_ADDRESS + 0x4000)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/* bl602 mmio registers are a bit odd, by default they are byte-wide
+ * registers that are on 32-bit word boundaries. So a "32-bit" registers
+ * is actually broken into four bytes spanning a total address space of
+ * 16 bytes.
+ */
+
+static inline uint64_t bl602_clint_time_read(void)
+{
+ uint64_t r = getreg32(MTIMER_HIGH);
+ r <<= 32;
+ r |= getreg32(MTIMER_LOW);
+
+ return r;
+}
+
+static inline uint64_t bl602_clint_time_cmp_read(void)
+{
+ return getreg64(MTIMER_CMP);
+}
+
+static inline void bl602_clint_time_cmp_write(uint64_t v)
+{
+ putreg64(v, MTIMER_CMP);
+}
+
+/****************************************************************************
+ * Name: bl602_reload_mtimecmp
+ ****************************************************************************/
+
+static void bl602_reload_mtimecmp(void)
+{
+ irqstate_t flags = spin_lock_irqsave();
+
+ uint64_t current;
+ uint64_t next;
+
+ if (!_b_tick_started)
+ {
+ _b_tick_started = true;
+ current = bl602_clint_time_read();
+ }
+ else
+ {
+ current = bl602_clint_time_cmp_read();
+ }
+
+ next = current + TICK_COUNT;
+
+ bl602_clint_time_cmp_write(next);
+
+ spin_unlock_irqrestore(flags);
+}
+
+/****************************************************************************
+ * Name: bl602_timerisr
+ ****************************************************************************/
+
+static int bl602_timerisr(int irq, void *context, FAR void *arg)
+{
+ bl602_reload_mtimecmp();
+
+ /* Process timer interrupt */
+
+ nxsched_process_timer();
+ return 0;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_timer_initialize
+ *
+ * Description:
+ * This function is called during start-up to initialize
+ * the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+ /* Attach timer interrupt handler */
+
+ irq_attach(BL602_IRQ_MTIMER, bl602_timerisr, NULL);
+
+ /* Reload CLINT mtimecmp */
+
+ bl602_reload_mtimecmp();
+
+ /* And enable the timer interrupt */
+
+ up_enable_irq(BL602_IRQ_MTIMER);
+}
diff --git a/arch/risc-v/src/bl602/bl602_vectors.S b/arch/risc-v/src/bl602/bl602_vectors.S
new file mode 100644
index 0000000000..2c09068533
--- /dev/null
+++ b/arch/risc-v/src/bl602/bl602_vectors.S
@@ -0,0 +1,42 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/bl602_vectors.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+ .section .init
+ .global __reset_vec
+ .global __trap_vec
+
+/****************************************************************************
+ * Name: __reset_vec
+ ****************************************************************************/
+
+__reset_vec:
+ jal __start
+
+/****************************************************************************
+ * Name: exception_common
+ ****************************************************************************/
+
+__trap_vec:
+ j exception_common
+ nop
diff --git a/arch/risc-v/src/bl602/chip.h b/arch/risc-v/src/bl602/chip.h
new file mode 100644
index 0000000000..e428757bde
--- /dev/null
+++ b/arch/risc-v/src/bl602/chip.h
@@ -0,0 +1,36 @@
+/****************************************************************************
+ * arch/risc-v/include/bl602/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_BL602_CHIP_H
+#define __ARCH_RISCV_INCLUDE_BL602_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <arch/irq.h>
+#include "riscv_internal.h"
+
+#endif /* __ARCH_RISCV_INCLUDE_BL602_CHIP_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_common.h b/arch/risc-v/src/bl602/hardware/bl602_common.h
new file mode 100644
index 0000000000..7b41b64718
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_common.h
@@ -0,0 +1,231 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_common.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BL602_FLASH_XIP_BASE 0x23000000
+#define BL602_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024)
+#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000
+#define BL602_FLASH_XIP_REMAP0_END (0x33000000 + 16 * 1024 * 1024)
+#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000
+#define BL602_FLASH_XIP_REMAP1_END (0x43000000 + 16 * 1024 * 1024)
+#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000
+#define BL602_FLASH_XIP_REMAP2_END (0x53000000 + 16 * 1024 * 1024)
+
+#define BL602_WRAM_BASE 0x42020000
+#define BL602_WRAM_END (0x42020000 + 176 * 1024)
+#define BL602_WRAM_REMAP0_BASE 0x22020000
+#define BL602_WRAM_REMAP0_END (0x22020000 + 176 * 1024)
+#define BL602_WRAM_REMAP1_BASE 0x32020000
+#define BL602_WRAM_REMAP1_END (0x32020000 + 176 * 1024)
+#define BL602_WRAM_REMAP2_BASE 0x52020000
+#define BL602_WRAM_REMAP2_END (0x52020000 + 176 * 1024)
+
+#define BL602_TCM_BASE 0x22008000
+#define BL602_TCM_END (0x22008000 + (96 + 176) * 1024)
+#define BL602_TCM_REMAP0_BASE 0x32008000
+#define BL602_TCM_REMAP0_END (0x32008000 + (96 + 176) * 1024)
+#define BL602_TCM_REMAP1_BASE 0x42008000
+#define BL602_TCM_REMAP1_END (0x42008000 + (96 + 176) * 1024)
+#define BL602_TCM_REMAP2_BASE 0x52008000
+#define BL602_TCM_REMAP2_END (0x52008000 + (96 + 176) * 1024)
+
+/* BL602 peripherals base address */
+
+#define GLB_BASE ((uint32_t)0x40000000)
+#define RF_BASE ((uint32_t)0x40001000)
+
+/* AUX module base address */
+
+#define GPIP_BASE ((uint32_t)0x40002000)
+
+/* Security Debug module base address */
+
+#define SEC_DBG_BASE ((uint32_t)0x40003000)
+
+/* Security Engine module base address */
+
+#define SEC_ENG_BASE ((uint32_t)0x40004000)
+
+/* Trustzone control security base address */
+
+#define TZC_SEC_BASE ((uint32_t)0x40005000)
+
+/* Trustzone control none-security base address */
+
+#define TZC_NSEC_BASE ((uint32_t)0x40006000)
+#define EF_DATA_BASE ((uint32_t)0x40007000)
+#define EF_CTRL_BASE ((uint32_t)0x40007000)
+#define CCI_BASE ((uint32_t)0x40008000)
+
+/* L1 cache config base address */
+
+#define L1C_BASE ((uint32_t)0x40009000)
+#define UART0_BASE ((uint32_t)0x4000A000)
+#define UART1_BASE ((uint32_t)0x4000A100)
+#define SPI_BASE ((uint32_t)0x4000A200)
+#define I2C_BASE ((uint32_t)0x4000A300)
+#define PWM_BASE ((uint32_t)0x4000A400)
+#define TIMER_BASE ((uint32_t)0x4000A500)
+#define IR_BASE ((uint32_t)0x4000A600)
+#define SF_CTRL_BASE ((uint32_t)0x4000B000)
+#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
+#define DMA_BASE ((uint32_t)0x4000C000)
+#define SDU_BASE ((uint32_t)0x4000D000)
+
+/* Power down sleep module base address */
+
+#define PDS_BASE ((uint32_t)0x4000E000)
+
+/* Hibernate module base address */
+
+#define HBN_BASE ((uint32_t)0x4000F000)
+
+/* Always on module base address */
+
+#define AON_BASE ((uint32_t)0x4000F000)
+#define HBN_RAM_BASE ((uint32_t)0x40010000)
+
+#define BL_RD_WORD(addr) (*((volatile uint32_t *)(addr)))
+#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(addr)) = (val))
+#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(addr)))
+#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(addr)) = (val))
+#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(addr)))
+#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(addr)) = (val))
+#define BL_RDWD_FRM_BYTEP(p) \
+ ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+#define BL_WRWD_TO_BYTEP(p, val) \
+ { \
+ p[0] = val & 0xff; \
+ p[1] = (val >> 8) & 0xff; \
+ p[2] = (val >> 16) & 0xff; \
+ p[3] = (val >> 24) & 0xff; \
+ }
+/**
+ * @brief Register access macro
+ */
+#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET)
+#define BL_WR_REG16(addr, regname, val) \
+ BL_WR_SHORT(addr + regname##_OFFSET, val)
+#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET)
+#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val)
+#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS))
+#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK)
+#define BL_GET_REG_BITS_VAL(val, bitname) \
+ (((val)&bitname##_MSK) >> bitname##_POS)
+#define BL_SET_REG_BITS_VAL(val, bitname, bitval) \
+ (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
+#define BL_IS_REG_BIT_SET(val, bitname) \
+ (((val) & (1U << (bitname##_POS))) != 0)
+#define __NOP() \
+ __asm volatile("nop") /* This implementation generates debug information \
+ */
+#define BL_DRV_DUMMY \
+ { \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ __NOP(); \
+ }
+
+/* Std driver attribute macro */
+
+#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code")))
+#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const")))
+#define ATTR_TCM_SECTION __attribute__((section(".tcm_code")))
+#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const")))
+#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data")))
+#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code")))
+#define SystemCoreClockSet(val) BL_WR_WORD(0x4000f108, val)
+#define SystemCoreClockGet(val) BL_RD_WORD(0x4000f108)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+enum bl_ahb_slave1_e
+{
+ BL_AHB_SLAVE1_GLB = 0x00,
+ BL_AHB_SLAVE1_RF = 0x01,
+ BL_AHB_SLAVE1_GPIP_PHY_AGC = 0x02,
+ BL_AHB_SLAVE1_SEC_DBG = 0x03,
+ BL_AHB_SLAVE1_SEC = 0x04,
+ BL_AHB_SLAVE1_TZ1 = 0x05,
+ BL_AHB_SLAVE1_TZ2 = 0x06,
+ BL_AHB_SLAVE1_EFUSE = 0x07,
+ BL_AHB_SLAVE1_CCI = 0x08,
+ BL_AHB_SLAVE1_L1C = 0x09,
+ BL_AHB_SLAVE1_RSVD0A = 0x0a,
+ BL_AHB_SLAVE1_SFC = 0x0b,
+ BL_AHB_SLAVE1_DMA = 0x0c,
+ BL_AHB_SLAVE1_SDU = 0x0d,
+ BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0e,
+ BL_AHB_SLAVE1_RSVD0F = 0x0f,
+ BL_AHB_SLAVE1_UART0 = 0x10,
+ BL_AHB_SLAVE1_UART1 = 0x11,
+ BL_AHB_SLAVE1_SPI = 0x12,
+ BL_AHB_SLAVE1_I2C = 0x13,
+ BL_AHB_SLAVE1_PWM = 0x14,
+ BL_AHB_SLAVE1_TMR = 0x15,
+ BL_AHB_SLAVE1_IRR = 0x16,
+ BL_AHB_SLAVE1_CKS = 0x17,
+ BL_AHB_SLAVE1_MAX = 0x18,
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_COMMON_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_glb.h b/arch/risc-v/src/bl602/hardware/bl602_glb.h
new file mode 100644
index 0000000000..d99514e59d
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_glb.h
@@ -0,0 +1,5836 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_glb.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GLB_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GLB_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hardware/bl602_common.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* 0x0 : clk_cfg0 */
+
+#define GLB_CLK_CFG0_OFFSET (0x0)
+#define GLB_REG_PLL_EN GLB_REG_PLL_EN
+#define GLB_REG_PLL_EN_POS (0U)
+#define GLB_REG_PLL_EN_LEN (1U)
+#define GLB_REG_PLL_EN_MSK \
+ (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
+#define GLB_REG_PLL_EN_UMSK \
+ (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
+#define GLB_REG_FCLK_EN GLB_REG_FCLK_EN
+#define GLB_REG_FCLK_EN_POS (1U)
+#define GLB_REG_FCLK_EN_LEN (1U)
+#define GLB_REG_FCLK_EN_MSK \
+ (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
+#define GLB_REG_FCLK_EN_UMSK \
+ (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
+#define GLB_REG_HCLK_EN GLB_REG_HCLK_EN
+#define GLB_REG_HCLK_EN_POS (2U)
+#define GLB_REG_HCLK_EN_LEN (1U)
+#define GLB_REG_HCLK_EN_MSK \
+ (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
+#define GLB_REG_HCLK_EN_UMSK \
+ (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
+#define GLB_REG_BCLK_EN GLB_REG_BCLK_EN
+#define GLB_REG_BCLK_EN_POS (3U)
+#define GLB_REG_BCLK_EN_LEN (1U)
+#define GLB_REG_BCLK_EN_MSK \
+ (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
+#define GLB_REG_BCLK_EN_UMSK \
+ (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
+#define GLB_REG_PLL_SEL GLB_REG_PLL_SEL
+#define GLB_REG_PLL_SEL_POS (4U)
+#define GLB_REG_PLL_SEL_LEN (2U)
+#define GLB_REG_PLL_SEL_MSK \
+ (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)
+#define GLB_REG_PLL_SEL_UMSK \
+ (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS))
+#define GLB_HBN_ROOT_CLK_SEL GLB_HBN_ROOT_CLK_SEL
+#define GLB_HBN_ROOT_CLK_SEL_POS (6U)
+#define GLB_HBN_ROOT_CLK_SEL_LEN (2U)
+#define GLB_HBN_ROOT_CLK_SEL_MSK \
+ (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
+#define GLB_HBN_ROOT_CLK_SEL_UMSK \
+ (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
+#define GLB_REG_HCLK_DIV GLB_REG_HCLK_DIV
+#define GLB_REG_HCLK_DIV_POS (8U)
+#define GLB_REG_HCLK_DIV_LEN (8U)
+#define GLB_REG_HCLK_DIV_MSK \
+ (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
+#define GLB_REG_HCLK_DIV_UMSK \
+ (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
+#define GLB_REG_BCLK_DIV GLB_REG_BCLK_DIV
+#define GLB_REG_BCLK_DIV_POS (16U)
+#define GLB_REG_BCLK_DIV_LEN (8U)
+#define GLB_REG_BCLK_DIV_MSK \
+ (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
+#define GLB_REG_BCLK_DIV_UMSK \
+ (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
+#define GLB_FCLK_SW_STATE GLB_FCLK_SW_STATE
+#define GLB_FCLK_SW_STATE_POS (24U)
+#define GLB_FCLK_SW_STATE_LEN (3U)
+#define GLB_FCLK_SW_STATE_MSK \
+ (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
+#define GLB_FCLK_SW_STATE_UMSK \
+ (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
+#define GLB_CHIP_RDY GLB_CHIP_RDY
+#define GLB_CHIP_RDY_POS (27U)
+#define GLB_CHIP_RDY_LEN (1U)
+#define GLB_CHIP_RDY_MSK (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
+#define GLB_CHIP_RDY_UMSK \
+ (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
+#define GLB_ID GLB_ID
+#define GLB_ID_POS (28U)
+#define GLB_ID_LEN (4U)
+#define GLB_ID_MSK (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)
+#define GLB_ID_UMSK (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS))
+
+/* 0x4 : clk_cfg1 */
+
+#define GLB_CLK_CFG1_OFFSET (0x4)
+#define GLB_WIFI_MAC_CORE_DIV GLB_WIFI_MAC_CORE_DIV
+#define GLB_WIFI_MAC_CORE_DIV_POS (0U)
+#define GLB_WIFI_MAC_CORE_DIV_LEN (4U)
+#define GLB_WIFI_MAC_CORE_DIV_MSK \
+ (((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS)
+#define GLB_WIFI_MAC_CORE_DIV_UMSK \
+ (~(((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS))
+#define GLB_WIFI_MAC_WT_DIV GLB_WIFI_MAC_WT_DIV
+#define GLB_WIFI_MAC_WT_DIV_POS (4U)
+#define GLB_WIFI_MAC_WT_DIV_LEN (4U)
+#define GLB_WIFI_MAC_WT_DIV_MSK \
+ (((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS)
+#define GLB_WIFI_MAC_WT_DIV_UMSK \
+ (~(((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS))
+#define GLB_BLE_CLK_SEL GLB_BLE_CLK_SEL
+#define GLB_BLE_CLK_SEL_POS (16U)
+#define GLB_BLE_CLK_SEL_LEN (6U)
+#define GLB_BLE_CLK_SEL_MSK \
+ (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)
+#define GLB_BLE_CLK_SEL_UMSK \
+ (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS))
+#define GLB_BLE_EN GLB_BLE_EN
+#define GLB_BLE_EN_POS (24U)
+#define GLB_BLE_EN_LEN (1U)
+#define GLB_BLE_EN_MSK (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)
+#define GLB_BLE_EN_UMSK (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS))
+
+/* 0x8 : clk_cfg2 */
+
+#define GLB_CLK_CFG2_OFFSET (0x8)
+#define GLB_UART_CLK_DIV GLB_UART_CLK_DIV
+#define GLB_UART_CLK_DIV_POS (0U)
+#define GLB_UART_CLK_DIV_LEN (3U)
+#define GLB_UART_CLK_DIV_MSK \
+ (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
+#define GLB_UART_CLK_DIV_UMSK \
+ (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
+#define GLB_UART_CLK_EN GLB_UART_CLK_EN
+#define GLB_UART_CLK_EN_POS (4U)
+#define GLB_UART_CLK_EN_LEN (1U)
+#define GLB_UART_CLK_EN_MSK \
+ (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
+#define GLB_UART_CLK_EN_UMSK \
+ (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
+#define GLB_HBN_UART_CLK_SEL GLB_HBN_UART_CLK_SEL
+#define GLB_HBN_UART_CLK_SEL_POS (7U)
+#define GLB_HBN_UART_CLK_SEL_LEN (1U)
+#define GLB_HBN_UART_CLK_SEL_MSK \
+ (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
+#define GLB_HBN_UART_CLK_SEL_UMSK \
+ (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
+#define GLB_SF_CLK_DIV GLB_SF_CLK_DIV
+#define GLB_SF_CLK_DIV_POS (8U)
+#define GLB_SF_CLK_DIV_LEN (3U)
+#define GLB_SF_CLK_DIV_MSK \
+ (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
+#define GLB_SF_CLK_DIV_UMSK \
+ (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
+#define GLB_SF_CLK_EN GLB_SF_CLK_EN
+#define GLB_SF_CLK_EN_POS (11U)
+#define GLB_SF_CLK_EN_LEN (1U)
+#define GLB_SF_CLK_EN_MSK \
+ (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
+#define GLB_SF_CLK_EN_UMSK \
+ (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
+#define GLB_SF_CLK_SEL GLB_SF_CLK_SEL
+#define GLB_SF_CLK_SEL_POS (12U)
+#define GLB_SF_CLK_SEL_LEN (2U)
+#define GLB_SF_CLK_SEL_MSK \
+ (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
+#define GLB_SF_CLK_SEL_UMSK \
+ (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
+#define GLB_SF_CLK_SEL2 GLB_SF_CLK_SEL2
+#define GLB_SF_CLK_SEL2_POS (14U)
+#define GLB_SF_CLK_SEL2_LEN (2U)
+#define GLB_SF_CLK_SEL2_MSK \
+ (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
+#define GLB_SF_CLK_SEL2_UMSK \
+ (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
+#define GLB_IR_CLK_DIV GLB_IR_CLK_DIV
+#define GLB_IR_CLK_DIV_POS (16U)
+#define GLB_IR_CLK_DIV_LEN (6U)
+#define GLB_IR_CLK_DIV_MSK \
+ (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
+#define GLB_IR_CLK_DIV_UMSK \
+ (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
+#define GLB_IR_CLK_EN GLB_IR_CLK_EN
+#define GLB_IR_CLK_EN_POS (23U)
+#define GLB_IR_CLK_EN_LEN (1U)
+#define GLB_IR_CLK_EN_MSK \
+ (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
+#define GLB_IR_CLK_EN_UMSK \
+ (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
+#define GLB_DMA_CLK_EN GLB_DMA_CLK_EN
+#define GLB_DMA_CLK_EN_POS (24U)
+#define GLB_DMA_CLK_EN_LEN (8U)
+#define GLB_DMA_CLK_EN_MSK \
+ (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
+#define GLB_DMA_CLK_EN_UMSK \
+ (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))
+
+/* 0xC : clk_cfg3 */
+
+#define GLB_CLK_CFG3_OFFSET (0xC)
+#define GLB_SPI_CLK_DIV GLB_SPI_CLK_DIV
+#define GLB_SPI_CLK_DIV_POS (0U)
+#define GLB_SPI_CLK_DIV_LEN (5U)
+#define GLB_SPI_CLK_DIV_MSK \
+ (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
+#define GLB_SPI_CLK_DIV_UMSK \
+ (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
+#define GLB_SPI_CLK_EN GLB_SPI_CLK_EN
+#define GLB_SPI_CLK_EN_POS (8U)
+#define GLB_SPI_CLK_EN_LEN (1U)
+#define GLB_SPI_CLK_EN_MSK \
+ (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
+#define GLB_SPI_CLK_EN_UMSK \
+ (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
+#define GLB_I2C_CLK_DIV GLB_I2C_CLK_DIV
+#define GLB_I2C_CLK_DIV_POS (16U)
+#define GLB_I2C_CLK_DIV_LEN (8U)
+#define GLB_I2C_CLK_DIV_MSK \
+ (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
+#define GLB_I2C_CLK_DIV_UMSK \
+ (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
+#define GLB_I2C_CLK_EN GLB_I2C_CLK_EN
+#define GLB_I2C_CLK_EN_POS (24U)
+#define GLB_I2C_CLK_EN_LEN (1U)
+#define GLB_I2C_CLK_EN_MSK \
+ (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
+#define GLB_I2C_CLK_EN_UMSK \
+ (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
+
+/* 0x10 : swrst_cfg0 */
+
+#define GLB_SWRST_CFG0_OFFSET (0x10)
+#define GLB_SWRST_S00 GLB_SWRST_S00
+#define GLB_SWRST_S00_POS (0U)
+#define GLB_SWRST_S00_LEN (1U)
+#define GLB_SWRST_S00_MSK \
+ (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
+#define GLB_SWRST_S00_UMSK \
+ (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
+#define GLB_SWRST_S01 GLB_SWRST_S01
+#define GLB_SWRST_S01_POS (1U)
+#define GLB_SWRST_S01_LEN (1U)
+#define GLB_SWRST_S01_MSK \
+ (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
+#define GLB_SWRST_S01_UMSK \
+ (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
+#define GLB_SWRST_S20 GLB_SWRST_S20
+#define GLB_SWRST_S20_POS (4U)
+#define GLB_SWRST_S20_LEN (1U)
+#define GLB_SWRST_S20_MSK \
+ (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
+#define GLB_SWRST_S20_UMSK \
+ (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
+#define GLB_SWRST_S30 GLB_SWRST_S30
+#define GLB_SWRST_S30_POS (8U)
+#define GLB_SWRST_S30_LEN (1U)
+#define GLB_SWRST_S30_MSK \
+ (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
+#define GLB_SWRST_S30_UMSK \
+ (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))
+
+/* 0x14 : swrst_cfg1 */
+
+#define GLB_SWRST_CFG1_OFFSET (0x14)
+#define GLB_SWRST_S10 GLB_SWRST_S10
+#define GLB_SWRST_S10_POS (0U)
+#define GLB_SWRST_S10_LEN (1U)
+#define GLB_SWRST_S10_MSK \
+ (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
+#define GLB_SWRST_S10_UMSK \
+ (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
+#define GLB_SWRST_S11 GLB_SWRST_S11
+#define GLB_SWRST_S11_POS (1U)
+#define GLB_SWRST_S11_LEN (1U)
+#define GLB_SWRST_S11_MSK \
+ (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
+#define GLB_SWRST_S11_UMSK \
+ (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
+#define GLB_SWRST_S12 GLB_SWRST_S12
+#define GLB_SWRST_S12_POS (2U)
+#define GLB_SWRST_S12_LEN (1U)
+#define GLB_SWRST_S12_MSK \
+ (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
+#define GLB_SWRST_S12_UMSK \
+ (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
+#define GLB_SWRST_S13 GLB_SWRST_S13
+#define GLB_SWRST_S13_POS (3U)
+#define GLB_SWRST_S13_LEN (1U)
+#define GLB_SWRST_S13_MSK \
+ (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
+#define GLB_SWRST_S13_UMSK \
+ (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
+#define GLB_SWRST_S14 GLB_SWRST_S14
+#define GLB_SWRST_S14_POS (4U)
+#define GLB_SWRST_S14_LEN (1U)
+#define GLB_SWRST_S14_MSK \
+ (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
+#define GLB_SWRST_S14_UMSK \
+ (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
+#define GLB_SWRST_S15 GLB_SWRST_S15
+#define GLB_SWRST_S15_POS (5U)
+#define GLB_SWRST_S15_LEN (1U)
+#define GLB_SWRST_S15_MSK \
+ (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
+#define GLB_SWRST_S15_UMSK \
+ (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
+#define GLB_SWRST_S16 GLB_SWRST_S16
+#define GLB_SWRST_S16_POS (6U)
+#define GLB_SWRST_S16_LEN (1U)
+#define GLB_SWRST_S16_MSK \
+ (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
+#define GLB_SWRST_S16_UMSK \
+ (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
+#define GLB_SWRST_S17 GLB_SWRST_S17
+#define GLB_SWRST_S17_POS (7U)
+#define GLB_SWRST_S17_LEN (1U)
+#define GLB_SWRST_S17_MSK \
+ (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
+#define GLB_SWRST_S17_UMSK \
+ (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
+#define GLB_SWRST_S18 GLB_SWRST_S18
+#define GLB_SWRST_S18_POS (8U)
+#define GLB_SWRST_S18_LEN (1U)
+#define GLB_SWRST_S18_MSK \
+ (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
+#define GLB_SWRST_S18_UMSK \
+ (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
+#define GLB_SWRST_S19 GLB_SWRST_S19
+#define GLB_SWRST_S19_POS (9U)
+#define GLB_SWRST_S19_LEN (1U)
+#define GLB_SWRST_S19_MSK \
+ (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
+#define GLB_SWRST_S19_UMSK \
+ (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
+#define GLB_SWRST_S1A GLB_SWRST_S1A
+#define GLB_SWRST_S1A_POS (10U)
+#define GLB_SWRST_S1A_LEN (1U)
+#define GLB_SWRST_S1A_MSK \
+ (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
+#define GLB_SWRST_S1A_UMSK \
+ (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
+#define GLB_SWRST_S1B GLB_SWRST_S1B
+#define GLB_SWRST_S1B_POS (11U)
+#define GLB_SWRST_S1B_LEN (1U)
+#define GLB_SWRST_S1B_MSK \
+ (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
+#define GLB_SWRST_S1B_UMSK \
+ (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
+#define GLB_SWRST_S1C GLB_SWRST_S1C
+#define GLB_SWRST_S1C_POS (12U)
+#define GLB_SWRST_S1C_LEN (1U)
+#define GLB_SWRST_S1C_MSK \
+ (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
+#define GLB_SWRST_S1C_UMSK \
+ (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
+#define GLB_SWRST_S1D GLB_SWRST_S1D
+#define GLB_SWRST_S1D_POS (13U)
+#define GLB_SWRST_S1D_LEN (1U)
+#define GLB_SWRST_S1D_MSK \
+ (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
+#define GLB_SWRST_S1D_UMSK \
+ (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
+#define GLB_SWRST_S1E GLB_SWRST_S1E
+#define GLB_SWRST_S1E_POS (14U)
+#define GLB_SWRST_S1E_LEN (1U)
+#define GLB_SWRST_S1E_MSK \
+ (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
+#define GLB_SWRST_S1E_UMSK \
+ (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
+#define GLB_SWRST_S1F GLB_SWRST_S1F
+#define GLB_SWRST_S1F_POS (15U)
+#define GLB_SWRST_S1F_LEN (1U)
+#define GLB_SWRST_S1F_MSK \
+ (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
+#define GLB_SWRST_S1F_UMSK \
+ (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
+#define GLB_SWRST_S1A0 GLB_SWRST_S1A0
+#define GLB_SWRST_S1A0_POS (16U)
+#define GLB_SWRST_S1A0_LEN (1U)
+#define GLB_SWRST_S1A0_MSK \
+ (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
+#define GLB_SWRST_S1A0_UMSK \
+ (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
+#define GLB_SWRST_S1A1 GLB_SWRST_S1A1
+#define GLB_SWRST_S1A1_POS (17U)
+#define GLB_SWRST_S1A1_LEN (1U)
+#define GLB_SWRST_S1A1_MSK \
+ (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
+#define GLB_SWRST_S1A1_UMSK \
+ (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
+#define GLB_SWRST_S1A2 GLB_SWRST_S1A2
+#define GLB_SWRST_S1A2_POS (18U)
+#define GLB_SWRST_S1A2_LEN (1U)
+#define GLB_SWRST_S1A2_MSK \
+ (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
+#define GLB_SWRST_S1A2_UMSK \
+ (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
+#define GLB_SWRST_S1A3 GLB_SWRST_S1A3
+#define GLB_SWRST_S1A3_POS (19U)
+#define GLB_SWRST_S1A3_LEN (1U)
+#define GLB_SWRST_S1A3_MSK \
+ (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
+#define GLB_SWRST_S1A3_UMSK \
+ (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
+#define GLB_SWRST_S1A4 GLB_SWRST_S1A4
+#define GLB_SWRST_S1A4_POS (20U)
+#define GLB_SWRST_S1A4_LEN (1U)
+#define GLB_SWRST_S1A4_MSK \
+ (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
+#define GLB_SWRST_S1A4_UMSK \
+ (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
+#define GLB_SWRST_S1A5 GLB_SWRST_S1A5
+#define GLB_SWRST_S1A5_POS (21U)
+#define GLB_SWRST_S1A5_LEN (1U)
+#define GLB_SWRST_S1A5_MSK \
+ (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
+#define GLB_SWRST_S1A5_UMSK \
+ (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
+#define GLB_SWRST_S1A6 GLB_SWRST_S1A6
+#define GLB_SWRST_S1A6_POS (22U)
+#define GLB_SWRST_S1A6_LEN (1U)
+#define GLB_SWRST_S1A6_MSK \
+ (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
+#define GLB_SWRST_S1A6_UMSK \
+ (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
+#define GLB_SWRST_S1A7 GLB_SWRST_S1A7
+#define GLB_SWRST_S1A7_POS (23U)
+#define GLB_SWRST_S1A7_LEN (1U)
+#define GLB_SWRST_S1A7_MSK \
+ (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
+#define GLB_SWRST_S1A7_UMSK \
+ (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
+
+/* 0x18 : swrst_cfg2 */
+
+#define GLB_SWRST_CFG2_OFFSET (0x18)
+#define GLB_REG_CTRL_PWRON_RST GLB_REG_CTRL_PWRON_RST
+#define GLB_REG_CTRL_PWRON_RST_POS (0U)
+#define GLB_REG_CTRL_PWRON_RST_LEN (1U)
+#define GLB_REG_CTRL_PWRON_RST_MSK \
+ (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
+#define GLB_REG_CTRL_PWRON_RST_UMSK \
+ (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
+#define GLB_REG_CTRL_CPU_RESET GLB_REG_CTRL_CPU_RESET
+#define GLB_REG_CTRL_CPU_RESET_POS (1U)
+#define GLB_REG_CTRL_CPU_RESET_LEN (1U)
+#define GLB_REG_CTRL_CPU_RESET_MSK \
+ (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
+#define GLB_REG_CTRL_CPU_RESET_UMSK \
+ (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
+#define GLB_REG_CTRL_SYS_RESET GLB_REG_CTRL_SYS_RESET
+#define GLB_REG_CTRL_SYS_RESET_POS (2U)
+#define GLB_REG_CTRL_SYS_RESET_LEN (1U)
+#define GLB_REG_CTRL_SYS_RESET_MSK \
+ (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
+#define GLB_REG_CTRL_SYS_RESET_UMSK \
+ (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
+#define GLB_REG_CTRL_RESET_DUMMY GLB_REG_CTRL_RESET_DUMMY
+#define GLB_REG_CTRL_RESET_DUMMY_POS (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_LEN (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_MSK \
+ (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
+#define GLB_REG_CTRL_RESET_DUMMY_UMSK \
+ (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) \
+ << GLB_REG_CTRL_RESET_DUMMY_POS))
+#define GLB_PKA_CLK_SEL GLB_PKA_CLK_SEL
+#define GLB_PKA_CLK_SEL_POS (24U)
+#define GLB_PKA_CLK_SEL_LEN (1U)
+#define GLB_PKA_CLK_SEL_MSK \
+ (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
+#define GLB_PKA_CLK_SEL_UMSK \
+ (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))
+
+/* 0x1C : swrst_cfg3 */
+
+#define GLB_SWRST_CFG3_OFFSET (0x1C)
+
+/* 0x20 : cgen_cfg0 */
+
+#define GLB_CGEN_CFG0_OFFSET (0x20)
+#define GLB_CGEN_M GLB_CGEN_M
+#define GLB_CGEN_M_POS (0U)
+#define GLB_CGEN_M_LEN (8U)
+#define GLB_CGEN_M_MSK (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)
+#define GLB_CGEN_M_UMSK (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS))
+
+/* 0x24 : cgen_cfg1 */
+
+#define GLB_CGEN_CFG1_OFFSET (0x24)
+#define GLB_CGEN_S1 GLB_CGEN_S1
+#define GLB_CGEN_S1_POS (0U)
+#define GLB_CGEN_S1_LEN (16U)
+#define GLB_CGEN_S1_MSK (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)
+#define GLB_CGEN_S1_UMSK (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS))
+#define GLB_CGEN_S1A GLB_CGEN_S1A
+#define GLB_CGEN_S1A_POS (16U)
+#define GLB_CGEN_S1A_LEN (8U)
+#define GLB_CGEN_S1A_MSK (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)
+#define GLB_CGEN_S1A_UMSK \
+ (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS))
+
+/* 0x28 : cgen_cfg2 */
+
+#define GLB_CGEN_CFG2_OFFSET (0x28)
+#define GLB_CGEN_S2 GLB_CGEN_S2
+#define GLB_CGEN_S2_POS (0U)
+#define GLB_CGEN_S2_LEN (1U)
+#define GLB_CGEN_S2_MSK (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)
+#define GLB_CGEN_S2_UMSK (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS))
+#define GLB_CGEN_S3 GLB_CGEN_S3
+#define GLB_CGEN_S3_POS (4U)
+#define GLB_CGEN_S3_LEN (1U)
+#define GLB_CGEN_S3_MSK (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)
+#define GLB_CGEN_S3_UMSK (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS))
+
+/* 0x2C : cgen_cfg3 */
+
+#define GLB_CGEN_CFG3_OFFSET (0x2C)
+
+/* 0x30 : MBIST_CTL */
+
+#define GLB_MBIST_CTL_OFFSET (0x30)
+#define GLB_IROM_MBIST_MODE GLB_IROM_MBIST_MODE
+#define GLB_IROM_MBIST_MODE_POS (0U)
+#define GLB_IROM_MBIST_MODE_LEN (1U)
+#define GLB_IROM_MBIST_MODE_MSK \
+ (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)
+#define GLB_IROM_MBIST_MODE_UMSK \
+ (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS))
+#define GLB_HSRAM_MBIST_MODE GLB_HSRAM_MBIST_MODE
+#define GLB_HSRAM_MBIST_MODE_POS (1U)
+#define GLB_HSRAM_MBIST_MODE_LEN (1U)
+#define GLB_HSRAM_MBIST_MODE_MSK \
+ (((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS)
+#define GLB_HSRAM_MBIST_MODE_UMSK \
+ (~(((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS))
+#define GLB_TAG_MBIST_MODE GLB_TAG_MBIST_MODE
+#define GLB_TAG_MBIST_MODE_POS (2U)
+#define GLB_TAG_MBIST_MODE_LEN (1U)
+#define GLB_TAG_MBIST_MODE_MSK \
+ (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)
+#define GLB_TAG_MBIST_MODE_UMSK \
+ (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS))
+#define GLB_OCRAM_MBIST_MODE GLB_OCRAM_MBIST_MODE
+#define GLB_OCRAM_MBIST_MODE_POS (3U)
+#define GLB_OCRAM_MBIST_MODE_LEN (1U)
+#define GLB_OCRAM_MBIST_MODE_MSK \
+ (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)
+#define GLB_OCRAM_MBIST_MODE_UMSK \
+ (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS))
+#define GLB_WIFI_MBIST_MODE GLB_WIFI_MBIST_MODE
+#define GLB_WIFI_MBIST_MODE_POS (4U)
+#define GLB_WIFI_MBIST_MODE_LEN (1U)
+#define GLB_WIFI_MBIST_MODE_MSK \
+ (((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS)
+#define GLB_WIFI_MBIST_MODE_UMSK \
+ (~(((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS))
+#define GLB_REG_MBIST_RST_N GLB_REG_MBIST_RST_N
+#define GLB_REG_MBIST_RST_N_POS (31U)
+#define GLB_REG_MBIST_RST_N_LEN (1U)
+#define GLB_REG_MBIST_RST_N_MSK \
+ (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)
+#define GLB_REG_MBIST_RST_N_UMSK \
+ (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS))
+
+/* 0x34 : MBIST_STAT */
+
+#define GLB_MBIST_STAT_OFFSET (0x34)
+#define GLB_IROM_MBIST_DONE GLB_IROM_MBIST_DONE
+#define GLB_IROM_MBIST_DONE_POS (0U)
+#define GLB_IROM_MBIST_DONE_LEN (1U)
+#define GLB_IROM_MBIST_DONE_MSK \
+ (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)
+#define GLB_IROM_MBIST_DONE_UMSK \
+ (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS))
+#define GLB_HSRAM_MBIST_DONE GLB_HSRAM_MBIST_DONE
+#define GLB_HSRAM_MBIST_DONE_POS (1U)
+#define GLB_HSRAM_MBIST_DONE_LEN (1U)
+#define GLB_HSRAM_MBIST_DONE_MSK \
+ (((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS)
+#define GLB_HSRAM_MBIST_DONE_UMSK \
+ (~(((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS))
+#define GLB_TAG_MBIST_DONE GLB_TAG_MBIST_DONE
+#define GLB_TAG_MBIST_DONE_POS (2U)
+#define GLB_TAG_MBIST_DONE_LEN (1U)
+#define GLB_TAG_MBIST_DONE_MSK \
+ (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)
+#define GLB_TAG_MBIST_DONE_UMSK \
+ (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS))
+#define GLB_OCRAM_MBIST_DONE GLB_OCRAM_MBIST_DONE
+#define GLB_OCRAM_MBIST_DONE_POS (3U)
+#define GLB_OCRAM_MBIST_DONE_LEN (1U)
+#define GLB_OCRAM_MBIST_DONE_MSK \
+ (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)
+#define GLB_OCRAM_MBIST_DONE_UMSK \
+ (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS))
+#define GLB_WIFI_MBIST_DONE GLB_WIFI_MBIST_DONE
+#define GLB_WIFI_MBIST_DONE_POS (4U)
+#define GLB_WIFI_MBIST_DONE_LEN (1U)
+#define GLB_WIFI_MBIST_DONE_MSK \
+ (((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS)
+#define GLB_WIFI_MBIST_DONE_UMSK \
+ (~(((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS))
+#define GLB_IROM_MBIST_FAIL GLB_IROM_MBIST_FAIL
+#define GLB_IROM_MBIST_FAIL_POS (16U)
+#define GLB_IROM_MBIST_FAIL_LEN (1U)
+#define GLB_IROM_MBIST_FAIL_MSK \
+ (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)
+#define GLB_IROM_MBIST_FAIL_UMSK \
+ (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS))
+#define GLB_HSRAM_MBIST_FAIL GLB_HSRAM_MBIST_FAIL
+#define GLB_HSRAM_MBIST_FAIL_POS (17U)
+#define GLB_HSRAM_MBIST_FAIL_LEN (1U)
+#define GLB_HSRAM_MBIST_FAIL_MSK \
+ (((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS)
+#define GLB_HSRAM_MBIST_FAIL_UMSK \
+ (~(((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS))
+#define GLB_TAG_MBIST_FAIL GLB_TAG_MBIST_FAIL
+#define GLB_TAG_MBIST_FAIL_POS (18U)
+#define GLB_TAG_MBIST_FAIL_LEN (1U)
+#define GLB_TAG_MBIST_FAIL_MSK \
+ (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)
+#define GLB_TAG_MBIST_FAIL_UMSK \
+ (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS))
+#define GLB_OCRAM_MBIST_FAIL GLB_OCRAM_MBIST_FAIL
+#define GLB_OCRAM_MBIST_FAIL_POS (19U)
+#define GLB_OCRAM_MBIST_FAIL_LEN (1U)
+#define GLB_OCRAM_MBIST_FAIL_MSK \
+ (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)
+#define GLB_OCRAM_MBIST_FAIL_UMSK \
+ (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS))
+#define GLB_WIFI_MBIST_FAIL GLB_WIFI_MBIST_FAIL
+#define GLB_WIFI_MBIST_FAIL_POS (20U)
+#define GLB_WIFI_MBIST_FAIL_LEN (1U)
+#define GLB_WIFI_MBIST_FAIL_MSK \
+ (((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS)
+#define GLB_WIFI_MBIST_FAIL_UMSK \
+ (~(((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS))
+
+/* 0x50 : bmx_cfg1 */
+
+#define GLB_BMX_CFG1_OFFSET (0x50)
+#define GLB_BMX_TIMEOUT_EN GLB_BMX_TIMEOUT_EN
+#define GLB_BMX_TIMEOUT_EN_POS (0U)
+#define GLB_BMX_TIMEOUT_EN_LEN (4U)
+#define GLB_BMX_TIMEOUT_EN_MSK \
+ (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)
+#define GLB_BMX_TIMEOUT_EN_UMSK \
+ (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS))
+#define GLB_BMX_ARB_MODE GLB_BMX_ARB_MODE
+#define GLB_BMX_ARB_MODE_POS (4U)
+#define GLB_BMX_ARB_MODE_LEN (2U)
+#define GLB_BMX_ARB_MODE_MSK \
+ (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)
+#define GLB_BMX_ARB_MODE_UMSK \
+ (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS))
+#define GLB_BMX_ERR_EN GLB_BMX_ERR_EN
+#define GLB_BMX_ERR_EN_POS (8U)
+#define GLB_BMX_ERR_EN_LEN (1U)
+#define GLB_BMX_ERR_EN_MSK \
+ (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)
+#define GLB_BMX_ERR_EN_UMSK \
+ (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS))
+#define GLB_BMX_BUSY_OPTION_DIS GLB_BMX_BUSY_OPTION_DIS
+#define GLB_BMX_BUSY_OPTION_DIS_POS (9U)
+#define GLB_BMX_BUSY_OPTION_DIS_LEN (1U)
+#define GLB_BMX_BUSY_OPTION_DIS_MSK \
+ (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)
+#define GLB_BMX_BUSY_OPTION_DIS_UMSK \
+ (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) \
+ << GLB_BMX_BUSY_OPTION_DIS_POS))
+#define GLB_BMX_GATING_DIS GLB_BMX_GATING_DIS
+#define GLB_BMX_GATING_DIS_POS (10U)
+#define GLB_BMX_GATING_DIS_LEN (1U)
+#define GLB_BMX_GATING_DIS_MSK \
+ (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)
+#define GLB_BMX_GATING_DIS_UMSK \
+ (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS))
+#define GLB_HSEL_OPTION GLB_HSEL_OPTION
+#define GLB_HSEL_OPTION_POS (12U)
+#define GLB_HSEL_OPTION_LEN (4U)
+#define GLB_HSEL_OPTION_MSK \
+ (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)
+#define GLB_HSEL_OPTION_UMSK \
+ (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS))
+#define GLB_PDS_APB_CFG GLB_PDS_APB_CFG
+#define GLB_PDS_APB_CFG_POS (16U)
+#define GLB_PDS_APB_CFG_LEN (8U)
+#define GLB_PDS_APB_CFG_MSK \
+ (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
+#define GLB_PDS_APB_CFG_UMSK \
+ (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
+#define GLB_HBN_APB_CFG GLB_HBN_APB_CFG
+#define GLB_HBN_APB_CFG_POS (24U)
+#define GLB_HBN_APB_CFG_LEN (8U)
+#define GLB_HBN_APB_CFG_MSK \
+ (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
+#define GLB_HBN_APB_CFG_UMSK \
+ (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))
+
+/* 0x54 : bmx_cfg2 */
+
+#define GLB_BMX_CFG2_OFFSET (0x54)
+#define GLB_BMX_ERR_ADDR_DIS GLB_BMX_ERR_ADDR_DIS
+#define GLB_BMX_ERR_ADDR_DIS_POS (0U)
+#define GLB_BMX_ERR_ADDR_DIS_LEN (1U)
+#define GLB_BMX_ERR_ADDR_DIS_MSK \
+ (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)
+#define GLB_BMX_ERR_ADDR_DIS_UMSK \
+ (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS))
+#define GLB_BMX_ERR_DEC GLB_BMX_ERR_DEC
+#define GLB_BMX_ERR_DEC_POS (4U)
+#define GLB_BMX_ERR_DEC_LEN (1U)
+#define GLB_BMX_ERR_DEC_MSK \
+ (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)
+#define GLB_BMX_ERR_DEC_UMSK \
+ (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS))
+#define GLB_BMX_ERR_TZ GLB_BMX_ERR_TZ
+#define GLB_BMX_ERR_TZ_POS (5U)
+#define GLB_BMX_ERR_TZ_LEN (1U)
+#define GLB_BMX_ERR_TZ_MSK \
+ (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)
+#define GLB_BMX_ERR_TZ_UMSK \
+ (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS))
+#define GLB_BMX_DBG_SEL GLB_BMX_DBG_SEL
+#define GLB_BMX_DBG_SEL_POS (28U)
+#define GLB_BMX_DBG_SEL_LEN (4U)
+#define GLB_BMX_DBG_SEL_MSK \
+ (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
+#define GLB_BMX_DBG_SEL_UMSK \
+ (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))
+
+/* 0x58 : bmx_err_addr */
+
+#define GLB_BMX_ERR_ADDR_OFFSET (0x58)
+#define GLB_BMX_ERR_ADDR GLB_BMX_ERR_ADDR
+#define GLB_BMX_ERR_ADDR_POS (0U)
+#define GLB_BMX_ERR_ADDR_LEN (32U)
+#define GLB_BMX_ERR_ADDR_MSK \
+ (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)
+#define GLB_BMX_ERR_ADDR_UMSK \
+ (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS))
+
+/* 0x5C : bmx_dbg_out */
+
+#define GLB_BMX_DBG_OUT_OFFSET (0x5C)
+#define GLB_BMX_DBG_OUT GLB_BMX_DBG_OUT
+#define GLB_BMX_DBG_OUT_POS (0U)
+#define GLB_BMX_DBG_OUT_LEN (32U)
+#define GLB_BMX_DBG_OUT_MSK \
+ (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)
+#define GLB_BMX_DBG_OUT_UMSK \
+ (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS))
+
+/* 0x60 : rsv0 */
+
+#define GLB_RSV0_OFFSET (0x60)
+
+/* 0x64 : rsv1 */
+
+#define GLB_RSV1_OFFSET (0x64)
+
+/* 0x68 : rsv2 */
+
+#define GLB_RSV2_OFFSET (0x68)
+
+/* 0x6C : rsv3 */
+
+#define GLB_RSV3_OFFSET (0x6C)
+
+/* 0x70 : sram_ret */
+
+#define GLB_SRAM_RET_OFFSET (0x70)
+#define GLB_REG_SRAM_RET GLB_REG_SRAM_RET
+#define GLB_REG_SRAM_RET_POS (0U)
+#define GLB_REG_SRAM_RET_LEN (32U)
+#define GLB_REG_SRAM_RET_MSK \
+ (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)
+#define GLB_REG_SRAM_RET_UMSK \
+ (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS))
+
+/* 0x74 : sram_slp */
+
+#define GLB_SRAM_SLP_OFFSET (0x74)
+#define GLB_REG_SRAM_SLP GLB_REG_SRAM_SLP
+#define GLB_REG_SRAM_SLP_POS (0U)
+#define GLB_REG_SRAM_SLP_LEN (32U)
+#define GLB_REG_SRAM_SLP_MSK \
+ (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)
+#define GLB_REG_SRAM_SLP_UMSK \
+ (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS))
+
+/* 0x78 : sram_parm */
+
+#define GLB_SRAM_PARM_OFFSET (0x78)
+#define GLB_REG_SRAM_PARM GLB_REG_SRAM_PARM
+#define GLB_REG_SRAM_PARM_POS (0U)
+#define GLB_REG_SRAM_PARM_LEN (32U)
+#define GLB_REG_SRAM_PARM_MSK \
+ (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)
+#define GLB_REG_SRAM_PARM_UMSK \
+ (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS))
+
+/* 0x7C : seam_misc */
+
+#define GLB_SEAM_MISC_OFFSET (0x7C)
+#define GLB_EM_SEL GLB_EM_SEL
+#define GLB_EM_SEL_POS (0U)
+#define GLB_EM_SEL_LEN (4U)
+#define GLB_EM_SEL_MSK (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
+#define GLB_EM_SEL_UMSK (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))
+
+/* 0x80 : glb_parm */
+
+#define GLB_PARM_OFFSET (0x80)
+#define GLB_REG_BD_EN GLB_REG_BD_EN
+#define GLB_REG_BD_EN_POS (0U)
+#define GLB_REG_BD_EN_LEN (1U)
+#define GLB_REG_BD_EN_MSK \
+ (((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)
+#define GLB_REG_BD_EN_UMSK \
+ (~(((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS))
+#define GLB_REG_EXT_RST_SMT GLB_REG_EXT_RST_SMT
+#define GLB_REG_EXT_RST_SMT_POS (1U)
+#define GLB_REG_EXT_RST_SMT_LEN (1U)
+#define GLB_REG_EXT_RST_SMT_MSK \
+ (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)
+#define GLB_REG_EXT_RST_SMT_UMSK \
+ (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS))
+#define GLB_JTAG_SWAP_SET GLB_JTAG_SWAP_SET
+#define GLB_JTAG_SWAP_SET_POS (2U)
+#define GLB_JTAG_SWAP_SET_LEN (6U)
+#define GLB_JTAG_SWAP_SET_MSK \
+ (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)
+#define GLB_JTAG_SWAP_SET_UMSK \
+ (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS))
+#define GLB_SWAP_SFLASH_IO_3_IO_0 GLB_SWAP_SFLASH_IO_3_IO_0
+#define GLB_SWAP_SFLASH_IO_3_IO_0_POS (8U)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN (1U)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_MSK \
+ (((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \
+ << GLB_SWAP_SFLASH_IO_3_IO_0_POS)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_UMSK \
+ (~(((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) \
+ << GLB_SWAP_SFLASH_IO_3_IO_0_POS))
+#define GLB_SEL_EMBEDDED_SFLASH GLB_SEL_EMBEDDED_SFLASH
+#define GLB_SEL_EMBEDDED_SFLASH_POS (9U)
+#define GLB_SEL_EMBEDDED_SFLASH_LEN (1U)
+#define GLB_SEL_EMBEDDED_SFLASH_MSK \
+ (((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)
+#define GLB_SEL_EMBEDDED_SFLASH_UMSK \
+ (~(((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) \
+ << GLB_SEL_EMBEDDED_SFLASH_POS))
+#define GLB_REG_SPI_0_MASTER_MODE GLB_REG_SPI_0_MASTER_MODE
+#define GLB_REG_SPI_0_MASTER_MODE_POS (12U)
+#define GLB_REG_SPI_0_MASTER_MODE_LEN (1U)
+#define GLB_REG_SPI_0_MASTER_MODE_MSK \
+ (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \
+ << GLB_REG_SPI_0_MASTER_MODE_POS)
+#define GLB_REG_SPI_0_MASTER_MODE_UMSK \
+ (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) \
+ << GLB_REG_SPI_0_MASTER_MODE_POS))
+#define GLB_REG_SPI_0_SWAP GLB_REG_SPI_0_SWAP
+#define GLB_REG_SPI_0_SWAP_POS (13U)
+#define GLB_REG_SPI_0_SWAP_LEN (1U)
+#define GLB_REG_SPI_0_SWAP_MSK \
+ (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
+#define GLB_REG_SPI_0_SWAP_UMSK \
+ (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
+#define GLB_REG_CCI_USE_JTAG_PIN GLB_REG_CCI_USE_JTAG_PIN
+#define GLB_REG_CCI_USE_JTAG_PIN_POS (15U)
+#define GLB_REG_CCI_USE_JTAG_PIN_LEN (1U)
+#define GLB_REG_CCI_USE_JTAG_PIN_MSK \
+ (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)
+#define GLB_REG_CCI_USE_JTAG_PIN_UMSK \
+ (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) \
+ << GLB_REG_CCI_USE_JTAG_PIN_POS))
+#define GLB_REG_CCI_USE_SDIO_PIN GLB_REG_CCI_USE_SDIO_PIN
+#define GLB_REG_CCI_USE_SDIO_PIN_POS (16U)
+#define GLB_REG_CCI_USE_SDIO_PIN_LEN (1U)
+#define GLB_REG_CCI_USE_SDIO_PIN_MSK \
+ (((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS)
+#define GLB_REG_CCI_USE_SDIO_PIN_UMSK \
+ (~(((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) \
+ << GLB_REG_CCI_USE_SDIO_PIN_POS))
+#define GLB_P1_ADC_TEST_WITH_CCI GLB_P1_ADC_TEST_WITH_CCI
+#define GLB_P1_ADC_TEST_WITH_CCI_POS (17U)
+#define GLB_P1_ADC_TEST_WITH_CCI_LEN (1U)
+#define GLB_P1_ADC_TEST_WITH_CCI_MSK \
+ (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)
+#define GLB_P1_ADC_TEST_WITH_CCI_UMSK \
+ (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) \
+ << GLB_P1_ADC_TEST_WITH_CCI_POS))
+#define GLB_P2_DAC_TEST_WITH_CCI GLB_P2_DAC_TEST_WITH_CCI
+#define GLB_P2_DAC_TEST_WITH_CCI_POS (18U)
+#define GLB_P2_DAC_TEST_WITH_CCI_LEN (1U)
+#define GLB_P2_DAC_TEST_WITH_CCI_MSK \
+ (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)
+#define GLB_P2_DAC_TEST_WITH_CCI_UMSK \
+ (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) \
+ << GLB_P2_DAC_TEST_WITH_CCI_POS))
+#define GLB_P3_CCI_USE_IO_2_5 GLB_P3_CCI_USE_IO_2_5
+#define GLB_P3_CCI_USE_IO_2_5_POS (19U)
+#define GLB_P3_CCI_USE_IO_2_5_LEN (1U)
+#define GLB_P3_CCI_USE_IO_2_5_MSK \
+ (((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)
+#define GLB_P3_CCI_USE_IO_2_5_UMSK \
+ (~(((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS))
+#define GLB_P4_ADC_TEST_WITH_JTAG GLB_P4_ADC_TEST_WITH_JTAG
+#define GLB_P4_ADC_TEST_WITH_JTAG_POS (20U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_LEN (1U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_MSK \
+ (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \
+ << GLB_P4_ADC_TEST_WITH_JTAG_POS)
+#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK \
+ (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) \
+ << GLB_P4_ADC_TEST_WITH_JTAG_POS))
+#define GLB_P5_DAC_TEST_WITH_JTAG GLB_P5_DAC_TEST_WITH_JTAG
+#define GLB_P5_DAC_TEST_WITH_JTAG_POS (21U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_LEN (1U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_MSK \
+ (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \
+ << GLB_P5_DAC_TEST_WITH_JTAG_POS)
+#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK \
+ (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) \
+ << GLB_P5_DAC_TEST_WITH_JTAG_POS))
+#define GLB_P6_SDIO_USE_IO_0_5 GLB_P6_SDIO_USE_IO_0_5
+#define GLB_P6_SDIO_USE_IO_0_5_POS (22U)
+#define GLB_P6_SDIO_USE_IO_0_5_LEN (1U)
+#define GLB_P6_SDIO_USE_IO_0_5_MSK \
+ (((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS)
+#define GLB_P6_SDIO_USE_IO_0_5_UMSK \
+ (~(((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS))
+#define GLB_P7_JTAG_USE_IO_2_5 GLB_P7_JTAG_USE_IO_2_5
+#define GLB_P7_JTAG_USE_IO_2_5_POS (23U)
+#define GLB_P7_JTAG_USE_IO_2_5_LEN (1U)
+#define GLB_P7_JTAG_USE_IO_2_5_MSK \
+ (((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)
+#define GLB_P7_JTAG_USE_IO_2_5_UMSK \
+ (~(((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS))
+#define GLB_UART_SWAP_SET GLB_UART_SWAP_SET
+#define GLB_UART_SWAP_SET_POS (24U)
+#define GLB_UART_SWAP_SET_LEN (3U)
+#define GLB_UART_SWAP_SET_MSK \
+ (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
+#define GLB_UART_SWAP_SET_UMSK \
+ (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
+
+/* 0x90 : CPU_CLK_CFG */
+
+#define GLB_CPU_CLK_CFG_OFFSET (0x90)
+#define GLB_CPU_RTC_DIV GLB_CPU_RTC_DIV
+#define GLB_CPU_RTC_DIV_POS (0U)
+#define GLB_CPU_RTC_DIV_LEN (17U)
+#define GLB_CPU_RTC_DIV_MSK \
+ (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)
+#define GLB_CPU_RTC_DIV_UMSK \
+ (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS))
+#define GLB_CPU_RTC_EN GLB_CPU_RTC_EN
+#define GLB_CPU_RTC_EN_POS (18U)
+#define GLB_CPU_RTC_EN_LEN (1U)
+#define GLB_CPU_RTC_EN_MSK \
+ (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)
+#define GLB_CPU_RTC_EN_UMSK \
+ (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS))
+#define GLB_CPU_RTC_SEL GLB_CPU_RTC_SEL
+#define GLB_CPU_RTC_SEL_POS (19U)
+#define GLB_CPU_RTC_SEL_LEN (1U)
+#define GLB_CPU_RTC_SEL_MSK \
+ (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)
+#define GLB_CPU_RTC_SEL_UMSK \
+ (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS))
+#define GLB_DEBUG_NDRESET_GATE GLB_DEBUG_NDRESET_GATE
+#define GLB_DEBUG_NDRESET_GATE_POS (20U)
+#define GLB_DEBUG_NDRESET_GATE_LEN (1U)
+#define GLB_DEBUG_NDRESET_GATE_MSK \
+ (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
+#define GLB_DEBUG_NDRESET_GATE_UMSK \
+ (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))
+
+/* 0xA4 : GPADC_32M_SRC_CTRL */
+
+#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4)
+#define GLB_GPADC_32M_CLK_DIV GLB_GPADC_32M_CLK_DIV
+#define GLB_GPADC_32M_CLK_DIV_POS (0U)
+#define GLB_GPADC_32M_CLK_DIV_LEN (6U)
+#define GLB_GPADC_32M_CLK_DIV_MSK \
+ (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
+#define GLB_GPADC_32M_CLK_DIV_UMSK \
+ (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
+#define GLB_GPADC_32M_CLK_SEL GLB_GPADC_32M_CLK_SEL
+#define GLB_GPADC_32M_CLK_SEL_POS (7U)
+#define GLB_GPADC_32M_CLK_SEL_LEN (1U)
+#define GLB_GPADC_32M_CLK_SEL_MSK \
+ (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
+#define GLB_GPADC_32M_CLK_SEL_UMSK \
+ (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
+#define GLB_GPADC_32M_DIV_EN GLB_GPADC_32M_DIV_EN
+#define GLB_GPADC_32M_DIV_EN_POS (8U)
+#define GLB_GPADC_32M_DIV_EN_LEN (1U)
+#define GLB_GPADC_32M_DIV_EN_MSK \
+ (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
+#define GLB_GPADC_32M_DIV_EN_UMSK \
+ (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))
+
+/* 0xA8 : DIG32K_WAKEUP_CTRL */
+
+#define GLB_DIG32K_WAKEUP_CTRL_OFFSET (0xA8)
+#define GLB_DIG_32K_DIV GLB_DIG_32K_DIV
+#define GLB_DIG_32K_DIV_POS (0U)
+#define GLB_DIG_32K_DIV_LEN (11U)
+#define GLB_DIG_32K_DIV_MSK \
+ (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
+#define GLB_DIG_32K_DIV_UMSK \
+ (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
+#define GLB_DIG_32K_EN GLB_DIG_32K_EN
+#define GLB_DIG_32K_EN_POS (12U)
+#define GLB_DIG_32K_EN_LEN (1U)
+#define GLB_DIG_32K_EN_MSK \
+ (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
+#define GLB_DIG_32K_EN_UMSK \
+ (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
+#define GLB_DIG_32K_COMP GLB_DIG_32K_COMP
+#define GLB_DIG_32K_COMP_POS (13U)
+#define GLB_DIG_32K_COMP_LEN (1U)
+#define GLB_DIG_32K_COMP_MSK \
+ (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
+#define GLB_DIG_32K_COMP_UMSK \
+ (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
+#define GLB_DIG_512K_DIV GLB_DIG_512K_DIV
+#define GLB_DIG_512K_DIV_POS (16U)
+#define GLB_DIG_512K_DIV_LEN (7U)
+#define GLB_DIG_512K_DIV_MSK \
+ (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
+#define GLB_DIG_512K_DIV_UMSK \
+ (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
+#define GLB_DIG_512K_EN GLB_DIG_512K_EN
+#define GLB_DIG_512K_EN_POS (24U)
+#define GLB_DIG_512K_EN_LEN (1U)
+#define GLB_DIG_512K_EN_MSK \
+ (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
+#define GLB_DIG_512K_EN_UMSK \
+ (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
+#define GLB_DIG_512K_COMP GLB_DIG_512K_COMP
+#define GLB_DIG_512K_COMP_POS (25U)
+#define GLB_DIG_512K_COMP_LEN (1U)
+#define GLB_DIG_512K_COMP_MSK \
+ (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
+#define GLB_DIG_512K_COMP_UMSK \
+ (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
+#define GLB_DIG_CLK_SRC_SEL GLB_DIG_CLK_SRC_SEL
+#define GLB_DIG_CLK_SRC_SEL_POS (28U)
+#define GLB_DIG_CLK_SRC_SEL_LEN (1U)
+#define GLB_DIG_CLK_SRC_SEL_MSK \
+ (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
+#define GLB_DIG_CLK_SRC_SEL_UMSK \
+ (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
+#define GLB_REG_EN_PLATFORM_WAKEUP GLB_REG_EN_PLATFORM_WAKEUP
+#define GLB_REG_EN_PLATFORM_WAKEUP_POS (31U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_LEN (1U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_MSK \
+ (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \
+ << GLB_REG_EN_PLATFORM_WAKEUP_POS)
+#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK \
+ (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) \
+ << GLB_REG_EN_PLATFORM_WAKEUP_POS))
+
+/* 0xAC : WIFI_BT_COEX_CTRL */
+
+#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC)
+#define GLB_COEX_BT_CHANNEL GLB_COEX_BT_CHANNEL
+#define GLB_COEX_BT_CHANNEL_POS (0U)
+#define GLB_COEX_BT_CHANNEL_LEN (7U)
+#define GLB_COEX_BT_CHANNEL_MSK \
+ (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)
+#define GLB_COEX_BT_CHANNEL_UMSK \
+ (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS))
+#define GLB_COEX_BT_PTI GLB_COEX_BT_PTI
+#define GLB_COEX_BT_PTI_POS (7U)
+#define GLB_COEX_BT_PTI_LEN (4U)
+#define GLB_COEX_BT_PTI_MSK \
+ (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)
+#define GLB_COEX_BT_PTI_UMSK \
+ (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS))
+#define GLB_COEX_BT_BW GLB_COEX_BT_BW
+#define GLB_COEX_BT_BW_POS (11U)
+#define GLB_COEX_BT_BW_LEN (1U)
+#define GLB_COEX_BT_BW_MSK \
+ (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)
+#define GLB_COEX_BT_BW_UMSK \
+ (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS))
+#define GLB_EN_GPIO_BT_COEX GLB_EN_GPIO_BT_COEX
+#define GLB_EN_GPIO_BT_COEX_POS (12U)
+#define GLB_EN_GPIO_BT_COEX_LEN (1U)
+#define GLB_EN_GPIO_BT_COEX_MSK \
+ (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)
+#define GLB_EN_GPIO_BT_COEX_UMSK \
+ (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS))
+
+/* 0xC0 : UART_SIG_SEL_0 */
+
+#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
+#define GLB_UART_SIG_0_SEL GLB_UART_SIG_0_SEL
+#define GLB_UART_SIG_0_SEL_POS (0U)
+#define GLB_UART_SIG_0_SEL_LEN (4U)
+#define GLB_UART_SIG_0_SEL_MSK \
+ (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
+#define GLB_UART_SIG_0_SEL_UMSK \
+ (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
+#define GLB_UART_SIG_1_SEL GLB_UART_SIG_1_SEL
+#define GLB_UART_SIG_1_SEL_POS (4U)
+#define GLB_UART_SIG_1_SEL_LEN (4U)
+#define GLB_UART_SIG_1_SEL_MSK \
+ (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
+#define GLB_UART_SIG_1_SEL_UMSK \
+ (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
+#define GLB_UART_SIG_2_SEL GLB_UART_SIG_2_SEL
+#define GLB_UART_SIG_2_SEL_POS (8U)
+#define GLB_UART_SIG_2_SEL_LEN (4U)
+#define GLB_UART_SIG_2_SEL_MSK \
+ (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
+#define GLB_UART_SIG_2_SEL_UMSK \
+ (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
+#define GLB_UART_SIG_3_SEL GLB_UART_SIG_3_SEL
+#define GLB_UART_SIG_3_SEL_POS (12U)
+#define GLB_UART_SIG_3_SEL_LEN (4U)
+#define GLB_UART_SIG_3_SEL_MSK \
+ (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
+#define GLB_UART_SIG_3_SEL_UMSK \
+ (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
+#define GLB_UART_SIG_4_SEL GLB_UART_SIG_4_SEL
+#define GLB_UART_SIG_4_SEL_POS (16U)
+#define GLB_UART_SIG_4_SEL_LEN (4U)
+#define GLB_UART_SIG_4_SEL_MSK \
+ (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
+#define GLB_UART_SIG_4_SEL_UMSK \
+ (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
+#define GLB_UART_SIG_5_SEL GLB_UART_SIG_5_SEL
+#define GLB_UART_SIG_5_SEL_POS (20U)
+#define GLB_UART_SIG_5_SEL_LEN (4U)
+#define GLB_UART_SIG_5_SEL_MSK \
+ (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
+#define GLB_UART_SIG_5_SEL_UMSK \
+ (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
+#define GLB_UART_SIG_6_SEL GLB_UART_SIG_6_SEL
+#define GLB_UART_SIG_6_SEL_POS (24U)
+#define GLB_UART_SIG_6_SEL_LEN (4U)
+#define GLB_UART_SIG_6_SEL_MSK \
+ (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
+#define GLB_UART_SIG_6_SEL_UMSK \
+ (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
+#define GLB_UART_SIG_7_SEL GLB_UART_SIG_7_SEL
+#define GLB_UART_SIG_7_SEL_POS (28U)
+#define GLB_UART_SIG_7_SEL_LEN (4U)
+#define GLB_UART_SIG_7_SEL_MSK \
+ (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
+#define GLB_UART_SIG_7_SEL_UMSK \
+ (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))
+
+/* 0xD0 : DBG_SEL_LL */
+
+#define GLB_DBG_SEL_LL_OFFSET (0xD0)
+#define GLB_REG_DBG_LL_CTRL GLB_REG_DBG_LL_CTRL
+#define GLB_REG_DBG_LL_CTRL_POS (0U)
+#define GLB_REG_DBG_LL_CTRL_LEN (32U)
+#define GLB_REG_DBG_LL_CTRL_MSK \
+ (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
+#define GLB_REG_DBG_LL_CTRL_UMSK \
+ (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))
+
+/* 0xD4 : DBG_SEL_LH */
+
+#define GLB_DBG_SEL_LH_OFFSET (0xD4)
+#define GLB_REG_DBG_LH_CTRL GLB_REG_DBG_LH_CTRL
+#define GLB_REG_DBG_LH_CTRL_POS (0U)
+#define GLB_REG_DBG_LH_CTRL_LEN (32U)
+#define GLB_REG_DBG_LH_CTRL_MSK \
+ (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
+#define GLB_REG_DBG_LH_CTRL_UMSK \
+ (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))
+
+/* 0xD8 : DBG_SEL_HL */
+
+#define GLB_DBG_SEL_HL_OFFSET (0xD8)
+#define GLB_REG_DBG_HL_CTRL GLB_REG_DBG_HL_CTRL
+#define GLB_REG_DBG_HL_CTRL_POS (0U)
+#define GLB_REG_DBG_HL_CTRL_LEN (32U)
+#define GLB_REG_DBG_HL_CTRL_MSK \
+ (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
+#define GLB_REG_DBG_HL_CTRL_UMSK \
+ (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))
+
+/* 0xDC : DBG_SEL_HH */
+
+#define GLB_DBG_SEL_HH_OFFSET (0xDC)
+#define GLB_REG_DBG_HH_CTRL GLB_REG_DBG_HH_CTRL
+#define GLB_REG_DBG_HH_CTRL_POS (0U)
+#define GLB_REG_DBG_HH_CTRL_LEN (32U)
+#define GLB_REG_DBG_HH_CTRL_MSK \
+ (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
+#define GLB_REG_DBG_HH_CTRL_UMSK \
+ (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))
+
+/* 0xE0 : debug */
+
+#define GLB_DEBUG_OFFSET (0xE0)
+#define GLB_DEBUG_OE GLB_DEBUG_OE
+#define GLB_DEBUG_OE_POS (0U)
+#define GLB_DEBUG_OE_LEN (1U)
+#define GLB_DEBUG_OE_MSK (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
+#define GLB_DEBUG_OE_UMSK \
+ (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
+#define GLB_DEBUG_I GLB_DEBUG_I
+#define GLB_DEBUG_I_POS (1U)
+#define GLB_DEBUG_I_LEN (31U)
+#define GLB_DEBUG_I_MSK (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
+#define GLB_DEBUG_I_UMSK (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))
+
+/* 0x100 : GPIO_CFGCTL0 */
+
+#define GLB_GPIO_CFGCTL0_OFFSET (0x100)
+#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS (0U)
+#define GLB_REG_GPIO_0_IE_LEN (1U)
+#define GLB_REG_GPIO_0_IE_MSK \
+ (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS (1U)
+#define GLB_REG_GPIO_0_SMT_LEN (1U)
+#define GLB_REG_GPIO_0_SMT_MSK \
+ (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS (2U)
+#define GLB_REG_GPIO_0_DRV_LEN (2U)
+#define GLB_REG_GPIO_0_DRV_MSK \
+ (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS (4U)
+#define GLB_REG_GPIO_0_PU_LEN (1U)
+#define GLB_REG_GPIO_0_PU_MSK \
+ (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS (5U)
+#define GLB_REG_GPIO_0_PD_LEN (1U)
+#define GLB_REG_GPIO_0_PD_MSK \
+ (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL
+#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_MSK \
+ (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \
+ << GLB_REAL_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS (16U)
+#define GLB_REG_GPIO_1_IE_LEN (1U)
+#define GLB_REG_GPIO_1_IE_MSK \
+ (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS (17U)
+#define GLB_REG_GPIO_1_SMT_LEN (1U)
+#define GLB_REG_GPIO_1_SMT_MSK \
+ (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS (18U)
+#define GLB_REG_GPIO_1_DRV_LEN (2U)
+#define GLB_REG_GPIO_1_DRV_MSK \
+ (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS (20U)
+#define GLB_REG_GPIO_1_PU_LEN (1U)
+#define GLB_REG_GPIO_1_PU_MSK \
+ (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS (21U)
+#define GLB_REG_GPIO_1_PD_LEN (1U)
+#define GLB_REG_GPIO_1_PD_MSK \
+ (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_1_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL
+#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_MSK \
+ (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \
+ << GLB_REAL_GPIO_1_FUNC_SEL_POS))
+
+/* 0x104 : GPIO_CFGCTL1 */
+
+#define GLB_GPIO_CFGCTL1_OFFSET (0x104)
+#define GLB_REG_GPIO_2_IE GLB_REG_GPIO_2_IE
+#define GLB_REG_GPIO_2_IE_POS (0U)
+#define GLB_REG_GPIO_2_IE_LEN (1U)
+#define GLB_REG_GPIO_2_IE_MSK \
+ (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
+#define GLB_REG_GPIO_2_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
+#define GLB_REG_GPIO_2_SMT GLB_REG_GPIO_2_SMT
+#define GLB_REG_GPIO_2_SMT_POS (1U)
+#define GLB_REG_GPIO_2_SMT_LEN (1U)
+#define GLB_REG_GPIO_2_SMT_MSK \
+ (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
+#define GLB_REG_GPIO_2_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
+#define GLB_REG_GPIO_2_DRV GLB_REG_GPIO_2_DRV
+#define GLB_REG_GPIO_2_DRV_POS (2U)
+#define GLB_REG_GPIO_2_DRV_LEN (2U)
+#define GLB_REG_GPIO_2_DRV_MSK \
+ (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
+#define GLB_REG_GPIO_2_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
+#define GLB_REG_GPIO_2_PU GLB_REG_GPIO_2_PU
+#define GLB_REG_GPIO_2_PU_POS (4U)
+#define GLB_REG_GPIO_2_PU_LEN (1U)
+#define GLB_REG_GPIO_2_PU_MSK \
+ (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
+#define GLB_REG_GPIO_2_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
+#define GLB_REG_GPIO_2_PD GLB_REG_GPIO_2_PD
+#define GLB_REG_GPIO_2_PD_POS (5U)
+#define GLB_REG_GPIO_2_PD_LEN (1U)
+#define GLB_REG_GPIO_2_PD_MSK \
+ (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
+#define GLB_REG_GPIO_2_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
+#define GLB_REG_GPIO_2_FUNC_SEL GLB_REG_GPIO_2_FUNC_SEL
+#define GLB_REG_GPIO_2_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_2_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_2_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
+#define GLB_REG_GPIO_2_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_2_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_2_FUNC_SEL GLB_REAL_GPIO_2_FUNC_SEL
+#define GLB_REAL_GPIO_2_FUNC_SEL_POS (12U)
+#define GLB_REAL_GPIO_2_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_2_FUNC_SEL_MSK \
+ (((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_2_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) \
+ << GLB_REAL_GPIO_2_FUNC_SEL_POS))
+#define GLB_REG_GPIO_3_IE GLB_REG_GPIO_3_IE
+#define GLB_REG_GPIO_3_IE_POS (16U)
+#define GLB_REG_GPIO_3_IE_LEN (1U)
+#define GLB_REG_GPIO_3_IE_MSK \
+ (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
+#define GLB_REG_GPIO_3_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
+#define GLB_REG_GPIO_3_SMT GLB_REG_GPIO_3_SMT
+#define GLB_REG_GPIO_3_SMT_POS (17U)
+#define GLB_REG_GPIO_3_SMT_LEN (1U)
+#define GLB_REG_GPIO_3_SMT_MSK \
+ (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
+#define GLB_REG_GPIO_3_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
+#define GLB_REG_GPIO_3_DRV GLB_REG_GPIO_3_DRV
+#define GLB_REG_GPIO_3_DRV_POS (18U)
+#define GLB_REG_GPIO_3_DRV_LEN (2U)
+#define GLB_REG_GPIO_3_DRV_MSK \
+ (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
+#define GLB_REG_GPIO_3_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
+#define GLB_REG_GPIO_3_PU GLB_REG_GPIO_3_PU
+#define GLB_REG_GPIO_3_PU_POS (20U)
+#define GLB_REG_GPIO_3_PU_LEN (1U)
+#define GLB_REG_GPIO_3_PU_MSK \
+ (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
+#define GLB_REG_GPIO_3_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
+#define GLB_REG_GPIO_3_PD GLB_REG_GPIO_3_PD
+#define GLB_REG_GPIO_3_PD_POS (21U)
+#define GLB_REG_GPIO_3_PD_LEN (1U)
+#define GLB_REG_GPIO_3_PD_MSK \
+ (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
+#define GLB_REG_GPIO_3_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
+#define GLB_REG_GPIO_3_FUNC_SEL GLB_REG_GPIO_3_FUNC_SEL
+#define GLB_REG_GPIO_3_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_3_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_3_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
+#define GLB_REG_GPIO_3_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_3_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_3_FUNC_SEL GLB_REAL_GPIO_3_FUNC_SEL
+#define GLB_REAL_GPIO_3_FUNC_SEL_POS (28U)
+#define GLB_REAL_GPIO_3_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_3_FUNC_SEL_MSK \
+ (((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_3_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) \
+ << GLB_REAL_GPIO_3_FUNC_SEL_POS))
+
+/* 0x108 : GPIO_CFGCTL2 */
+
+#define GLB_GPIO_CFGCTL2_OFFSET (0x108)
+#define GLB_REG_GPIO_4_IE GLB_REG_GPIO_4_IE
+#define GLB_REG_GPIO_4_IE_POS (0U)
+#define GLB_REG_GPIO_4_IE_LEN (1U)
+#define GLB_REG_GPIO_4_IE_MSK \
+ (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
+#define GLB_REG_GPIO_4_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
+#define GLB_REG_GPIO_4_SMT GLB_REG_GPIO_4_SMT
+#define GLB_REG_GPIO_4_SMT_POS (1U)
+#define GLB_REG_GPIO_4_SMT_LEN (1U)
+#define GLB_REG_GPIO_4_SMT_MSK \
+ (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
+#define GLB_REG_GPIO_4_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
+#define GLB_REG_GPIO_4_DRV GLB_REG_GPIO_4_DRV
+#define GLB_REG_GPIO_4_DRV_POS (2U)
+#define GLB_REG_GPIO_4_DRV_LEN (2U)
+#define GLB_REG_GPIO_4_DRV_MSK \
+ (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
+#define GLB_REG_GPIO_4_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
+#define GLB_REG_GPIO_4_PU GLB_REG_GPIO_4_PU
+#define GLB_REG_GPIO_4_PU_POS (4U)
+#define GLB_REG_GPIO_4_PU_LEN (1U)
+#define GLB_REG_GPIO_4_PU_MSK \
+ (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
+#define GLB_REG_GPIO_4_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
+#define GLB_REG_GPIO_4_PD GLB_REG_GPIO_4_PD
+#define GLB_REG_GPIO_4_PD_POS (5U)
+#define GLB_REG_GPIO_4_PD_LEN (1U)
+#define GLB_REG_GPIO_4_PD_MSK \
+ (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
+#define GLB_REG_GPIO_4_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
+#define GLB_REG_GPIO_4_FUNC_SEL GLB_REG_GPIO_4_FUNC_SEL
+#define GLB_REG_GPIO_4_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_4_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_4_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
+#define GLB_REG_GPIO_4_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_4_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_4_FUNC_SEL GLB_REAL_GPIO_4_FUNC_SEL
+#define GLB_REAL_GPIO_4_FUNC_SEL_POS (12U)
+#define GLB_REAL_GPIO_4_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_4_FUNC_SEL_MSK \
+ (((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_4_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) \
+ << GLB_REAL_GPIO_4_FUNC_SEL_POS))
+#define GLB_REG_GPIO_5_IE GLB_REG_GPIO_5_IE
+#define GLB_REG_GPIO_5_IE_POS (16U)
+#define GLB_REG_GPIO_5_IE_LEN (1U)
+#define GLB_REG_GPIO_5_IE_MSK \
+ (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
+#define GLB_REG_GPIO_5_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
+#define GLB_REG_GPIO_5_SMT GLB_REG_GPIO_5_SMT
+#define GLB_REG_GPIO_5_SMT_POS (17U)
+#define GLB_REG_GPIO_5_SMT_LEN (1U)
+#define GLB_REG_GPIO_5_SMT_MSK \
+ (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
+#define GLB_REG_GPIO_5_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
+#define GLB_REG_GPIO_5_DRV GLB_REG_GPIO_5_DRV
+#define GLB_REG_GPIO_5_DRV_POS (18U)
+#define GLB_REG_GPIO_5_DRV_LEN (2U)
+#define GLB_REG_GPIO_5_DRV_MSK \
+ (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
+#define GLB_REG_GPIO_5_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
+#define GLB_REG_GPIO_5_PU GLB_REG_GPIO_5_PU
+#define GLB_REG_GPIO_5_PU_POS (20U)
+#define GLB_REG_GPIO_5_PU_LEN (1U)
+#define GLB_REG_GPIO_5_PU_MSK \
+ (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
+#define GLB_REG_GPIO_5_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
+#define GLB_REG_GPIO_5_PD GLB_REG_GPIO_5_PD
+#define GLB_REG_GPIO_5_PD_POS (21U)
+#define GLB_REG_GPIO_5_PD_LEN (1U)
+#define GLB_REG_GPIO_5_PD_MSK \
+ (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
+#define GLB_REG_GPIO_5_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
+#define GLB_REG_GPIO_5_FUNC_SEL GLB_REG_GPIO_5_FUNC_SEL
+#define GLB_REG_GPIO_5_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_5_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_5_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
+#define GLB_REG_GPIO_5_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_5_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_5_FUNC_SEL GLB_REAL_GPIO_5_FUNC_SEL
+#define GLB_REAL_GPIO_5_FUNC_SEL_POS (28U)
+#define GLB_REAL_GPIO_5_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_5_FUNC_SEL_MSK \
+ (((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_5_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) \
+ << GLB_REAL_GPIO_5_FUNC_SEL_POS))
+
+/* 0x10C : GPIO_CFGCTL3 */
+
+#define GLB_GPIO_CFGCTL3_OFFSET (0x10C)
+#define GLB_REG_GPIO_6_IE GLB_REG_GPIO_6_IE
+#define GLB_REG_GPIO_6_IE_POS (0U)
+#define GLB_REG_GPIO_6_IE_LEN (1U)
+#define GLB_REG_GPIO_6_IE_MSK \
+ (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
+#define GLB_REG_GPIO_6_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
+#define GLB_REG_GPIO_6_SMT GLB_REG_GPIO_6_SMT
+#define GLB_REG_GPIO_6_SMT_POS (1U)
+#define GLB_REG_GPIO_6_SMT_LEN (1U)
+#define GLB_REG_GPIO_6_SMT_MSK \
+ (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
+#define GLB_REG_GPIO_6_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
+#define GLB_REG_GPIO_6_DRV GLB_REG_GPIO_6_DRV
+#define GLB_REG_GPIO_6_DRV_POS (2U)
+#define GLB_REG_GPIO_6_DRV_LEN (2U)
+#define GLB_REG_GPIO_6_DRV_MSK \
+ (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
+#define GLB_REG_GPIO_6_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
+#define GLB_REG_GPIO_6_PU GLB_REG_GPIO_6_PU
+#define GLB_REG_GPIO_6_PU_POS (4U)
+#define GLB_REG_GPIO_6_PU_LEN (1U)
+#define GLB_REG_GPIO_6_PU_MSK \
+ (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
+#define GLB_REG_GPIO_6_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
+#define GLB_REG_GPIO_6_PD GLB_REG_GPIO_6_PD
+#define GLB_REG_GPIO_6_PD_POS (5U)
+#define GLB_REG_GPIO_6_PD_LEN (1U)
+#define GLB_REG_GPIO_6_PD_MSK \
+ (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
+#define GLB_REG_GPIO_6_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
+#define GLB_REG_GPIO_6_FUNC_SEL GLB_REG_GPIO_6_FUNC_SEL
+#define GLB_REG_GPIO_6_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_6_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_6_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
+#define GLB_REG_GPIO_6_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_6_FUNC_SEL_POS))
+#define GLB_REG_GPIO_7_IE GLB_REG_GPIO_7_IE
+#define GLB_REG_GPIO_7_IE_POS (16U)
+#define GLB_REG_GPIO_7_IE_LEN (1U)
+#define GLB_REG_GPIO_7_IE_MSK \
+ (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
+#define GLB_REG_GPIO_7_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
+#define GLB_REG_GPIO_7_SMT GLB_REG_GPIO_7_SMT
+#define GLB_REG_GPIO_7_SMT_POS (17U)
+#define GLB_REG_GPIO_7_SMT_LEN (1U)
+#define GLB_REG_GPIO_7_SMT_MSK \
+ (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
+#define GLB_REG_GPIO_7_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
+#define GLB_REG_GPIO_7_DRV GLB_REG_GPIO_7_DRV
+#define GLB_REG_GPIO_7_DRV_POS (18U)
+#define GLB_REG_GPIO_7_DRV_LEN (2U)
+#define GLB_REG_GPIO_7_DRV_MSK \
+ (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
+#define GLB_REG_GPIO_7_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
+#define GLB_REG_GPIO_7_PU GLB_REG_GPIO_7_PU
+#define GLB_REG_GPIO_7_PU_POS (20U)
+#define GLB_REG_GPIO_7_PU_LEN (1U)
+#define GLB_REG_GPIO_7_PU_MSK \
+ (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
+#define GLB_REG_GPIO_7_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
+#define GLB_REG_GPIO_7_PD GLB_REG_GPIO_7_PD
+#define GLB_REG_GPIO_7_PD_POS (21U)
+#define GLB_REG_GPIO_7_PD_LEN (1U)
+#define GLB_REG_GPIO_7_PD_MSK \
+ (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
+#define GLB_REG_GPIO_7_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
+#define GLB_REG_GPIO_7_FUNC_SEL GLB_REG_GPIO_7_FUNC_SEL
+#define GLB_REG_GPIO_7_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_7_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_7_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
+#define GLB_REG_GPIO_7_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_7_FUNC_SEL_POS))
+
+/* 0x110 : GPIO_CFGCTL4 */
+
+#define GLB_GPIO_CFGCTL4_OFFSET (0x110)
+#define GLB_REG_GPIO_8_IE GLB_REG_GPIO_8_IE
+#define GLB_REG_GPIO_8_IE_POS (0U)
+#define GLB_REG_GPIO_8_IE_LEN (1U)
+#define GLB_REG_GPIO_8_IE_MSK \
+ (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
+#define GLB_REG_GPIO_8_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
+#define GLB_REG_GPIO_8_SMT GLB_REG_GPIO_8_SMT
+#define GLB_REG_GPIO_8_SMT_POS (1U)
+#define GLB_REG_GPIO_8_SMT_LEN (1U)
+#define GLB_REG_GPIO_8_SMT_MSK \
+ (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
+#define GLB_REG_GPIO_8_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
+#define GLB_REG_GPIO_8_DRV GLB_REG_GPIO_8_DRV
+#define GLB_REG_GPIO_8_DRV_POS (2U)
+#define GLB_REG_GPIO_8_DRV_LEN (2U)
+#define GLB_REG_GPIO_8_DRV_MSK \
+ (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
+#define GLB_REG_GPIO_8_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
+#define GLB_REG_GPIO_8_PU GLB_REG_GPIO_8_PU
+#define GLB_REG_GPIO_8_PU_POS (4U)
+#define GLB_REG_GPIO_8_PU_LEN (1U)
+#define GLB_REG_GPIO_8_PU_MSK \
+ (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
+#define GLB_REG_GPIO_8_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
+#define GLB_REG_GPIO_8_PD GLB_REG_GPIO_8_PD
+#define GLB_REG_GPIO_8_PD_POS (5U)
+#define GLB_REG_GPIO_8_PD_LEN (1U)
+#define GLB_REG_GPIO_8_PD_MSK \
+ (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
+#define GLB_REG_GPIO_8_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
+#define GLB_REG_GPIO_8_FUNC_SEL GLB_REG_GPIO_8_FUNC_SEL
+#define GLB_REG_GPIO_8_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_8_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_8_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
+#define GLB_REG_GPIO_8_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_8_FUNC_SEL_POS))
+#define GLB_REG_GPIO_9_IE GLB_REG_GPIO_9_IE
+#define GLB_REG_GPIO_9_IE_POS (16U)
+#define GLB_REG_GPIO_9_IE_LEN (1U)
+#define GLB_REG_GPIO_9_IE_MSK \
+ (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
+#define GLB_REG_GPIO_9_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
+#define GLB_REG_GPIO_9_SMT GLB_REG_GPIO_9_SMT
+#define GLB_REG_GPIO_9_SMT_POS (17U)
+#define GLB_REG_GPIO_9_SMT_LEN (1U)
+#define GLB_REG_GPIO_9_SMT_MSK \
+ (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
+#define GLB_REG_GPIO_9_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
+#define GLB_REG_GPIO_9_DRV GLB_REG_GPIO_9_DRV
+#define GLB_REG_GPIO_9_DRV_POS (18U)
+#define GLB_REG_GPIO_9_DRV_LEN (2U)
+#define GLB_REG_GPIO_9_DRV_MSK \
+ (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
+#define GLB_REG_GPIO_9_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
+#define GLB_REG_GPIO_9_PU GLB_REG_GPIO_9_PU
+#define GLB_REG_GPIO_9_PU_POS (20U)
+#define GLB_REG_GPIO_9_PU_LEN (1U)
+#define GLB_REG_GPIO_9_PU_MSK \
+ (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
+#define GLB_REG_GPIO_9_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
+#define GLB_REG_GPIO_9_PD GLB_REG_GPIO_9_PD
+#define GLB_REG_GPIO_9_PD_POS (21U)
+#define GLB_REG_GPIO_9_PD_LEN (1U)
+#define GLB_REG_GPIO_9_PD_MSK \
+ (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
+#define GLB_REG_GPIO_9_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
+#define GLB_REG_GPIO_9_FUNC_SEL GLB_REG_GPIO_9_FUNC_SEL
+#define GLB_REG_GPIO_9_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_9_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_9_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
+#define GLB_REG_GPIO_9_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_9_FUNC_SEL_POS))
+
+/* 0x114 : GPIO_CFGCTL5 */
+
+#define GLB_GPIO_CFGCTL5_OFFSET (0x114)
+#define GLB_REG_GPIO_10_IE GLB_REG_GPIO_10_IE
+#define GLB_REG_GPIO_10_IE_POS (0U)
+#define GLB_REG_GPIO_10_IE_LEN (1U)
+#define GLB_REG_GPIO_10_IE_MSK \
+ (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
+#define GLB_REG_GPIO_10_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
+#define GLB_REG_GPIO_10_SMT GLB_REG_GPIO_10_SMT
+#define GLB_REG_GPIO_10_SMT_POS (1U)
+#define GLB_REG_GPIO_10_SMT_LEN (1U)
+#define GLB_REG_GPIO_10_SMT_MSK \
+ (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
+#define GLB_REG_GPIO_10_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
+#define GLB_REG_GPIO_10_DRV GLB_REG_GPIO_10_DRV
+#define GLB_REG_GPIO_10_DRV_POS (2U)
+#define GLB_REG_GPIO_10_DRV_LEN (2U)
+#define GLB_REG_GPIO_10_DRV_MSK \
+ (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
+#define GLB_REG_GPIO_10_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
+#define GLB_REG_GPIO_10_PU GLB_REG_GPIO_10_PU
+#define GLB_REG_GPIO_10_PU_POS (4U)
+#define GLB_REG_GPIO_10_PU_LEN (1U)
+#define GLB_REG_GPIO_10_PU_MSK \
+ (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
+#define GLB_REG_GPIO_10_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
+#define GLB_REG_GPIO_10_PD GLB_REG_GPIO_10_PD
+#define GLB_REG_GPIO_10_PD_POS (5U)
+#define GLB_REG_GPIO_10_PD_LEN (1U)
+#define GLB_REG_GPIO_10_PD_MSK \
+ (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
+#define GLB_REG_GPIO_10_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
+#define GLB_REG_GPIO_10_FUNC_SEL GLB_REG_GPIO_10_FUNC_SEL
+#define GLB_REG_GPIO_10_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_10_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_10_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
+#define GLB_REG_GPIO_10_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_10_FUNC_SEL_POS))
+#define GLB_REG_GPIO_11_IE GLB_REG_GPIO_11_IE
+#define GLB_REG_GPIO_11_IE_POS (16U)
+#define GLB_REG_GPIO_11_IE_LEN (1U)
+#define GLB_REG_GPIO_11_IE_MSK \
+ (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
+#define GLB_REG_GPIO_11_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
+#define GLB_REG_GPIO_11_SMT GLB_REG_GPIO_11_SMT
+#define GLB_REG_GPIO_11_SMT_POS (17U)
+#define GLB_REG_GPIO_11_SMT_LEN (1U)
+#define GLB_REG_GPIO_11_SMT_MSK \
+ (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
+#define GLB_REG_GPIO_11_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
+#define GLB_REG_GPIO_11_DRV GLB_REG_GPIO_11_DRV
+#define GLB_REG_GPIO_11_DRV_POS (18U)
+#define GLB_REG_GPIO_11_DRV_LEN (2U)
+#define GLB_REG_GPIO_11_DRV_MSK \
+ (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
+#define GLB_REG_GPIO_11_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
+#define GLB_REG_GPIO_11_PU GLB_REG_GPIO_11_PU
+#define GLB_REG_GPIO_11_PU_POS (20U)
+#define GLB_REG_GPIO_11_PU_LEN (1U)
+#define GLB_REG_GPIO_11_PU_MSK \
+ (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
+#define GLB_REG_GPIO_11_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
+#define GLB_REG_GPIO_11_PD GLB_REG_GPIO_11_PD
+#define GLB_REG_GPIO_11_PD_POS (21U)
+#define GLB_REG_GPIO_11_PD_LEN (1U)
+#define GLB_REG_GPIO_11_PD_MSK \
+ (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
+#define GLB_REG_GPIO_11_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
+#define GLB_REG_GPIO_11_FUNC_SEL GLB_REG_GPIO_11_FUNC_SEL
+#define GLB_REG_GPIO_11_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_11_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_11_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
+#define GLB_REG_GPIO_11_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_11_FUNC_SEL_POS))
+
+/* 0x118 : GPIO_CFGCTL6 */
+
+#define GLB_GPIO_CFGCTL6_OFFSET (0x118)
+#define GLB_REG_GPIO_12_IE GLB_REG_GPIO_12_IE
+#define GLB_REG_GPIO_12_IE_POS (0U)
+#define GLB_REG_GPIO_12_IE_LEN (1U)
+#define GLB_REG_GPIO_12_IE_MSK \
+ (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
+#define GLB_REG_GPIO_12_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
+#define GLB_REG_GPIO_12_SMT GLB_REG_GPIO_12_SMT
+#define GLB_REG_GPIO_12_SMT_POS (1U)
+#define GLB_REG_GPIO_12_SMT_LEN (1U)
+#define GLB_REG_GPIO_12_SMT_MSK \
+ (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
+#define GLB_REG_GPIO_12_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
+#define GLB_REG_GPIO_12_DRV GLB_REG_GPIO_12_DRV
+#define GLB_REG_GPIO_12_DRV_POS (2U)
+#define GLB_REG_GPIO_12_DRV_LEN (2U)
+#define GLB_REG_GPIO_12_DRV_MSK \
+ (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
+#define GLB_REG_GPIO_12_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
+#define GLB_REG_GPIO_12_PU GLB_REG_GPIO_12_PU
+#define GLB_REG_GPIO_12_PU_POS (4U)
+#define GLB_REG_GPIO_12_PU_LEN (1U)
+#define GLB_REG_GPIO_12_PU_MSK \
+ (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
+#define GLB_REG_GPIO_12_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
+#define GLB_REG_GPIO_12_PD GLB_REG_GPIO_12_PD
+#define GLB_REG_GPIO_12_PD_POS (5U)
+#define GLB_REG_GPIO_12_PD_LEN (1U)
+#define GLB_REG_GPIO_12_PD_MSK \
+ (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
+#define GLB_REG_GPIO_12_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
+#define GLB_REG_GPIO_12_FUNC_SEL GLB_REG_GPIO_12_FUNC_SEL
+#define GLB_REG_GPIO_12_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_12_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_12_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
+#define GLB_REG_GPIO_12_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_12_FUNC_SEL_POS))
+#define GLB_REG_GPIO_13_IE GLB_REG_GPIO_13_IE
+#define GLB_REG_GPIO_13_IE_POS (16U)
+#define GLB_REG_GPIO_13_IE_LEN (1U)
+#define GLB_REG_GPIO_13_IE_MSK \
+ (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
+#define GLB_REG_GPIO_13_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
+#define GLB_REG_GPIO_13_SMT GLB_REG_GPIO_13_SMT
+#define GLB_REG_GPIO_13_SMT_POS (17U)
+#define GLB_REG_GPIO_13_SMT_LEN (1U)
+#define GLB_REG_GPIO_13_SMT_MSK \
+ (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
+#define GLB_REG_GPIO_13_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
+#define GLB_REG_GPIO_13_DRV GLB_REG_GPIO_13_DRV
+#define GLB_REG_GPIO_13_DRV_POS (18U)
+#define GLB_REG_GPIO_13_DRV_LEN (2U)
+#define GLB_REG_GPIO_13_DRV_MSK \
+ (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
+#define GLB_REG_GPIO_13_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
+#define GLB_REG_GPIO_13_PU GLB_REG_GPIO_13_PU
+#define GLB_REG_GPIO_13_PU_POS (20U)
+#define GLB_REG_GPIO_13_PU_LEN (1U)
+#define GLB_REG_GPIO_13_PU_MSK \
+ (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
+#define GLB_REG_GPIO_13_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
+#define GLB_REG_GPIO_13_PD GLB_REG_GPIO_13_PD
+#define GLB_REG_GPIO_13_PD_POS (21U)
+#define GLB_REG_GPIO_13_PD_LEN (1U)
+#define GLB_REG_GPIO_13_PD_MSK \
+ (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
+#define GLB_REG_GPIO_13_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
+#define GLB_REG_GPIO_13_FUNC_SEL GLB_REG_GPIO_13_FUNC_SEL
+#define GLB_REG_GPIO_13_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_13_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_13_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
+#define GLB_REG_GPIO_13_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_13_FUNC_SEL_POS))
+
+/* 0x11C : GPIO_CFGCTL7 */
+
+#define GLB_GPIO_CFGCTL7_OFFSET (0x11C)
+#define GLB_REG_GPIO_14_IE GLB_REG_GPIO_14_IE
+#define GLB_REG_GPIO_14_IE_POS (0U)
+#define GLB_REG_GPIO_14_IE_LEN (1U)
+#define GLB_REG_GPIO_14_IE_MSK \
+ (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
+#define GLB_REG_GPIO_14_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
+#define GLB_REG_GPIO_14_SMT GLB_REG_GPIO_14_SMT
+#define GLB_REG_GPIO_14_SMT_POS (1U)
+#define GLB_REG_GPIO_14_SMT_LEN (1U)
+#define GLB_REG_GPIO_14_SMT_MSK \
+ (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
+#define GLB_REG_GPIO_14_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
+#define GLB_REG_GPIO_14_DRV GLB_REG_GPIO_14_DRV
+#define GLB_REG_GPIO_14_DRV_POS (2U)
+#define GLB_REG_GPIO_14_DRV_LEN (2U)
+#define GLB_REG_GPIO_14_DRV_MSK \
+ (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
+#define GLB_REG_GPIO_14_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
+#define GLB_REG_GPIO_14_PU GLB_REG_GPIO_14_PU
+#define GLB_REG_GPIO_14_PU_POS (4U)
+#define GLB_REG_GPIO_14_PU_LEN (1U)
+#define GLB_REG_GPIO_14_PU_MSK \
+ (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
+#define GLB_REG_GPIO_14_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
+#define GLB_REG_GPIO_14_PD GLB_REG_GPIO_14_PD
+#define GLB_REG_GPIO_14_PD_POS (5U)
+#define GLB_REG_GPIO_14_PD_LEN (1U)
+#define GLB_REG_GPIO_14_PD_MSK \
+ (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
+#define GLB_REG_GPIO_14_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
+#define GLB_REG_GPIO_14_FUNC_SEL GLB_REG_GPIO_14_FUNC_SEL
+#define GLB_REG_GPIO_14_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_14_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_14_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
+#define GLB_REG_GPIO_14_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_14_FUNC_SEL_POS))
+#define GLB_REG_GPIO_15_IE GLB_REG_GPIO_15_IE
+#define GLB_REG_GPIO_15_IE_POS (16U)
+#define GLB_REG_GPIO_15_IE_LEN (1U)
+#define GLB_REG_GPIO_15_IE_MSK \
+ (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
+#define GLB_REG_GPIO_15_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
+#define GLB_REG_GPIO_15_SMT GLB_REG_GPIO_15_SMT
+#define GLB_REG_GPIO_15_SMT_POS (17U)
+#define GLB_REG_GPIO_15_SMT_LEN (1U)
+#define GLB_REG_GPIO_15_SMT_MSK \
+ (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
+#define GLB_REG_GPIO_15_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
+#define GLB_REG_GPIO_15_DRV GLB_REG_GPIO_15_DRV
+#define GLB_REG_GPIO_15_DRV_POS (18U)
+#define GLB_REG_GPIO_15_DRV_LEN (2U)
+#define GLB_REG_GPIO_15_DRV_MSK \
+ (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
+#define GLB_REG_GPIO_15_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
+#define GLB_REG_GPIO_15_PU GLB_REG_GPIO_15_PU
+#define GLB_REG_GPIO_15_PU_POS (20U)
+#define GLB_REG_GPIO_15_PU_LEN (1U)
+#define GLB_REG_GPIO_15_PU_MSK \
+ (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
+#define GLB_REG_GPIO_15_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
+#define GLB_REG_GPIO_15_PD GLB_REG_GPIO_15_PD
+#define GLB_REG_GPIO_15_PD_POS (21U)
+#define GLB_REG_GPIO_15_PD_LEN (1U)
+#define GLB_REG_GPIO_15_PD_MSK \
+ (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
+#define GLB_REG_GPIO_15_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
+#define GLB_REG_GPIO_15_FUNC_SEL GLB_REG_GPIO_15_FUNC_SEL
+#define GLB_REG_GPIO_15_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_15_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_15_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
+#define GLB_REG_GPIO_15_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_15_FUNC_SEL_POS))
+
+/* 0x120 : GPIO_CFGCTL8 */
+
+#define GLB_GPIO_CFGCTL8_OFFSET (0x120)
+#define GLB_REG_GPIO_16_IE GLB_REG_GPIO_16_IE
+#define GLB_REG_GPIO_16_IE_POS (0U)
+#define GLB_REG_GPIO_16_IE_LEN (1U)
+#define GLB_REG_GPIO_16_IE_MSK \
+ (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
+#define GLB_REG_GPIO_16_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
+#define GLB_REG_GPIO_16_SMT GLB_REG_GPIO_16_SMT
+#define GLB_REG_GPIO_16_SMT_POS (1U)
+#define GLB_REG_GPIO_16_SMT_LEN (1U)
+#define GLB_REG_GPIO_16_SMT_MSK \
+ (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
+#define GLB_REG_GPIO_16_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
+#define GLB_REG_GPIO_16_DRV GLB_REG_GPIO_16_DRV
+#define GLB_REG_GPIO_16_DRV_POS (2U)
+#define GLB_REG_GPIO_16_DRV_LEN (2U)
+#define GLB_REG_GPIO_16_DRV_MSK \
+ (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
+#define GLB_REG_GPIO_16_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
+#define GLB_REG_GPIO_16_PU GLB_REG_GPIO_16_PU
+#define GLB_REG_GPIO_16_PU_POS (4U)
+#define GLB_REG_GPIO_16_PU_LEN (1U)
+#define GLB_REG_GPIO_16_PU_MSK \
+ (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
+#define GLB_REG_GPIO_16_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
+#define GLB_REG_GPIO_16_PD GLB_REG_GPIO_16_PD
+#define GLB_REG_GPIO_16_PD_POS (5U)
+#define GLB_REG_GPIO_16_PD_LEN (1U)
+#define GLB_REG_GPIO_16_PD_MSK \
+ (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
+#define GLB_REG_GPIO_16_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
+#define GLB_REG_GPIO_16_FUNC_SEL GLB_REG_GPIO_16_FUNC_SEL
+#define GLB_REG_GPIO_16_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_16_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_16_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
+#define GLB_REG_GPIO_16_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_16_FUNC_SEL_POS))
+#define GLB_REG_GPIO_17_IE GLB_REG_GPIO_17_IE
+#define GLB_REG_GPIO_17_IE_POS (16U)
+#define GLB_REG_GPIO_17_IE_LEN (1U)
+#define GLB_REG_GPIO_17_IE_MSK \
+ (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
+#define GLB_REG_GPIO_17_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
+#define GLB_REG_GPIO_17_SMT GLB_REG_GPIO_17_SMT
+#define GLB_REG_GPIO_17_SMT_POS (17U)
+#define GLB_REG_GPIO_17_SMT_LEN (1U)
+#define GLB_REG_GPIO_17_SMT_MSK \
+ (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
+#define GLB_REG_GPIO_17_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
+#define GLB_REG_GPIO_17_DRV GLB_REG_GPIO_17_DRV
+#define GLB_REG_GPIO_17_DRV_POS (18U)
+#define GLB_REG_GPIO_17_DRV_LEN (2U)
+#define GLB_REG_GPIO_17_DRV_MSK \
+ (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
+#define GLB_REG_GPIO_17_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
+#define GLB_REG_GPIO_17_PU GLB_REG_GPIO_17_PU
+#define GLB_REG_GPIO_17_PU_POS (20U)
+#define GLB_REG_GPIO_17_PU_LEN (1U)
+#define GLB_REG_GPIO_17_PU_MSK \
+ (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
+#define GLB_REG_GPIO_17_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
+#define GLB_REG_GPIO_17_PD GLB_REG_GPIO_17_PD
+#define GLB_REG_GPIO_17_PD_POS (21U)
+#define GLB_REG_GPIO_17_PD_LEN (1U)
+#define GLB_REG_GPIO_17_PD_MSK \
+ (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
+#define GLB_REG_GPIO_17_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
+#define GLB_REG_GPIO_17_FUNC_SEL GLB_REG_GPIO_17_FUNC_SEL
+#define GLB_REG_GPIO_17_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_17_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_17_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
+#define GLB_REG_GPIO_17_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_17_FUNC_SEL_POS))
+
+/* 0x124 : GPIO_CFGCTL9 */
+
+#define GLB_GPIO_CFGCTL9_OFFSET (0x124)
+#define GLB_REG_GPIO_18_IE GLB_REG_GPIO_18_IE
+#define GLB_REG_GPIO_18_IE_POS (0U)
+#define GLB_REG_GPIO_18_IE_LEN (1U)
+#define GLB_REG_GPIO_18_IE_MSK \
+ (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
+#define GLB_REG_GPIO_18_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
+#define GLB_REG_GPIO_18_SMT GLB_REG_GPIO_18_SMT
+#define GLB_REG_GPIO_18_SMT_POS (1U)
+#define GLB_REG_GPIO_18_SMT_LEN (1U)
+#define GLB_REG_GPIO_18_SMT_MSK \
+ (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
+#define GLB_REG_GPIO_18_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
+#define GLB_REG_GPIO_18_DRV GLB_REG_GPIO_18_DRV
+#define GLB_REG_GPIO_18_DRV_POS (2U)
+#define GLB_REG_GPIO_18_DRV_LEN (2U)
+#define GLB_REG_GPIO_18_DRV_MSK \
+ (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
+#define GLB_REG_GPIO_18_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
+#define GLB_REG_GPIO_18_PU GLB_REG_GPIO_18_PU
+#define GLB_REG_GPIO_18_PU_POS (4U)
+#define GLB_REG_GPIO_18_PU_LEN (1U)
+#define GLB_REG_GPIO_18_PU_MSK \
+ (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
+#define GLB_REG_GPIO_18_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
+#define GLB_REG_GPIO_18_PD GLB_REG_GPIO_18_PD
+#define GLB_REG_GPIO_18_PD_POS (5U)
+#define GLB_REG_GPIO_18_PD_LEN (1U)
+#define GLB_REG_GPIO_18_PD_MSK \
+ (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
+#define GLB_REG_GPIO_18_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
+#define GLB_REG_GPIO_18_FUNC_SEL GLB_REG_GPIO_18_FUNC_SEL
+#define GLB_REG_GPIO_18_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_18_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_18_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
+#define GLB_REG_GPIO_18_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_18_FUNC_SEL_POS))
+#define GLB_REG_GPIO_19_IE GLB_REG_GPIO_19_IE
+#define GLB_REG_GPIO_19_IE_POS (16U)
+#define GLB_REG_GPIO_19_IE_LEN (1U)
+#define GLB_REG_GPIO_19_IE_MSK \
+ (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
+#define GLB_REG_GPIO_19_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
+#define GLB_REG_GPIO_19_SMT GLB_REG_GPIO_19_SMT
+#define GLB_REG_GPIO_19_SMT_POS (17U)
+#define GLB_REG_GPIO_19_SMT_LEN (1U)
+#define GLB_REG_GPIO_19_SMT_MSK \
+ (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
+#define GLB_REG_GPIO_19_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
+#define GLB_REG_GPIO_19_DRV GLB_REG_GPIO_19_DRV
+#define GLB_REG_GPIO_19_DRV_POS (18U)
+#define GLB_REG_GPIO_19_DRV_LEN (2U)
+#define GLB_REG_GPIO_19_DRV_MSK \
+ (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
+#define GLB_REG_GPIO_19_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
+#define GLB_REG_GPIO_19_PU GLB_REG_GPIO_19_PU
+#define GLB_REG_GPIO_19_PU_POS (20U)
+#define GLB_REG_GPIO_19_PU_LEN (1U)
+#define GLB_REG_GPIO_19_PU_MSK \
+ (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
+#define GLB_REG_GPIO_19_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
+#define GLB_REG_GPIO_19_PD GLB_REG_GPIO_19_PD
+#define GLB_REG_GPIO_19_PD_POS (21U)
+#define GLB_REG_GPIO_19_PD_LEN (1U)
+#define GLB_REG_GPIO_19_PD_MSK \
+ (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
+#define GLB_REG_GPIO_19_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
+#define GLB_REG_GPIO_19_FUNC_SEL GLB_REG_GPIO_19_FUNC_SEL
+#define GLB_REG_GPIO_19_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_19_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_19_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
+#define GLB_REG_GPIO_19_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_19_FUNC_SEL_POS))
+
+/* 0x128 : GPIO_CFGCTL10 */
+
+#define GLB_GPIO_CFGCTL10_OFFSET (0x128)
+#define GLB_REG_GPIO_20_IE GLB_REG_GPIO_20_IE
+#define GLB_REG_GPIO_20_IE_POS (0U)
+#define GLB_REG_GPIO_20_IE_LEN (1U)
+#define GLB_REG_GPIO_20_IE_MSK \
+ (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
+#define GLB_REG_GPIO_20_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
+#define GLB_REG_GPIO_20_SMT GLB_REG_GPIO_20_SMT
+#define GLB_REG_GPIO_20_SMT_POS (1U)
+#define GLB_REG_GPIO_20_SMT_LEN (1U)
+#define GLB_REG_GPIO_20_SMT_MSK \
+ (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
+#define GLB_REG_GPIO_20_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
+#define GLB_REG_GPIO_20_DRV GLB_REG_GPIO_20_DRV
+#define GLB_REG_GPIO_20_DRV_POS (2U)
+#define GLB_REG_GPIO_20_DRV_LEN (2U)
+#define GLB_REG_GPIO_20_DRV_MSK \
+ (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
+#define GLB_REG_GPIO_20_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
+#define GLB_REG_GPIO_20_PU GLB_REG_GPIO_20_PU
+#define GLB_REG_GPIO_20_PU_POS (4U)
+#define GLB_REG_GPIO_20_PU_LEN (1U)
+#define GLB_REG_GPIO_20_PU_MSK \
+ (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
+#define GLB_REG_GPIO_20_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
+#define GLB_REG_GPIO_20_PD GLB_REG_GPIO_20_PD
+#define GLB_REG_GPIO_20_PD_POS (5U)
+#define GLB_REG_GPIO_20_PD_LEN (1U)
+#define GLB_REG_GPIO_20_PD_MSK \
+ (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
+#define GLB_REG_GPIO_20_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
+#define GLB_REG_GPIO_20_FUNC_SEL GLB_REG_GPIO_20_FUNC_SEL
+#define GLB_REG_GPIO_20_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_20_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_20_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
+#define GLB_REG_GPIO_20_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_20_FUNC_SEL_POS))
+#define GLB_REG_GPIO_21_IE GLB_REG_GPIO_21_IE
+#define GLB_REG_GPIO_21_IE_POS (16U)
+#define GLB_REG_GPIO_21_IE_LEN (1U)
+#define GLB_REG_GPIO_21_IE_MSK \
+ (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
+#define GLB_REG_GPIO_21_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
+#define GLB_REG_GPIO_21_SMT GLB_REG_GPIO_21_SMT
+#define GLB_REG_GPIO_21_SMT_POS (17U)
+#define GLB_REG_GPIO_21_SMT_LEN (1U)
+#define GLB_REG_GPIO_21_SMT_MSK \
+ (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
+#define GLB_REG_GPIO_21_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
+#define GLB_REG_GPIO_21_DRV GLB_REG_GPIO_21_DRV
+#define GLB_REG_GPIO_21_DRV_POS (18U)
+#define GLB_REG_GPIO_21_DRV_LEN (2U)
+#define GLB_REG_GPIO_21_DRV_MSK \
+ (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
+#define GLB_REG_GPIO_21_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
+#define GLB_REG_GPIO_21_PU GLB_REG_GPIO_21_PU
+#define GLB_REG_GPIO_21_PU_POS (20U)
+#define GLB_REG_GPIO_21_PU_LEN (1U)
+#define GLB_REG_GPIO_21_PU_MSK \
+ (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
+#define GLB_REG_GPIO_21_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
+#define GLB_REG_GPIO_21_PD GLB_REG_GPIO_21_PD
+#define GLB_REG_GPIO_21_PD_POS (21U)
+#define GLB_REG_GPIO_21_PD_LEN (1U)
+#define GLB_REG_GPIO_21_PD_MSK \
+ (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
+#define GLB_REG_GPIO_21_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
+#define GLB_REG_GPIO_21_FUNC_SEL GLB_REG_GPIO_21_FUNC_SEL
+#define GLB_REG_GPIO_21_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_21_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_21_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
+#define GLB_REG_GPIO_21_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_21_FUNC_SEL_POS))
+
+/* 0x12C : GPIO_CFGCTL11 */
+
+#define GLB_GPIO_CFGCTL11_OFFSET (0x12C)
+#define GLB_REG_GPIO_22_IE GLB_REG_GPIO_22_IE
+#define GLB_REG_GPIO_22_IE_POS (0U)
+#define GLB_REG_GPIO_22_IE_LEN (1U)
+#define GLB_REG_GPIO_22_IE_MSK \
+ (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
+#define GLB_REG_GPIO_22_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
+#define GLB_REG_GPIO_22_SMT GLB_REG_GPIO_22_SMT
+#define GLB_REG_GPIO_22_SMT_POS (1U)
+#define GLB_REG_GPIO_22_SMT_LEN (1U)
+#define GLB_REG_GPIO_22_SMT_MSK \
+ (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
+#define GLB_REG_GPIO_22_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
+#define GLB_REG_GPIO_22_DRV GLB_REG_GPIO_22_DRV
+#define GLB_REG_GPIO_22_DRV_POS (2U)
+#define GLB_REG_GPIO_22_DRV_LEN (2U)
+#define GLB_REG_GPIO_22_DRV_MSK \
+ (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
+#define GLB_REG_GPIO_22_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
+#define GLB_REG_GPIO_22_PU GLB_REG_GPIO_22_PU
+#define GLB_REG_GPIO_22_PU_POS (4U)
+#define GLB_REG_GPIO_22_PU_LEN (1U)
+#define GLB_REG_GPIO_22_PU_MSK \
+ (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
+#define GLB_REG_GPIO_22_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
+#define GLB_REG_GPIO_22_PD GLB_REG_GPIO_22_PD
+#define GLB_REG_GPIO_22_PD_POS (5U)
+#define GLB_REG_GPIO_22_PD_LEN (1U)
+#define GLB_REG_GPIO_22_PD_MSK \
+ (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
+#define GLB_REG_GPIO_22_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
+#define GLB_REG_GPIO_22_FUNC_SEL GLB_REG_GPIO_22_FUNC_SEL
+#define GLB_REG_GPIO_22_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_22_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_22_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
+#define GLB_REG_GPIO_22_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_22_FUNC_SEL_POS))
+#define GLB_REG_GPIO_23_IE GLB_REG_GPIO_23_IE
+#define GLB_REG_GPIO_23_IE_POS (16U)
+#define GLB_REG_GPIO_23_IE_LEN (1U)
+#define GLB_REG_GPIO_23_IE_MSK \
+ (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
+#define GLB_REG_GPIO_23_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
+#define GLB_REG_GPIO_23_SMT GLB_REG_GPIO_23_SMT
+#define GLB_REG_GPIO_23_SMT_POS (17U)
+#define GLB_REG_GPIO_23_SMT_LEN (1U)
+#define GLB_REG_GPIO_23_SMT_MSK \
+ (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
+#define GLB_REG_GPIO_23_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
+#define GLB_REG_GPIO_23_DRV GLB_REG_GPIO_23_DRV
+#define GLB_REG_GPIO_23_DRV_POS (18U)
+#define GLB_REG_GPIO_23_DRV_LEN (2U)
+#define GLB_REG_GPIO_23_DRV_MSK \
+ (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
+#define GLB_REG_GPIO_23_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
+#define GLB_REG_GPIO_23_PU GLB_REG_GPIO_23_PU
+#define GLB_REG_GPIO_23_PU_POS (20U)
+#define GLB_REG_GPIO_23_PU_LEN (1U)
+#define GLB_REG_GPIO_23_PU_MSK \
+ (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
+#define GLB_REG_GPIO_23_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
+#define GLB_REG_GPIO_23_PD GLB_REG_GPIO_23_PD
+#define GLB_REG_GPIO_23_PD_POS (21U)
+#define GLB_REG_GPIO_23_PD_LEN (1U)
+#define GLB_REG_GPIO_23_PD_MSK \
+ (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
+#define GLB_REG_GPIO_23_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
+
+/* 0x130 : GPIO_CFGCTL12 */
+
+#define GLB_GPIO_CFGCTL12_OFFSET (0x130)
+#define GLB_REG_GPIO_24_IE GLB_REG_GPIO_24_IE
+#define GLB_REG_GPIO_24_IE_POS (0U)
+#define GLB_REG_GPIO_24_IE_LEN (1U)
+#define GLB_REG_GPIO_24_IE_MSK \
+ (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
+#define GLB_REG_GPIO_24_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
+#define GLB_REG_GPIO_24_SMT GLB_REG_GPIO_24_SMT
+#define GLB_REG_GPIO_24_SMT_POS (1U)
+#define GLB_REG_GPIO_24_SMT_LEN (1U)
+#define GLB_REG_GPIO_24_SMT_MSK \
+ (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
+#define GLB_REG_GPIO_24_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
+#define GLB_REG_GPIO_24_DRV GLB_REG_GPIO_24_DRV
+#define GLB_REG_GPIO_24_DRV_POS (2U)
+#define GLB_REG_GPIO_24_DRV_LEN (2U)
+#define GLB_REG_GPIO_24_DRV_MSK \
+ (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
+#define GLB_REG_GPIO_24_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
+#define GLB_REG_GPIO_24_PU GLB_REG_GPIO_24_PU
+#define GLB_REG_GPIO_24_PU_POS (4U)
+#define GLB_REG_GPIO_24_PU_LEN (1U)
+#define GLB_REG_GPIO_24_PU_MSK \
+ (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
+#define GLB_REG_GPIO_24_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
+#define GLB_REG_GPIO_24_PD GLB_REG_GPIO_24_PD
+#define GLB_REG_GPIO_24_PD_POS (5U)
+#define GLB_REG_GPIO_24_PD_LEN (1U)
+#define GLB_REG_GPIO_24_PD_MSK \
+ (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
+#define GLB_REG_GPIO_24_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
+#define GLB_REG_GPIO_25_IE GLB_REG_GPIO_25_IE
+#define GLB_REG_GPIO_25_IE_POS (16U)
+#define GLB_REG_GPIO_25_IE_LEN (1U)
+#define GLB_REG_GPIO_25_IE_MSK \
+ (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
+#define GLB_REG_GPIO_25_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
+#define GLB_REG_GPIO_25_SMT GLB_REG_GPIO_25_SMT
+#define GLB_REG_GPIO_25_SMT_POS (17U)
+#define GLB_REG_GPIO_25_SMT_LEN (1U)
+#define GLB_REG_GPIO_25_SMT_MSK \
+ (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
+#define GLB_REG_GPIO_25_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
+#define GLB_REG_GPIO_25_DRV GLB_REG_GPIO_25_DRV
+#define GLB_REG_GPIO_25_DRV_POS (18U)
+#define GLB_REG_GPIO_25_DRV_LEN (2U)
+#define GLB_REG_GPIO_25_DRV_MSK \
+ (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
+#define GLB_REG_GPIO_25_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
+#define GLB_REG_GPIO_25_PU GLB_REG_GPIO_25_PU
+#define GLB_REG_GPIO_25_PU_POS (20U)
+#define GLB_REG_GPIO_25_PU_LEN (1U)
+#define GLB_REG_GPIO_25_PU_MSK \
+ (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
+#define GLB_REG_GPIO_25_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
+#define GLB_REG_GPIO_25_PD GLB_REG_GPIO_25_PD
+#define GLB_REG_GPIO_25_PD_POS (21U)
+#define GLB_REG_GPIO_25_PD_LEN (1U)
+#define GLB_REG_GPIO_25_PD_MSK \
+ (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
+#define GLB_REG_GPIO_25_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
+
+/* 0x134 : GPIO_CFGCTL13 */
+
+#define GLB_GPIO_CFGCTL13_OFFSET (0x134)
+#define GLB_REG_GPIO_26_IE GLB_REG_GPIO_26_IE
+#define GLB_REG_GPIO_26_IE_POS (0U)
+#define GLB_REG_GPIO_26_IE_LEN (1U)
+#define GLB_REG_GPIO_26_IE_MSK \
+ (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
+#define GLB_REG_GPIO_26_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
+#define GLB_REG_GPIO_26_SMT GLB_REG_GPIO_26_SMT
+#define GLB_REG_GPIO_26_SMT_POS (1U)
+#define GLB_REG_GPIO_26_SMT_LEN (1U)
+#define GLB_REG_GPIO_26_SMT_MSK \
+ (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
+#define GLB_REG_GPIO_26_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
+#define GLB_REG_GPIO_26_DRV GLB_REG_GPIO_26_DRV
+#define GLB_REG_GPIO_26_DRV_POS (2U)
+#define GLB_REG_GPIO_26_DRV_LEN (2U)
+#define GLB_REG_GPIO_26_DRV_MSK \
+ (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
+#define GLB_REG_GPIO_26_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
+#define GLB_REG_GPIO_26_PU GLB_REG_GPIO_26_PU
+#define GLB_REG_GPIO_26_PU_POS (4U)
+#define GLB_REG_GPIO_26_PU_LEN (1U)
+#define GLB_REG_GPIO_26_PU_MSK \
+ (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
+#define GLB_REG_GPIO_26_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
+#define GLB_REG_GPIO_26_PD GLB_REG_GPIO_26_PD
+#define GLB_REG_GPIO_26_PD_POS (5U)
+#define GLB_REG_GPIO_26_PD_LEN (1U)
+#define GLB_REG_GPIO_26_PD_MSK \
+ (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
+#define GLB_REG_GPIO_26_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
+#define GLB_REG_GPIO_27_IE GLB_REG_GPIO_27_IE
+#define GLB_REG_GPIO_27_IE_POS (16U)
+#define GLB_REG_GPIO_27_IE_LEN (1U)
+#define GLB_REG_GPIO_27_IE_MSK \
+ (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
+#define GLB_REG_GPIO_27_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
+#define GLB_REG_GPIO_27_SMT GLB_REG_GPIO_27_SMT
+#define GLB_REG_GPIO_27_SMT_POS (17U)
+#define GLB_REG_GPIO_27_SMT_LEN (1U)
+#define GLB_REG_GPIO_27_SMT_MSK \
+ (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
+#define GLB_REG_GPIO_27_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
+#define GLB_REG_GPIO_27_DRV GLB_REG_GPIO_27_DRV
+#define GLB_REG_GPIO_27_DRV_POS (18U)
+#define GLB_REG_GPIO_27_DRV_LEN (2U)
+#define GLB_REG_GPIO_27_DRV_MSK \
+ (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
+#define GLB_REG_GPIO_27_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
+#define GLB_REG_GPIO_27_PU GLB_REG_GPIO_27_PU
+#define GLB_REG_GPIO_27_PU_POS (20U)
+#define GLB_REG_GPIO_27_PU_LEN (1U)
+#define GLB_REG_GPIO_27_PU_MSK \
+ (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
+#define GLB_REG_GPIO_27_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
+#define GLB_REG_GPIO_27_PD GLB_REG_GPIO_27_PD
+#define GLB_REG_GPIO_27_PD_POS (21U)
+#define GLB_REG_GPIO_27_PD_LEN (1U)
+#define GLB_REG_GPIO_27_PD_MSK \
+ (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
+#define GLB_REG_GPIO_27_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
+
+/* 0x138 : GPIO_CFGCTL14 */
+
+#define GLB_GPIO_CFGCTL14_OFFSET (0x138)
+#define GLB_REG_GPIO_28_IE GLB_REG_GPIO_28_IE
+#define GLB_REG_GPIO_28_IE_POS (0U)
+#define GLB_REG_GPIO_28_IE_LEN (1U)
+#define GLB_REG_GPIO_28_IE_MSK \
+ (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
+#define GLB_REG_GPIO_28_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
+#define GLB_REG_GPIO_28_SMT GLB_REG_GPIO_28_SMT
+#define GLB_REG_GPIO_28_SMT_POS (1U)
+#define GLB_REG_GPIO_28_SMT_LEN (1U)
+#define GLB_REG_GPIO_28_SMT_MSK \
+ (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
+#define GLB_REG_GPIO_28_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
+#define GLB_REG_GPIO_28_DRV GLB_REG_GPIO_28_DRV
+#define GLB_REG_GPIO_28_DRV_POS (2U)
+#define GLB_REG_GPIO_28_DRV_LEN (2U)
+#define GLB_REG_GPIO_28_DRV_MSK \
+ (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
+#define GLB_REG_GPIO_28_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
+#define GLB_REG_GPIO_28_PU GLB_REG_GPIO_28_PU
+#define GLB_REG_GPIO_28_PU_POS (4U)
+#define GLB_REG_GPIO_28_PU_LEN (1U)
+#define GLB_REG_GPIO_28_PU_MSK \
+ (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
+#define GLB_REG_GPIO_28_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
+#define GLB_REG_GPIO_28_PD GLB_REG_GPIO_28_PD
+#define GLB_REG_GPIO_28_PD_POS (5U)
+#define GLB_REG_GPIO_28_PD_LEN (1U)
+#define GLB_REG_GPIO_28_PD_MSK \
+ (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
+#define GLB_REG_GPIO_28_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
+
+/* 0x180 : GPIO_CFGCTL30 */
+
+#define GLB_GPIO_CFGCTL30_OFFSET (0x180)
+#define GLB_REG_GPIO_0_I GLB_REG_GPIO_0_I
+#define GLB_REG_GPIO_0_I_POS (0U)
+#define GLB_REG_GPIO_0_I_LEN (1U)
+#define GLB_REG_GPIO_0_I_MSK \
+ (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
+#define GLB_REG_GPIO_0_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
+#define GLB_REG_GPIO_1_I GLB_REG_GPIO_1_I
+#define GLB_REG_GPIO_1_I_POS (1U)
+#define GLB_REG_GPIO_1_I_LEN (1U)
+#define GLB_REG_GPIO_1_I_MSK \
+ (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
+#define GLB_REG_GPIO_1_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
+#define GLB_REG_GPIO_2_I GLB_REG_GPIO_2_I
+#define GLB_REG_GPIO_2_I_POS (2U)
+#define GLB_REG_GPIO_2_I_LEN (1U)
+#define GLB_REG_GPIO_2_I_MSK \
+ (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
+#define GLB_REG_GPIO_2_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
+#define GLB_REG_GPIO_3_I GLB_REG_GPIO_3_I
+#define GLB_REG_GPIO_3_I_POS (3U)
+#define GLB_REG_GPIO_3_I_LEN (1U)
+#define GLB_REG_GPIO_3_I_MSK \
+ (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
+#define GLB_REG_GPIO_3_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
+#define GLB_REG_GPIO_4_I GLB_REG_GPIO_4_I
+#define GLB_REG_GPIO_4_I_POS (4U)
+#define GLB_REG_GPIO_4_I_LEN (1U)
+#define GLB_REG_GPIO_4_I_MSK \
+ (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
+#define GLB_REG_GPIO_4_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
+#define GLB_REG_GPIO_5_I GLB_REG_GPIO_5_I
+#define GLB_REG_GPIO_5_I_POS (5U)
+#define GLB_REG_GPIO_5_I_LEN (1U)
+#define GLB_REG_GPIO_5_I_MSK \
+ (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
+#define GLB_REG_GPIO_5_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
+#define GLB_REG_GPIO_6_I GLB_REG_GPIO_6_I
+#define GLB_REG_GPIO_6_I_POS (6U)
+#define GLB_REG_GPIO_6_I_LEN (1U)
+#define GLB_REG_GPIO_6_I_MSK \
+ (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
+#define GLB_REG_GPIO_6_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
+#define GLB_REG_GPIO_7_I GLB_REG_GPIO_7_I
+#define GLB_REG_GPIO_7_I_POS (7U)
+#define GLB_REG_GPIO_7_I_LEN (1U)
+#define GLB_REG_GPIO_7_I_MSK \
+ (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
+#define GLB_REG_GPIO_7_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
+#define GLB_REG_GPIO_8_I GLB_REG_GPIO_8_I
+#define GLB_REG_GPIO_8_I_POS (8U)
+#define GLB_REG_GPIO_8_I_LEN (1U)
+#define GLB_REG_GPIO_8_I_MSK \
+ (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
+#define GLB_REG_GPIO_8_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
+#define GLB_REG_GPIO_9_I GLB_REG_GPIO_9_I
+#define GLB_REG_GPIO_9_I_POS (9U)
+#define GLB_REG_GPIO_9_I_LEN (1U)
+#define GLB_REG_GPIO_9_I_MSK \
+ (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
+#define GLB_REG_GPIO_9_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
+#define GLB_REG_GPIO_10_I GLB_REG_GPIO_10_I
+#define GLB_REG_GPIO_10_I_POS (10U)
+#define GLB_REG_GPIO_10_I_LEN (1U)
+#define GLB_REG_GPIO_10_I_MSK \
+ (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
+#define GLB_REG_GPIO_10_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
+#define GLB_REG_GPIO_11_I GLB_REG_GPIO_11_I
+#define GLB_REG_GPIO_11_I_POS (11U)
+#define GLB_REG_GPIO_11_I_LEN (1U)
+#define GLB_REG_GPIO_11_I_MSK \
+ (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
+#define GLB_REG_GPIO_11_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
+#define GLB_REG_GPIO_12_I GLB_REG_GPIO_12_I
+#define GLB_REG_GPIO_12_I_POS (12U)
+#define GLB_REG_GPIO_12_I_LEN (1U)
+#define GLB_REG_GPIO_12_I_MSK \
+ (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
+#define GLB_REG_GPIO_12_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
+#define GLB_REG_GPIO_13_I GLB_REG_GPIO_13_I
+#define GLB_REG_GPIO_13_I_POS (13U)
+#define GLB_REG_GPIO_13_I_LEN (1U)
+#define GLB_REG_GPIO_13_I_MSK \
+ (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
+#define GLB_REG_GPIO_13_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
+#define GLB_REG_GPIO_14_I GLB_REG_GPIO_14_I
+#define GLB_REG_GPIO_14_I_POS (14U)
+#define GLB_REG_GPIO_14_I_LEN (1U)
+#define GLB_REG_GPIO_14_I_MSK \
+ (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
+#define GLB_REG_GPIO_14_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
+#define GLB_REG_GPIO_15_I GLB_REG_GPIO_15_I
+#define GLB_REG_GPIO_15_I_POS (15U)
+#define GLB_REG_GPIO_15_I_LEN (1U)
+#define GLB_REG_GPIO_15_I_MSK \
+ (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
+#define GLB_REG_GPIO_15_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
+#define GLB_REG_GPIO_16_I GLB_REG_GPIO_16_I
+#define GLB_REG_GPIO_16_I_POS (16U)
+#define GLB_REG_GPIO_16_I_LEN (1U)
+#define GLB_REG_GPIO_16_I_MSK \
+ (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
+#define GLB_REG_GPIO_16_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
+#define GLB_REG_GPIO_17_I GLB_REG_GPIO_17_I
+#define GLB_REG_GPIO_17_I_POS (17U)
+#define GLB_REG_GPIO_17_I_LEN (1U)
+#define GLB_REG_GPIO_17_I_MSK \
+ (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
+#define GLB_REG_GPIO_17_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
+#define GLB_REG_GPIO_18_I GLB_REG_GPIO_18_I
+#define GLB_REG_GPIO_18_I_POS (18U)
+#define GLB_REG_GPIO_18_I_LEN (1U)
+#define GLB_REG_GPIO_18_I_MSK \
+ (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
+#define GLB_REG_GPIO_18_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
+#define GLB_REG_GPIO_19_I GLB_REG_GPIO_19_I
+#define GLB_REG_GPIO_19_I_POS (19U)
+#define GLB_REG_GPIO_19_I_LEN (1U)
+#define GLB_REG_GPIO_19_I_MSK \
+ (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
+#define GLB_REG_GPIO_19_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
+#define GLB_REG_GPIO_20_I GLB_REG_GPIO_20_I
+#define GLB_REG_GPIO_20_I_POS (20U)
+#define GLB_REG_GPIO_20_I_LEN (1U)
+#define GLB_REG_GPIO_20_I_MSK \
+ (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
+#define GLB_REG_GPIO_20_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
+#define GLB_REG_GPIO_21_I GLB_REG_GPIO_21_I
+#define GLB_REG_GPIO_21_I_POS (21U)
+#define GLB_REG_GPIO_21_I_LEN (1U)
+#define GLB_REG_GPIO_21_I_MSK \
+ (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
+#define GLB_REG_GPIO_21_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
+#define GLB_REG_GPIO_22_I GLB_REG_GPIO_22_I
+#define GLB_REG_GPIO_22_I_POS (22U)
+#define GLB_REG_GPIO_22_I_LEN (1U)
+#define GLB_REG_GPIO_22_I_MSK \
+ (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
+#define GLB_REG_GPIO_22_I_UMSK \
+ (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
+
+/* 0x184 : GPIO_CFGCTL31 */
+
+#define GLB_GPIO_CFGCTL31_OFFSET (0x184)
+
+/* 0x188 : GPIO_CFGCTL32 */
+
+#define GLB_GPIO_CFGCTL32_OFFSET (0x188)
+#define GLB_REG_GPIO_0_O GLB_REG_GPIO_0_O
+#define GLB_REG_GPIO_0_O_POS (0U)
+#define GLB_REG_GPIO_0_O_LEN (1U)
+#define GLB_REG_GPIO_0_O_MSK \
+ (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
+#define GLB_REG_GPIO_0_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
+#define GLB_REG_GPIO_1_O GLB_REG_GPIO_1_O
+#define GLB_REG_GPIO_1_O_POS (1U)
+#define GLB_REG_GPIO_1_O_LEN (1U)
+#define GLB_REG_GPIO_1_O_MSK \
+ (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
+#define GLB_REG_GPIO_1_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
+#define GLB_REG_GPIO_2_O GLB_REG_GPIO_2_O
+#define GLB_REG_GPIO_2_O_POS (2U)
+#define GLB_REG_GPIO_2_O_LEN (1U)
+#define GLB_REG_GPIO_2_O_MSK \
+ (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
+#define GLB_REG_GPIO_2_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
+#define GLB_REG_GPIO_3_O GLB_REG_GPIO_3_O
+#define GLB_REG_GPIO_3_O_POS (3U)
+#define GLB_REG_GPIO_3_O_LEN (1U)
+#define GLB_REG_GPIO_3_O_MSK \
+ (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
+#define GLB_REG_GPIO_3_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
+#define GLB_REG_GPIO_4_O GLB_REG_GPIO_4_O
+#define GLB_REG_GPIO_4_O_POS (4U)
+#define GLB_REG_GPIO_4_O_LEN (1U)
+#define GLB_REG_GPIO_4_O_MSK \
+ (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
+#define GLB_REG_GPIO_4_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
+#define GLB_REG_GPIO_5_O GLB_REG_GPIO_5_O
+#define GLB_REG_GPIO_5_O_POS (5U)
+#define GLB_REG_GPIO_5_O_LEN (1U)
+#define GLB_REG_GPIO_5_O_MSK \
+ (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
+#define GLB_REG_GPIO_5_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
+#define GLB_REG_GPIO_6_O GLB_REG_GPIO_6_O
+#define GLB_REG_GPIO_6_O_POS (6U)
+#define GLB_REG_GPIO_6_O_LEN (1U)
+#define GLB_REG_GPIO_6_O_MSK \
+ (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
+#define GLB_REG_GPIO_6_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
+#define GLB_REG_GPIO_7_O GLB_REG_GPIO_7_O
+#define GLB_REG_GPIO_7_O_POS (7U)
+#define GLB_REG_GPIO_7_O_LEN (1U)
+#define GLB_REG_GPIO_7_O_MSK \
+ (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
+#define GLB_REG_GPIO_7_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
+#define GLB_REG_GPIO_8_O GLB_REG_GPIO_8_O
+#define GLB_REG_GPIO_8_O_POS (8U)
+#define GLB_REG_GPIO_8_O_LEN (1U)
+#define GLB_REG_GPIO_8_O_MSK \
+ (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
+#define GLB_REG_GPIO_8_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
+#define GLB_REG_GPIO_9_O GLB_REG_GPIO_9_O
+#define GLB_REG_GPIO_9_O_POS (9U)
+#define GLB_REG_GPIO_9_O_LEN (1U)
+#define GLB_REG_GPIO_9_O_MSK \
+ (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
+#define GLB_REG_GPIO_9_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
+#define GLB_REG_GPIO_10_O GLB_REG_GPIO_10_O
+#define GLB_REG_GPIO_10_O_POS (10U)
+#define GLB_REG_GPIO_10_O_LEN (1U)
+#define GLB_REG_GPIO_10_O_MSK \
+ (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
+#define GLB_REG_GPIO_10_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
+#define GLB_REG_GPIO_11_O GLB_REG_GPIO_11_O
+#define GLB_REG_GPIO_11_O_POS (11U)
+#define GLB_REG_GPIO_11_O_LEN (1U)
+#define GLB_REG_GPIO_11_O_MSK \
+ (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
+#define GLB_REG_GPIO_11_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
+#define GLB_REG_GPIO_12_O GLB_REG_GPIO_12_O
+#define GLB_REG_GPIO_12_O_POS (12U)
+#define GLB_REG_GPIO_12_O_LEN (1U)
+#define GLB_REG_GPIO_12_O_MSK \
+ (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
+#define GLB_REG_GPIO_12_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
+#define GLB_REG_GPIO_13_O GLB_REG_GPIO_13_O
+#define GLB_REG_GPIO_13_O_POS (13U)
+#define GLB_REG_GPIO_13_O_LEN (1U)
+#define GLB_REG_GPIO_13_O_MSK \
+ (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
+#define GLB_REG_GPIO_13_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
+#define GLB_REG_GPIO_14_O GLB_REG_GPIO_14_O
+#define GLB_REG_GPIO_14_O_POS (14U)
+#define GLB_REG_GPIO_14_O_LEN (1U)
+#define GLB_REG_GPIO_14_O_MSK \
+ (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
+#define GLB_REG_GPIO_14_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
+#define GLB_REG_GPIO_15_O GLB_REG_GPIO_15_O
+#define GLB_REG_GPIO_15_O_POS (15U)
+#define GLB_REG_GPIO_15_O_LEN (1U)
+#define GLB_REG_GPIO_15_O_MSK \
+ (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
+#define GLB_REG_GPIO_15_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
+#define GLB_REG_GPIO_16_O GLB_REG_GPIO_16_O
+#define GLB_REG_GPIO_16_O_POS (16U)
+#define GLB_REG_GPIO_16_O_LEN (1U)
+#define GLB_REG_GPIO_16_O_MSK \
+ (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
+#define GLB_REG_GPIO_16_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
+#define GLB_REG_GPIO_17_O GLB_REG_GPIO_17_O
+#define GLB_REG_GPIO_17_O_POS (17U)
+#define GLB_REG_GPIO_17_O_LEN (1U)
+#define GLB_REG_GPIO_17_O_MSK \
+ (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
+#define GLB_REG_GPIO_17_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
+#define GLB_REG_GPIO_18_O GLB_REG_GPIO_18_O
+#define GLB_REG_GPIO_18_O_POS (18U)
+#define GLB_REG_GPIO_18_O_LEN (1U)
+#define GLB_REG_GPIO_18_O_MSK \
+ (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
+#define GLB_REG_GPIO_18_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
+#define GLB_REG_GPIO_19_O GLB_REG_GPIO_19_O
+#define GLB_REG_GPIO_19_O_POS (19U)
+#define GLB_REG_GPIO_19_O_LEN (1U)
+#define GLB_REG_GPIO_19_O_MSK \
+ (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
+#define GLB_REG_GPIO_19_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
+#define GLB_REG_GPIO_20_O GLB_REG_GPIO_20_O
+#define GLB_REG_GPIO_20_O_POS (20U)
+#define GLB_REG_GPIO_20_O_LEN (1U)
+#define GLB_REG_GPIO_20_O_MSK \
+ (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
+#define GLB_REG_GPIO_20_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
+#define GLB_REG_GPIO_21_O GLB_REG_GPIO_21_O
+#define GLB_REG_GPIO_21_O_POS (21U)
+#define GLB_REG_GPIO_21_O_LEN (1U)
+#define GLB_REG_GPIO_21_O_MSK \
+ (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
+#define GLB_REG_GPIO_21_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
+#define GLB_REG_GPIO_22_O GLB_REG_GPIO_22_O
+#define GLB_REG_GPIO_22_O_POS (22U)
+#define GLB_REG_GPIO_22_O_LEN (1U)
+#define GLB_REG_GPIO_22_O_MSK \
+ (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
+#define GLB_REG_GPIO_22_O_UMSK \
+ (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
+
+/* 0x18C : GPIO_CFGCTL33 */
+
+#define GLB_GPIO_CFGCTL33_OFFSET (0x18C)
+
+/* 0x190 : GPIO_CFGCTL34 */
+
+#define GLB_GPIO_CFGCTL34_OFFSET (0x190)
+#define GLB_REG_GPIO_0_OE GLB_REG_GPIO_0_OE
+#define GLB_REG_GPIO_0_OE_POS (0U)
+#define GLB_REG_GPIO_0_OE_LEN (1U)
+#define GLB_REG_GPIO_0_OE_MSK \
+ (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
+#define GLB_REG_GPIO_0_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
+#define GLB_REG_GPIO_1_OE GLB_REG_GPIO_1_OE
+#define GLB_REG_GPIO_1_OE_POS (1U)
+#define GLB_REG_GPIO_1_OE_LEN (1U)
+#define GLB_REG_GPIO_1_OE_MSK \
+ (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
+#define GLB_REG_GPIO_1_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
+#define GLB_REG_GPIO_2_OE GLB_REG_GPIO_2_OE
+#define GLB_REG_GPIO_2_OE_POS (2U)
+#define GLB_REG_GPIO_2_OE_LEN (1U)
+#define GLB_REG_GPIO_2_OE_MSK \
+ (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
+#define GLB_REG_GPIO_2_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
+#define GLB_REG_GPIO_3_OE GLB_REG_GPIO_3_OE
+#define GLB_REG_GPIO_3_OE_POS (3U)
+#define GLB_REG_GPIO_3_OE_LEN (1U)
+#define GLB_REG_GPIO_3_OE_MSK \
+ (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
+#define GLB_REG_GPIO_3_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
+#define GLB_REG_GPIO_4_OE GLB_REG_GPIO_4_OE
+#define GLB_REG_GPIO_4_OE_POS (4U)
+#define GLB_REG_GPIO_4_OE_LEN (1U)
+#define GLB_REG_GPIO_4_OE_MSK \
+ (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
+#define GLB_REG_GPIO_4_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
+#define GLB_REG_GPIO_5_OE GLB_REG_GPIO_5_OE
+#define GLB_REG_GPIO_5_OE_POS (5U)
+#define GLB_REG_GPIO_5_OE_LEN (1U)
+#define GLB_REG_GPIO_5_OE_MSK \
+ (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
+#define GLB_REG_GPIO_5_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
+#define GLB_REG_GPIO_6_OE GLB_REG_GPIO_6_OE
+#define GLB_REG_GPIO_6_OE_POS (6U)
+#define GLB_REG_GPIO_6_OE_LEN (1U)
+#define GLB_REG_GPIO_6_OE_MSK \
+ (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
+#define GLB_REG_GPIO_6_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
+#define GLB_REG_GPIO_7_OE GLB_REG_GPIO_7_OE
+#define GLB_REG_GPIO_7_OE_POS (7U)
+#define GLB_REG_GPIO_7_OE_LEN (1U)
+#define GLB_REG_GPIO_7_OE_MSK \
+ (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
+#define GLB_REG_GPIO_7_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
+#define GLB_REG_GPIO_8_OE GLB_REG_GPIO_8_OE
+#define GLB_REG_GPIO_8_OE_POS (8U)
+#define GLB_REG_GPIO_8_OE_LEN (1U)
+#define GLB_REG_GPIO_8_OE_MSK \
+ (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
+#define GLB_REG_GPIO_8_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
+#define GLB_REG_GPIO_9_OE GLB_REG_GPIO_9_OE
+#define GLB_REG_GPIO_9_OE_POS (9U)
+#define GLB_REG_GPIO_9_OE_LEN (1U)
+#define GLB_REG_GPIO_9_OE_MSK \
+ (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
+#define GLB_REG_GPIO_9_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
+#define GLB_REG_GPIO_10_OE GLB_REG_GPIO_10_OE
+#define GLB_REG_GPIO_10_OE_POS (10U)
+#define GLB_REG_GPIO_10_OE_LEN (1U)
+#define GLB_REG_GPIO_10_OE_MSK \
+ (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
+#define GLB_REG_GPIO_10_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
+#define GLB_REG_GPIO_11_OE GLB_REG_GPIO_11_OE
+#define GLB_REG_GPIO_11_OE_POS (11U)
+#define GLB_REG_GPIO_11_OE_LEN (1U)
+#define GLB_REG_GPIO_11_OE_MSK \
+ (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
+#define GLB_REG_GPIO_11_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
+#define GLB_REG_GPIO_12_OE GLB_REG_GPIO_12_OE
+#define GLB_REG_GPIO_12_OE_POS (12U)
+#define GLB_REG_GPIO_12_OE_LEN (1U)
+#define GLB_REG_GPIO_12_OE_MSK \
+ (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
+#define GLB_REG_GPIO_12_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
+#define GLB_REG_GPIO_13_OE GLB_REG_GPIO_13_OE
+#define GLB_REG_GPIO_13_OE_POS (13U)
+#define GLB_REG_GPIO_13_OE_LEN (1U)
+#define GLB_REG_GPIO_13_OE_MSK \
+ (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
+#define GLB_REG_GPIO_13_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
+#define GLB_REG_GPIO_14_OE GLB_REG_GPIO_14_OE
+#define GLB_REG_GPIO_14_OE_POS (14U)
+#define GLB_REG_GPIO_14_OE_LEN (1U)
+#define GLB_REG_GPIO_14_OE_MSK \
+ (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
+#define GLB_REG_GPIO_14_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
+#define GLB_REG_GPIO_15_OE GLB_REG_GPIO_15_OE
+#define GLB_REG_GPIO_15_OE_POS (15U)
+#define GLB_REG_GPIO_15_OE_LEN (1U)
+#define GLB_REG_GPIO_15_OE_MSK \
+ (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
+#define GLB_REG_GPIO_15_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
+#define GLB_REG_GPIO_16_OE GLB_REG_GPIO_16_OE
+#define GLB_REG_GPIO_16_OE_POS (16U)
+#define GLB_REG_GPIO_16_OE_LEN (1U)
+#define GLB_REG_GPIO_16_OE_MSK \
+ (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
+#define GLB_REG_GPIO_16_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
+#define GLB_REG_GPIO_17_OE GLB_REG_GPIO_17_OE
+#define GLB_REG_GPIO_17_OE_POS (17U)
+#define GLB_REG_GPIO_17_OE_LEN (1U)
+#define GLB_REG_GPIO_17_OE_MSK \
+ (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
+#define GLB_REG_GPIO_17_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
+#define GLB_REG_GPIO_18_OE GLB_REG_GPIO_18_OE
+#define GLB_REG_GPIO_18_OE_POS (18U)
+#define GLB_REG_GPIO_18_OE_LEN (1U)
+#define GLB_REG_GPIO_18_OE_MSK \
+ (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
+#define GLB_REG_GPIO_18_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
+#define GLB_REG_GPIO_19_OE GLB_REG_GPIO_19_OE
+#define GLB_REG_GPIO_19_OE_POS (19U)
+#define GLB_REG_GPIO_19_OE_LEN (1U)
+#define GLB_REG_GPIO_19_OE_MSK \
+ (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
+#define GLB_REG_GPIO_19_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
+#define GLB_REG_GPIO_20_OE GLB_REG_GPIO_20_OE
+#define GLB_REG_GPIO_20_OE_POS (20U)
+#define GLB_REG_GPIO_20_OE_LEN (1U)
+#define GLB_REG_GPIO_20_OE_MSK \
+ (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
+#define GLB_REG_GPIO_20_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
+#define GLB_REG_GPIO_21_OE GLB_REG_GPIO_21_OE
+#define GLB_REG_GPIO_21_OE_POS (21U)
+#define GLB_REG_GPIO_21_OE_LEN (1U)
+#define GLB_REG_GPIO_21_OE_MSK \
+ (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
+#define GLB_REG_GPIO_21_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
+#define GLB_REG_GPIO_22_OE GLB_REG_GPIO_22_OE
+#define GLB_REG_GPIO_22_OE_POS (22U)
+#define GLB_REG_GPIO_22_OE_LEN (1U)
+#define GLB_REG_GPIO_22_OE_MSK \
+ (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
+#define GLB_REG_GPIO_22_OE_UMSK \
+ (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
+
+/* 0x194 : GPIO_CFGCTL35 */
+
+#define GLB_GPIO_CFGCTL35_OFFSET (0x194)
+
+/* 0x1A0 : GPIO_INT_MASK1 */
+
+#define GLB_GPIO_INT_MASK1_OFFSET (0x1A0)
+#define GLB_REG_GPIO_INT_MASK1 GLB_REG_GPIO_INT_MASK1
+#define GLB_REG_GPIO_INT_MASK1_POS (0U)
+#define GLB_REG_GPIO_INT_MASK1_LEN (32U)
+#define GLB_REG_GPIO_INT_MASK1_MSK \
+ (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)
+#define GLB_REG_GPIO_INT_MASK1_UMSK \
+ (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS))
+
+/* 0x1A8 : GPIO_INT_STAT1 */
+
+#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8)
+#define GLB_GPIO_INT_STAT1 GLB_GPIO_INT_STAT1
+#define GLB_GPIO_INT_STAT1_POS (0U)
+#define GLB_GPIO_INT_STAT1_LEN (32U)
+#define GLB_GPIO_INT_STAT1_MSK \
+ (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)
+#define GLB_GPIO_INT_STAT1_UMSK \
+ (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS))
+
+/* 0x1B0 : GPIO_INT_CLR1 */
+
+#define GLB_GPIO_INT_CLR1_OFFSET (0x1B0)
+#define GLB_REG_GPIO_INT_CLR1 GLB_REG_GPIO_INT_CLR1
+#define GLB_REG_GPIO_INT_CLR1_POS (0U)
+#define GLB_REG_GPIO_INT_CLR1_LEN (32U)
+#define GLB_REG_GPIO_INT_CLR1_MSK \
+ (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)
+#define GLB_REG_GPIO_INT_CLR1_UMSK \
+ (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS))
+
+/* 0x1C0 : GPIO_INT_MODE_SET1 */
+
+#define GLB_GPIO_INT_MODE_SET1_OFFSET (0x1C0)
+#define GLB_REG_GPIO_INT_MODE_SET1 GLB_REG_GPIO_INT_MODE_SET1
+#define GLB_REG_GPIO_INT_MODE_SET1_POS (0U)
+#define GLB_REG_GPIO_INT_MODE_SET1_LEN (32U)
+#define GLB_REG_GPIO_INT_MODE_SET1_MSK \
+ (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \
+ << GLB_REG_GPIO_INT_MODE_SET1_POS)
+#define GLB_REG_GPIO_INT_MODE_SET1_UMSK \
+ (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) \
+ << GLB_REG_GPIO_INT_MODE_SET1_POS))
+
+/* 0x1C4 : GPIO_INT_MODE_SET2 */
+
+#define GLB_GPIO_INT_MODE_SET2_OFFSET (0x1C4)
+#define GLB_REG_GPIO_INT_MODE_SET2 GLB_REG_GPIO_INT_MODE_SET2
+#define GLB_REG_GPIO_INT_MODE_SET2_POS (0U)
+#define GLB_REG_GPIO_INT_MODE_SET2_LEN (32U)
+#define GLB_REG_GPIO_INT_MODE_SET2_MSK \
+ (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \
+ << GLB_REG_GPIO_INT_MODE_SET2_POS)
+#define GLB_REG_GPIO_INT_MODE_SET2_UMSK \
+ (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) \
+ << GLB_REG_GPIO_INT_MODE_SET2_POS))
+
+/* 0x1C8 : GPIO_INT_MODE_SET3 */
+
+#define GLB_GPIO_INT_MODE_SET3_OFFSET (0x1C8)
+#define GLB_REG_GPIO_INT_MODE_SET3 GLB_REG_GPIO_INT_MODE_SET3
+#define GLB_REG_GPIO_INT_MODE_SET3_POS (0U)
+#define GLB_REG_GPIO_INT_MODE_SET3_LEN (32U)
+#define GLB_REG_GPIO_INT_MODE_SET3_MSK \
+ (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \
+ << GLB_REG_GPIO_INT_MODE_SET3_POS)
+#define GLB_REG_GPIO_INT_MODE_SET3_UMSK \
+ (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) \
+ << GLB_REG_GPIO_INT_MODE_SET3_POS))
+
+/* 0x224 : led_driver */
+
+#define GLB_LED_DRIVER_OFFSET (0x224)
+#define GLB_LED_DIN_REG GLB_LED_DIN_REG
+#define GLB_LED_DIN_REG_POS (0U)
+#define GLB_LED_DIN_REG_LEN (1U)
+#define GLB_LED_DIN_REG_MSK \
+ (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)
+#define GLB_LED_DIN_REG_UMSK \
+ (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS))
+#define GLB_LED_DIN_SEL GLB_LED_DIN_SEL
+#define GLB_LED_DIN_SEL_POS (1U)
+#define GLB_LED_DIN_SEL_LEN (1U)
+#define GLB_LED_DIN_SEL_MSK \
+ (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)
+#define GLB_LED_DIN_SEL_UMSK \
+ (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS))
+#define GLB_LED_DIN_POLARITY_SEL GLB_LED_DIN_POLARITY_SEL
+#define GLB_LED_DIN_POLARITY_SEL_POS (2U)
+#define GLB_LED_DIN_POLARITY_SEL_LEN (1U)
+#define GLB_LED_DIN_POLARITY_SEL_MSK \
+ (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)
+#define GLB_LED_DIN_POLARITY_SEL_UMSK \
+ (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) \
+ << GLB_LED_DIN_POLARITY_SEL_POS))
+#define GLB_LEDDRV_IBIAS GLB_LEDDRV_IBIAS
+#define GLB_LEDDRV_IBIAS_POS (4U)
+#define GLB_LEDDRV_IBIAS_LEN (4U)
+#define GLB_LEDDRV_IBIAS_MSK \
+ (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)
+#define GLB_LEDDRV_IBIAS_UMSK \
+ (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS))
+#define GLB_IR_RX_GPIO_SEL GLB_IR_RX_GPIO_SEL
+#define GLB_IR_RX_GPIO_SEL_POS (8U)
+#define GLB_IR_RX_GPIO_SEL_LEN (2U)
+#define GLB_IR_RX_GPIO_SEL_MSK \
+ (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
+#define GLB_IR_RX_GPIO_SEL_UMSK \
+ (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
+#define GLB_PU_LEDDRV GLB_PU_LEDDRV
+#define GLB_PU_LEDDRV_POS (31U)
+#define GLB_PU_LEDDRV_LEN (1U)
+#define GLB_PU_LEDDRV_MSK \
+ (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)
+#define GLB_PU_LEDDRV_UMSK \
+ (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS))
+
+/* 0x308 : gpdac_ctrl */
+
+#define GLB_GPDAC_CTRL_OFFSET (0x308)
+#define GLB_GPDACA_RSTN_ANA GLB_GPDACA_RSTN_ANA
+#define GLB_GPDACA_RSTN_ANA_POS (0U)
+#define GLB_GPDACA_RSTN_ANA_LEN (1U)
+#define GLB_GPDACA_RSTN_ANA_MSK \
+ (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
+#define GLB_GPDACA_RSTN_ANA_UMSK \
+ (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
+#define GLB_GPDACB_RSTN_ANA GLB_GPDACB_RSTN_ANA
+#define GLB_GPDACB_RSTN_ANA_POS (1U)
+#define GLB_GPDACB_RSTN_ANA_LEN (1U)
+#define GLB_GPDACB_RSTN_ANA_MSK \
+ (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
+#define GLB_GPDACB_RSTN_ANA_UMSK \
+ (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
+#define GLB_GPDAC_TEST_EN GLB_GPDAC_TEST_EN
+#define GLB_GPDAC_TEST_EN_POS (7U)
+#define GLB_GPDAC_TEST_EN_LEN (1U)
+#define GLB_GPDAC_TEST_EN_MSK \
+ (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
+#define GLB_GPDAC_TEST_EN_UMSK \
+ (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
+#define GLB_GPDAC_REF_SEL GLB_GPDAC_REF_SEL
+#define GLB_GPDAC_REF_SEL_POS (8U)
+#define GLB_GPDAC_REF_SEL_LEN (1U)
+#define GLB_GPDAC_REF_SEL_MSK \
+ (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
+#define GLB_GPDAC_REF_SEL_UMSK \
+ (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
+#define GLB_GPDAC_TEST_SEL GLB_GPDAC_TEST_SEL
+#define GLB_GPDAC_TEST_SEL_POS (9U)
+#define GLB_GPDAC_TEST_SEL_LEN (3U)
+#define GLB_GPDAC_TEST_SEL_MSK \
+ (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
+#define GLB_GPDAC_TEST_SEL_UMSK \
+ (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
+#define GLB_GPDAC_RESERVED GLB_GPDAC_RESERVED
+#define GLB_GPDAC_RESERVED_POS (24U)
+#define GLB_GPDAC_RESERVED_LEN (8U)
+#define GLB_GPDAC_RESERVED_MSK \
+ (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
+#define GLB_GPDAC_RESERVED_UMSK \
+ (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))
+
+/* 0x30C : gpdac_actrl */
+
+#define GLB_GPDAC_ACTRL_OFFSET (0x30C)
+#define GLB_GPDAC_A_EN GLB_GPDAC_A_EN
+#define GLB_GPDAC_A_EN_POS (0U)
+#define GLB_GPDAC_A_EN_LEN (1U)
+#define GLB_GPDAC_A_EN_MSK \
+ (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
+#define GLB_GPDAC_A_EN_UMSK \
+ (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
+#define GLB_GPDAC_IOA_EN GLB_GPDAC_IOA_EN
+#define GLB_GPDAC_IOA_EN_POS (1U)
+#define GLB_GPDAC_IOA_EN_LEN (1U)
+#define GLB_GPDAC_IOA_EN_MSK \
+ (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
+#define GLB_GPDAC_IOA_EN_UMSK \
+ (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
+#define GLB_GPDAC_A_RNG GLB_GPDAC_A_RNG
+#define GLB_GPDAC_A_RNG_POS (18U)
+#define GLB_GPDAC_A_RNG_LEN (2U)
+#define GLB_GPDAC_A_RNG_MSK \
+ (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
+#define GLB_GPDAC_A_RNG_UMSK \
+ (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
+#define GLB_GPDAC_A_OUTMUX GLB_GPDAC_A_OUTMUX
+#define GLB_GPDAC_A_OUTMUX_POS (20U)
+#define GLB_GPDAC_A_OUTMUX_LEN (3U)
+#define GLB_GPDAC_A_OUTMUX_MSK \
+ (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
+#define GLB_GPDAC_A_OUTMUX_UMSK \
+ (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))
+
+/* 0x310 : gpdac_bctrl */
+
+#define GLB_GPDAC_BCTRL_OFFSET (0x310)
+#define GLB_GPDAC_B_EN GLB_GPDAC_B_EN
+#define GLB_GPDAC_B_EN_POS (0U)
+#define GLB_GPDAC_B_EN_LEN (1U)
+#define GLB_GPDAC_B_EN_MSK \
+ (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
+#define GLB_GPDAC_B_EN_UMSK \
+ (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
+#define GLB_GPDAC_IOB_EN GLB_GPDAC_IOB_EN
+#define GLB_GPDAC_IOB_EN_POS (1U)
+#define GLB_GPDAC_IOB_EN_LEN (1U)
+#define GLB_GPDAC_IOB_EN_MSK \
+ (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
+#define GLB_GPDAC_IOB_EN_UMSK \
+ (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
+#define GLB_GPDAC_B_RNG GLB_GPDAC_B_RNG
+#define GLB_GPDAC_B_RNG_POS (18U)
+#define GLB_GPDAC_B_RNG_LEN (2U)
+#define GLB_GPDAC_B_RNG_MSK \
+ (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
+#define GLB_GPDAC_B_RNG_UMSK \
+ (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
+#define GLB_GPDAC_B_OUTMUX GLB_GPDAC_B_OUTMUX
+#define GLB_GPDAC_B_OUTMUX_POS (20U)
+#define GLB_GPDAC_B_OUTMUX_LEN (3U)
+#define GLB_GPDAC_B_OUTMUX_MSK \
+ (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
+#define GLB_GPDAC_B_OUTMUX_UMSK \
+ (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))
+
+/* 0x314 : gpdac_data */
+
+#define GLB_GPDAC_DATA_OFFSET (0x314)
+#define GLB_GPDAC_B_DATA GLB_GPDAC_B_DATA
+#define GLB_GPDAC_B_DATA_POS (0U)
+#define GLB_GPDAC_B_DATA_LEN (10U)
+#define GLB_GPDAC_B_DATA_MSK \
+ (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
+#define GLB_GPDAC_B_DATA_UMSK \
+ (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
+#define GLB_GPDAC_A_DATA GLB_GPDAC_A_DATA
+#define GLB_GPDAC_A_DATA_POS (16U)
+#define GLB_GPDAC_A_DATA_LEN (10U)
+#define GLB_GPDAC_A_DATA_MSK \
+ (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
+#define GLB_GPDAC_A_DATA_UMSK \
+ (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))
+
+/* 0xF00 : tzc_glb_ctrl_0 */
+
+#define GLB_TZC_GLB_CTRL_0_OFFSET (0xF00)
+#define GLB_TZC_GLB_SWRST_S00_LOCK GLB_TZC_GLB_SWRST_S00_LOCK
+#define GLB_TZC_GLB_SWRST_S00_LOCK_POS (0U)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S00_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S00_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S01_LOCK GLB_TZC_GLB_SWRST_S01_LOCK
+#define GLB_TZC_GLB_SWRST_S01_LOCK_POS (1U)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S01_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S01_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S30_LOCK GLB_TZC_GLB_SWRST_S30_LOCK
+#define GLB_TZC_GLB_SWRST_S30_LOCK_POS (8U)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S30_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S30_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK GLB_TZC_GLB_CTRL_PWRON_RST_LOCK
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS (12U)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK GLB_TZC_GLB_CTRL_CPU_RESET_LOCK
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS (13U)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK GLB_TZC_GLB_CTRL_SYS_RESET_LOCK
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS (14U)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS (15U)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS))
+#define GLB_TZC_GLB_MISC_LOCK GLB_TZC_GLB_MISC_LOCK
+#define GLB_TZC_GLB_MISC_LOCK_POS (25U)
+#define GLB_TZC_GLB_MISC_LOCK_LEN (1U)
+#define GLB_TZC_GLB_MISC_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
+#define GLB_TZC_GLB_MISC_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
+#define GLB_TZC_GLB_SRAM_LOCK GLB_TZC_GLB_SRAM_LOCK
+#define GLB_TZC_GLB_SRAM_LOCK_POS (26U)
+#define GLB_TZC_GLB_SRAM_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SRAM_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
+#define GLB_TZC_GLB_SRAM_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
+#define GLB_TZC_GLB_L2C_LOCK GLB_TZC_GLB_L2C_LOCK
+#define GLB_TZC_GLB_L2C_LOCK_POS (27U)
+#define GLB_TZC_GLB_L2C_LOCK_LEN (1U)
+#define GLB_TZC_GLB_L2C_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)
+#define GLB_TZC_GLB_L2C_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS))
+#define GLB_TZC_GLB_BMX_LOCK GLB_TZC_GLB_BMX_LOCK
+#define GLB_TZC_GLB_BMX_LOCK_POS (28U)
+#define GLB_TZC_GLB_BMX_LOCK_LEN (1U)
+#define GLB_TZC_GLB_BMX_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
+#define GLB_TZC_GLB_BMX_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
+#define GLB_TZC_GLB_DBG_LOCK GLB_TZC_GLB_DBG_LOCK
+#define GLB_TZC_GLB_DBG_LOCK_POS (29U)
+#define GLB_TZC_GLB_DBG_LOCK_LEN (1U)
+#define GLB_TZC_GLB_DBG_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
+#define GLB_TZC_GLB_DBG_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
+#define GLB_TZC_GLB_MBIST_LOCK GLB_TZC_GLB_MBIST_LOCK
+#define GLB_TZC_GLB_MBIST_LOCK_POS (30U)
+#define GLB_TZC_GLB_MBIST_LOCK_LEN (1U)
+#define GLB_TZC_GLB_MBIST_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
+#define GLB_TZC_GLB_MBIST_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
+#define GLB_TZC_GLB_CLK_LOCK GLB_TZC_GLB_CLK_LOCK
+#define GLB_TZC_GLB_CLK_LOCK_POS (31U)
+#define GLB_TZC_GLB_CLK_LOCK_LEN (1U)
+#define GLB_TZC_GLB_CLK_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
+#define GLB_TZC_GLB_CLK_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))
+
+/* 0xF04 : tzc_glb_ctrl_1 */
+
+#define GLB_TZC_GLB_CTRL_1_OFFSET (0xF04)
+#define GLB_TZC_GLB_SWRST_S20_LOCK GLB_TZC_GLB_SWRST_S20_LOCK
+#define GLB_TZC_GLB_SWRST_S20_LOCK_POS (0U)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S20_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S20_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S21_LOCK GLB_TZC_GLB_SWRST_S21_LOCK
+#define GLB_TZC_GLB_SWRST_S21_LOCK_POS (1U)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S21_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S21_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S22_LOCK GLB_TZC_GLB_SWRST_S22_LOCK
+#define GLB_TZC_GLB_SWRST_S22_LOCK_POS (2U)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S22_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S22_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S23_LOCK GLB_TZC_GLB_SWRST_S23_LOCK
+#define GLB_TZC_GLB_SWRST_S23_LOCK_POS (3U)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S23_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S23_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S24_LOCK GLB_TZC_GLB_SWRST_S24_LOCK
+#define GLB_TZC_GLB_SWRST_S24_LOCK_POS (4U)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S24_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S24_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S25_LOCK GLB_TZC_GLB_SWRST_S25_LOCK
+#define GLB_TZC_GLB_SWRST_S25_LOCK_POS (5U)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S25_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S25_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S26_LOCK GLB_TZC_GLB_SWRST_S26_LOCK
+#define GLB_TZC_GLB_SWRST_S26_LOCK_POS (6U)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S26_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S26_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S27_LOCK GLB_TZC_GLB_SWRST_S27_LOCK
+#define GLB_TZC_GLB_SWRST_S27_LOCK_POS (7U)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S27_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S27_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S28_LOCK GLB_TZC_GLB_SWRST_S28_LOCK
+#define GLB_TZC_GLB_SWRST_S28_LOCK_POS (8U)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S28_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S28_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S29_LOCK GLB_TZC_GLB_SWRST_S29_LOCK
+#define GLB_TZC_GLB_SWRST_S29_LOCK_POS (9U)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S29_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S29_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2A_LOCK GLB_TZC_GLB_SWRST_S2A_LOCK
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS (10U)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2A_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2B_LOCK GLB_TZC_GLB_SWRST_S2B_LOCK
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS (11U)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2B_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2C_LOCK GLB_TZC_GLB_SWRST_S2C_LOCK
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS (12U)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2C_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2D_LOCK GLB_TZC_GLB_SWRST_S2D_LOCK
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS (13U)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2D_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2E_LOCK GLB_TZC_GLB_SWRST_S2E_LOCK
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS (14U)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2E_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2F_LOCK GLB_TZC_GLB_SWRST_S2F_LOCK
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS (15U)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S2F_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S10_LOCK GLB_TZC_GLB_SWRST_S10_LOCK
+#define GLB_TZC_GLB_SWRST_S10_LOCK_POS (16U)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S10_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S10_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S11_LOCK GLB_TZC_GLB_SWRST_S11_LOCK
+#define GLB_TZC_GLB_SWRST_S11_LOCK_POS (17U)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S11_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S11_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S12_LOCK GLB_TZC_GLB_SWRST_S12_LOCK
+#define GLB_TZC_GLB_SWRST_S12_LOCK_POS (18U)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S12_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S12_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S13_LOCK GLB_TZC_GLB_SWRST_S13_LOCK
+#define GLB_TZC_GLB_SWRST_S13_LOCK_POS (19U)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S13_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S13_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S14_LOCK GLB_TZC_GLB_SWRST_S14_LOCK
+#define GLB_TZC_GLB_SWRST_S14_LOCK_POS (20U)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S14_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S14_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S15_LOCK GLB_TZC_GLB_SWRST_S15_LOCK
+#define GLB_TZC_GLB_SWRST_S15_LOCK_POS (21U)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S15_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S15_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S16_LOCK GLB_TZC_GLB_SWRST_S16_LOCK
+#define GLB_TZC_GLB_SWRST_S16_LOCK_POS (22U)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S16_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S16_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S17_LOCK GLB_TZC_GLB_SWRST_S17_LOCK
+#define GLB_TZC_GLB_SWRST_S17_LOCK_POS (23U)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S17_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S17_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S18_LOCK GLB_TZC_GLB_SWRST_S18_LOCK
+#define GLB_TZC_GLB_SWRST_S18_LOCK_POS (24U)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S18_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S18_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S19_LOCK GLB_TZC_GLB_SWRST_S19_LOCK
+#define GLB_TZC_GLB_SWRST_S19_LOCK_POS (25U)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S19_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S19_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1A_LOCK GLB_TZC_GLB_SWRST_S1A_LOCK
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS (26U)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1A_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1B_LOCK GLB_TZC_GLB_SWRST_S1B_LOCK
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS (27U)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1B_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1C_LOCK GLB_TZC_GLB_SWRST_S1C_LOCK
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS (28U)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1C_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1D_LOCK GLB_TZC_GLB_SWRST_S1D_LOCK
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS (29U)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1D_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1E_LOCK GLB_TZC_GLB_SWRST_S1E_LOCK
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS (30U)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1E_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1F_LOCK GLB_TZC_GLB_SWRST_S1F_LOCK
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS (31U)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN (1U)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_SWRST_S1F_LOCK_POS))
+
+/* 0xF08 : tzc_glb_ctrl_2 */
+
+#define GLB_TZC_GLB_CTRL_2_OFFSET (0xF08)
+#define GLB_TZC_GLB_GPIO_0_LOCK GLB_TZC_GLB_GPIO_0_LOCK
+#define GLB_TZC_GLB_GPIO_0_LOCK_POS (0U)
+#define GLB_TZC_GLB_GPIO_0_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_0_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_0_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_1_LOCK GLB_TZC_GLB_GPIO_1_LOCK
+#define GLB_TZC_GLB_GPIO_1_LOCK_POS (1U)
+#define GLB_TZC_GLB_GPIO_1_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_1_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_1_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_2_LOCK GLB_TZC_GLB_GPIO_2_LOCK
+#define GLB_TZC_GLB_GPIO_2_LOCK_POS (2U)
+#define GLB_TZC_GLB_GPIO_2_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_2_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_2_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_3_LOCK GLB_TZC_GLB_GPIO_3_LOCK
+#define GLB_TZC_GLB_GPIO_3_LOCK_POS (3U)
+#define GLB_TZC_GLB_GPIO_3_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_3_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_3_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_4_LOCK GLB_TZC_GLB_GPIO_4_LOCK
+#define GLB_TZC_GLB_GPIO_4_LOCK_POS (4U)
+#define GLB_TZC_GLB_GPIO_4_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_4_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_4_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_5_LOCK GLB_TZC_GLB_GPIO_5_LOCK
+#define GLB_TZC_GLB_GPIO_5_LOCK_POS (5U)
+#define GLB_TZC_GLB_GPIO_5_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_5_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_5_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_6_LOCK GLB_TZC_GLB_GPIO_6_LOCK
+#define GLB_TZC_GLB_GPIO_6_LOCK_POS (6U)
+#define GLB_TZC_GLB_GPIO_6_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_6_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_6_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_7_LOCK GLB_TZC_GLB_GPIO_7_LOCK
+#define GLB_TZC_GLB_GPIO_7_LOCK_POS (7U)
+#define GLB_TZC_GLB_GPIO_7_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_7_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_7_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_8_LOCK GLB_TZC_GLB_GPIO_8_LOCK
+#define GLB_TZC_GLB_GPIO_8_LOCK_POS (8U)
+#define GLB_TZC_GLB_GPIO_8_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_8_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_8_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_9_LOCK GLB_TZC_GLB_GPIO_9_LOCK
+#define GLB_TZC_GLB_GPIO_9_LOCK_POS (9U)
+#define GLB_TZC_GLB_GPIO_9_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_9_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_9_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_10_LOCK GLB_TZC_GLB_GPIO_10_LOCK
+#define GLB_TZC_GLB_GPIO_10_LOCK_POS (10U)
+#define GLB_TZC_GLB_GPIO_10_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_10_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_10_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_11_LOCK GLB_TZC_GLB_GPIO_11_LOCK
+#define GLB_TZC_GLB_GPIO_11_LOCK_POS (11U)
+#define GLB_TZC_GLB_GPIO_11_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_11_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_11_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_12_LOCK GLB_TZC_GLB_GPIO_12_LOCK
+#define GLB_TZC_GLB_GPIO_12_LOCK_POS (12U)
+#define GLB_TZC_GLB_GPIO_12_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_12_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_12_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_13_LOCK GLB_TZC_GLB_GPIO_13_LOCK
+#define GLB_TZC_GLB_GPIO_13_LOCK_POS (13U)
+#define GLB_TZC_GLB_GPIO_13_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_13_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_13_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_14_LOCK GLB_TZC_GLB_GPIO_14_LOCK
+#define GLB_TZC_GLB_GPIO_14_LOCK_POS (14U)
+#define GLB_TZC_GLB_GPIO_14_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_14_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_14_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_15_LOCK GLB_TZC_GLB_GPIO_15_LOCK
+#define GLB_TZC_GLB_GPIO_15_LOCK_POS (15U)
+#define GLB_TZC_GLB_GPIO_15_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_15_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_15_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_16_LOCK GLB_TZC_GLB_GPIO_16_LOCK
+#define GLB_TZC_GLB_GPIO_16_LOCK_POS (16U)
+#define GLB_TZC_GLB_GPIO_16_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_16_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_16_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_17_LOCK GLB_TZC_GLB_GPIO_17_LOCK
+#define GLB_TZC_GLB_GPIO_17_LOCK_POS (17U)
+#define GLB_TZC_GLB_GPIO_17_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_17_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_17_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_18_LOCK GLB_TZC_GLB_GPIO_18_LOCK
+#define GLB_TZC_GLB_GPIO_18_LOCK_POS (18U)
+#define GLB_TZC_GLB_GPIO_18_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_18_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_18_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_19_LOCK GLB_TZC_GLB_GPIO_19_LOCK
+#define GLB_TZC_GLB_GPIO_19_LOCK_POS (19U)
+#define GLB_TZC_GLB_GPIO_19_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_19_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_19_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_20_LOCK GLB_TZC_GLB_GPIO_20_LOCK
+#define GLB_TZC_GLB_GPIO_20_LOCK_POS (20U)
+#define GLB_TZC_GLB_GPIO_20_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_20_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_20_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_21_LOCK GLB_TZC_GLB_GPIO_21_LOCK
+#define GLB_TZC_GLB_GPIO_21_LOCK_POS (21U)
+#define GLB_TZC_GLB_GPIO_21_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_21_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_21_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_22_LOCK GLB_TZC_GLB_GPIO_22_LOCK
+#define GLB_TZC_GLB_GPIO_22_LOCK_POS (22U)
+#define GLB_TZC_GLB_GPIO_22_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_22_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_22_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_23_LOCK GLB_TZC_GLB_GPIO_23_LOCK
+#define GLB_TZC_GLB_GPIO_23_LOCK_POS (23U)
+#define GLB_TZC_GLB_GPIO_23_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_23_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_23_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_24_LOCK GLB_TZC_GLB_GPIO_24_LOCK
+#define GLB_TZC_GLB_GPIO_24_LOCK_POS (24U)
+#define GLB_TZC_GLB_GPIO_24_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_24_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_24_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_25_LOCK GLB_TZC_GLB_GPIO_25_LOCK
+#define GLB_TZC_GLB_GPIO_25_LOCK_POS (25U)
+#define GLB_TZC_GLB_GPIO_25_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_25_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_25_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_26_LOCK GLB_TZC_GLB_GPIO_26_LOCK
+#define GLB_TZC_GLB_GPIO_26_LOCK_POS (26U)
+#define GLB_TZC_GLB_GPIO_26_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_26_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_26_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_27_LOCK GLB_TZC_GLB_GPIO_27_LOCK
+#define GLB_TZC_GLB_GPIO_27_LOCK_POS (27U)
+#define GLB_TZC_GLB_GPIO_27_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_27_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_27_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_28_LOCK GLB_TZC_GLB_GPIO_28_LOCK
+#define GLB_TZC_GLB_GPIO_28_LOCK_POS (28U)
+#define GLB_TZC_GLB_GPIO_28_LOCK_LEN (1U)
+#define GLB_TZC_GLB_GPIO_28_LOCK_MSK \
+ (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK \
+ (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) \
+ << GLB_TZC_GLB_GPIO_28_LOCK_POS))
+
+/* 0xF0C : tzc_glb_ctrl_3 */
+
+#define GLB_TZC_GLB_CTRL_3_OFFSET (0xF0C)
+
+/* 0x0 : GPIO_CFGCTL */
+
+#define GLB_GPIO_CFGCTL_OFFSET (0x0)
+#define GLB_REG_GPIO_0_IE GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS (0U)
+#define GLB_REG_GPIO_0_IE_LEN (1U)
+#define GLB_REG_GPIO_0_IE_MSK \
+ (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS (1U)
+#define GLB_REG_GPIO_0_SMT_LEN (1U)
+#define GLB_REG_GPIO_0_SMT_MSK \
+ (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS (2U)
+#define GLB_REG_GPIO_0_DRV_LEN (2U)
+#define GLB_REG_GPIO_0_DRV_MSK \
+ (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS (4U)
+#define GLB_REG_GPIO_0_PU_LEN (1U)
+#define GLB_REG_GPIO_0_PU_MSK \
+ (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS (5U)
+#define GLB_REG_GPIO_0_PD_LEN (1U)
+#define GLB_REG_GPIO_0_PD_MSK \
+ (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_0_FUNC_SEL GLB_REAL_GPIO_0_FUNC_SEL
+#define GLB_REAL_GPIO_0_FUNC_SEL_POS (12U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_MSK \
+ (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) \
+ << GLB_REAL_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_IE GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS (16U)
+#define GLB_REG_GPIO_1_IE_LEN (1U)
+#define GLB_REG_GPIO_1_IE_MSK \
+ (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS (17U)
+#define GLB_REG_GPIO_1_SMT_LEN (1U)
+#define GLB_REG_GPIO_1_SMT_MSK \
+ (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS (18U)
+#define GLB_REG_GPIO_1_DRV_LEN (2U)
+#define GLB_REG_GPIO_1_DRV_MSK \
+ (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS (20U)
+#define GLB_REG_GPIO_1_PU_LEN (1U)
+#define GLB_REG_GPIO_1_PU_MSK \
+ (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS (21U)
+#define GLB_REG_GPIO_1_PD_LEN (1U)
+#define GLB_REG_GPIO_1_PD_MSK \
+ (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS (24U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN (4U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK \
+ (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) \
+ << GLB_REG_GPIO_1_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_1_FUNC_SEL GLB_REAL_GPIO_1_FUNC_SEL
+#define GLB_REAL_GPIO_1_FUNC_SEL_POS (28U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_LEN (4U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_MSK \
+ (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK \
+ (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) \
+ << GLB_REAL_GPIO_1_FUNC_SEL_POS))
+
+#define GLB_GPIO_OFFSET 0x100
+#define GLB_GPIO_INPUT_OFFSET 0x180
+#define GLB_GPIO_OUTPUT_OFFSET 0x188
+#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* GLB root clock type definition */
+
+enum glb_root_clk_e
+{
+ GLB_ROOT_CLK_RC32M, /* root clock select RC32M */
+ GLB_ROOT_CLK_XTAL, /* root clock select XTAL */
+ GLB_ROOT_CLK_PLL /* root clock select PLL others */
+};
+
+/* GLB system clock type definition */
+
+enum glb_sys_clk_e
+{
+ GLB_SYS_CLK_RC32M, /* use RC32M as system clock frequency */
+ GLB_SYS_CLK_XTAL, /* use XTAL as system clock */
+ GLB_SYS_CLK_PLL48M, /* use PLL output 48M as system clock */
+ GLB_SYS_CLK_PLL120M, /* use PLL output 120M as system clock */
+ GLB_SYS_CLK_PLL160M, /* use PLL output 160M as system clock */
+ GLB_SYS_CLK_PLL192M /* use PLL output 192M as system clock */
+};
+
+/* GLB DMA clock ID type definition */
+
+enum glb_dma_clk_id_e
+{
+ GLB_DMA_CLK_DMA0_CH0, /* DMA clock ID:channel 0 */
+ GLB_DMA_CLK_DMA0_CH1, /* DMA clock ID:channel 1 */
+ GLB_DMA_CLK_DMA0_CH2, /* DMA clock ID:channel 2 */
+ GLB_DMA_CLK_DMA0_CH3 /* DMA clock ID:channel 3 */
+};
+
+/* GLB clock source type definition */
+
+enum glb_ir_clk_src_e
+{
+ GLB_IR_CLK_SRC_XCLK /* IR clock source select XCLK */
+};
+
+/* GLB flash clock type definition */
+
+enum glb_sflash_clk_e
+{
+ GLB_SFLASH_CLK_120M, /* Select 120M as flash clock */
+ GLB_SFLASH_CLK_XTAL, /* Select XTAL as flash clock */
+ GLB_SFLASH_CLK_48M, /* Select 48M as flash clock */
+ GLB_SFLASH_CLK_80M, /* Select 80M as flash clock */
+ GLB_SFLASH_CLK_BCLK, /* Select BCLK as flash clock */
+ GLB_SFLASH_CLK_96M /* Select 96M as flash clock */
+};
+
+/* GLB SPI pad action type definition */
+
+enum glb_spi_pad_act_as_e
+{
+ GLB_SPI_PAD_ACT_AS_SLAVE, /* SPI pad act as slave */
+ GLB_SPI_PAD_ACT_AS_MASTER /* SPI pad act as master */
+};
+
+/* GLB PKA clock type definition */
+
+enum glb_pka_clk_type_e
+{
+ GLB_PKA_CLK_HCLK, /* Select HCLK as PKA clock */
+ GLB_PKA_CLK_PLL120M /* Select PLL 120M as PKA clock */
+};
+
+/* BMX arb mode type definition */
+
+enum bmx_arb_type_e
+{
+ BMX_ARB_FIX, /* 0->fix */
+ BMX_ARB_ROUND_ROBIN, /* 2->round-robin */
+ BMX_ARB_RANDOM /* 3->random */
+};
+
+/* BMX configuration structure type definition */
+
+struct bmx_cfg_type_s
+{
+ /* Bus timeout enable: detect slave no reaponse in 1024 cycles */
+
+ uint8_t timeout_en;
+ void * err_en; /* Bus error response enable */
+ enum bmx_arb_type_e arb_mod; /* 0->fix, 2->round-robin, 3->random */
+};
+
+/* BMX bus err type definition */
+
+enum bmx_bus_err_type_e
+{
+ BMX_BUS_ERR_TRUSTZONE_DECODE, /* Bus trustzone decode error */
+ BMX_BUS_ERR_ADDR_DECODE /* Bus addr decode error */
+};
+
+/* BMX bus err interrupt type definition */
+
+enum bmx_err_int_type_e
+{
+ BMX_ERR_INT_ERR, /* BMX bus err interrupt */
+ BMX_ERR_INT_ALL /* BMX bus err interrupt max num */
+};
+
+/* BMX time out interrupt type definition */
+
+enum bmx_to_int_type_e
+{
+ BMX_TO_INT_TIMEOUT, /* BMX timeout interrupt */
+ BMX_TO_INT_ALL /* BMX timeout interrupt max num */
+};
+
+/* GLB EM type definition */
+
+enum glb_em_type_e
+{
+ GLB_EM_0KB = 0x0, /* 0x0 --> 0KB */
+ GLB_EM_8KB = 0x3, /* 0x3 --> 8KB */
+ GLB_EM_16KB = 0xf /* 0xF --> 16KB */
+};
+
+/* GLB RTC clock type definition */
+
+enum glb_mtimer_clk_e
+{
+ GLB_MTIMER_CLK_BCLK, /* BUS clock */
+ GLB_MTIMER_CLK_32K /* 32KHz */
+};
+
+/* GLB ADC clock type definition */
+
+enum glb_adc_clk_e
+{
+ GLB_ADC_CLK_96M, /* use 96M as ADC clock */
+ GLB_ADC_CLK_XCLK /* use XCLK as ADC clock */
+};
+
+/* GLB DAC clock type definition */
+
+enum glb_dac_clk_e
+{
+ GLB_DAC_CLK_32M, /* use 32M as DAC clock */
+ GLB_DAC_CLK_XCLK /* use XCLK as DAC clock */
+};
+
+/* GLB DIG clock source select type definition */
+
+enum glb_dig_clk_e
+{
+ GLB_DIG_CLK_PLL_32M, /* select PLL 32M as DIG clock source */
+ GLB_DIG_CLK_XCLK /* select XCLK as DIG clock source */
+};
+
+/* GLB 512K clock out select type definition */
+
+enum glb_512k_clk_out_e
+{
+ GLB_512K_CLK_OUT_512K, /* select 512K clock out */
+ GLB_512K_CLK_OUT_256K, /* select 256K clock out */
+ GLB_512K_CLK_OUT_128K /* select 128K clock out */
+};
+
+/* GLB BT bandwidth type definition */
+
+enum glb_bt_bandwidth_e
+{
+ GLB_BT_BANDWIDTH_1M, /* BT bandwidth 1MHz */
+ GLB_BT_BANDWIDTH_2M /* BT bandwidth 2MHz */
+};
+
+/* GLB UART signal type definition */
+
+enum glb_uart_sig_e
+{
+ GLB_UART_SIG_0, /* UART signal 0 */
+ GLB_UART_SIG_1, /* UART signal 1 */
+ GLB_UART_SIG_2, /* UART signal 2 */
+ GLB_UART_SIG_3, /* UART signal 3 */
+ GLB_UART_SIG_4, /* UART signal 4 */
+ GLB_UART_SIG_5, /* UART signal 5 */
+ GLB_UART_SIG_6, /* UART signal 6 */
+ GLB_UART_SIG_7 /* UART signal 7 */
+};
+
+/* GLB UART signal function type definition */
+
+enum glb_uart_sig_fun_e
+{
+ GLB_UART_SIG_FUN_UART0_RTS, /* UART funtion: UART 0 RTS */
+ GLB_UART_SIG_FUN_UART0_CTS, /* UART funtion: UART 0 CTS */
+ GLB_UART_SIG_FUN_UART0_TXD, /* UART funtion: UART 0 TXD */
+ GLB_UART_SIG_FUN_UART0_RXD, /* UART funtion: UART 0 RXD */
+ GLB_UART_SIG_FUN_UART1_RTS, /* UART funtion: UART 1 RTS */
+ GLB_UART_SIG_FUN_UART1_CTS, /* UART funtion: UART 1 CTS */
+ GLB_UART_SIG_FUN_UART1_TXD, /* UART funtion: UART 1 TXD */
+ GLB_UART_SIG_FUN_UART1_RXD /* UART funtion: UART 1 RXD */
+};
+
+/* GLB GPIO real mode type definition */
+
+enum glb_gpio_real_mode_e
+{
+ /* GPIO real function is reg_gpio_x_func_sel */
+
+ GLB_GPIO_REAL_MODE_REG = 0x0,
+ GLB_GPIO_REAL_MODE_SDIO = 0x1, /* GPIO real function is SDIO */
+ GLB_GPIO_REAL_MODE_RF = 0xc, /* GPIO real function is RF */
+ GLB_GPIO_REAL_MODE_JTAG = 0xe, /* GPIO real function is JTAG */
+ GLB_GPIO_REAL_MODE_CCI = 0xf /* GPIO real function is CCI */
+};
+
+/* GLB GPIO interrupt trigger mode type definition */
+
+enum glb_gpio_int_trig_e
+{
+ GLB_GPIO_INT_TRIG_NEG_PULSE, /* GPIO negedge pulse trigger interrupt */
+ GLB_GPIO_INT_TRIG_POS_PULSE, /* GPIO posedge pulse trigger interrupt */
+
+ /* GPIO negedge level trigger interrupt (32k 3T) */
+
+ GLB_GPIO_INT_TRIG_NEG_LEVEL,
+
+ /* GPIO posedge level trigger interrupt (32k 3T) */
+
+ GLB_GPIO_INT_TRIG_POS_LEVEL
+};
+
+/* GLB GPIO interrupt control mode type definition */
+
+enum glb_gpio_int_control_e
+{
+ GLB_GPIO_INT_CONTROL_SYNC, /* GPIO interrupt sync mode */
+ GLB_GPIO_INT_CONTROL_ASYNC /* GPIO interrupt async mode */
+};
+
+/* PLL XTAL type definition */
+
+enum glb_pll_xtal_e
+{
+ GLB_PLL_XTAL_NONE, /* XTAL is none */
+ GLB_PLL_XTAL_24M, /* XTAL is 24M */
+ GLB_PLL_XTAL_32M, /* XTAL is 32M */
+ GLB_PLL_XTAL_38P4M, /* XTAL is 38.4M */
+ GLB_PLL_XTAL_40M, /* XTAL is 40M */
+ GLB_PLL_XTAL_26M, /* XTAL is 26M */
+ GLB_PLL_XTAL_RC32M /* XTAL is RC32M */
+};
+
+/* PLL output clock type definition */
+
+enum glb_pll_clk_e
+{
+ GLB_PLL_CLK_480M, /* PLL output clock:480M */
+ GLB_PLL_CLK_240M, /* PLL output clock:240M */
+ GLB_PLL_CLK_192M, /* PLL output clock:192M */
+ GLB_PLL_CLK_160M, /* PLL output clock:160M */
+ GLB_PLL_CLK_120M, /* PLL output clock:120M */
+ GLB_PLL_CLK_96M, /* PLL output clock:96M */
+ GLB_PLL_CLK_80M, /* PLL output clock:80M */
+ GLB_PLL_CLK_48M, /* PLL output clock:48M */
+ GLB_PLL_CLK_32M /* PLL output clock:32M */
+};
+
+struct glb_reg_s
+{
+ /* 0x0 : clk_cfg0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_pll_en : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_fclk_en : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_hclk_en : 1; /* [ 2], r/w, 0x1 */
+ uint32_t reg_bclk_en : 1; /* [ 3], r/w, 0x1 */
+ uint32_t reg_pll_sel : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t hbn_root_clk_sel : 2; /* [ 7: 6], r, 0x0 */
+ uint32_t reg_hclk_div : 8; /* [15: 8], r/w, 0x0 */
+ uint32_t reg_bclk_div : 8; /* [23:16], r/w, 0x0 */
+ uint32_t fclk_sw_state : 3; /* [26:24], r, 0x0 */
+ uint32_t chip_rdy : 1; /* [ 27], r, 0x0 */
+ uint32_t glb_id : 4; /* [31:28], r, 0x6 */
+ } bf;
+ uint32_t word;
+ } clk_cfg0;
+
+ /* 0x4 : clk_cfg1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t wifi_mac_core_div : 4; /* [ 3: 0], r/w, 0x1 */
+ uint32_t wifi_mac_wt_div : 4; /* [ 7: 4], r/w, 0x0 */
+ uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */
+ uint32_t ble_clk_sel : 6; /* [21:16], r/w, 0x10 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t ble_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } clk_cfg1;
+
+ /* 0x8 : clk_cfg2 */
+
+ union
+ {
+ struct
+ {
+ uint32_t uart_clk_div : 3; /* [ 2: 0], r/w, 0x7 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t uart_clk_en : 1; /* [ 4], r/w, 0x1 */
+ uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */
+ uint32_t hbn_uart_clk_sel : 1; /* [ 7], r, 0x0 */
+ uint32_t sf_clk_div : 3; /* [10: 8], r/w, 0x3 */
+ uint32_t sf_clk_en : 1; /* [ 11], r/w, 0x1 */
+ uint32_t sf_clk_sel : 2; /* [13:12], r/w, 0x2 */
+ uint32_t sf_clk_sel2 : 2; /* [15:14], r/w, 0x0 */
+ uint32_t ir_clk_div : 6; /* [21:16], r/w, 0xf */
+ uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */
+ uint32_t ir_clk_en : 1; /* [ 23], r/w, 0x1 */
+ uint32_t dma_clk_en : 8; /* [31:24], r/w, 0xff */
+ } bf;
+ uint32_t word;
+ } clk_cfg2;
+
+ /* 0xC : clk_cfg3 */
+
+ union
+ {
+ struct
+ {
+ uint32_t spi_clk_div : 5; /* [ 4: 0], r/w, 0x3 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t spi_clk_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
+ uint32_t i2c_clk_div : 8; /* [23:16], r/w, 0xff */
+ uint32_t i2c_clk_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } clk_cfg3;
+
+ /* 0x10 : swrst_cfg0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t swrst_s00 : 1; /* [ 0], r/w, 0x0 */
+ uint32_t swrst_s01 : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
+ uint32_t swrst_s20 : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t swrst_s30 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } swrst_cfg0;
+
+ /* 0x14 : swrst_cfg1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t swrst_s10 : 1; /* [ 0], r/w, 0x0 */
+ uint32_t swrst_s11 : 1; /* [ 1], r/w, 0x0 */
+ uint32_t swrst_s12 : 1; /* [ 2], r/w, 0x0 */
+ uint32_t swrst_s13 : 1; /* [ 3], r/w, 0x0 */
+ uint32_t swrst_s14 : 1; /* [ 4], r/w, 0x0 */
+ uint32_t swrst_s15 : 1; /* [ 5], r/w, 0x0 */
+ uint32_t swrst_s16 : 1; /* [ 6], r/w, 0x0 */
+ uint32_t swrst_s17 : 1; /* [ 7], r/w, 0x0 */
+ uint32_t swrst_s18 : 1; /* [ 8], r/w, 0x0 */
+ uint32_t swrst_s19 : 1; /* [ 9], r/w, 0x0 */
+ uint32_t swrst_s1a : 1; /* [ 10], r/w, 0x0 */
+ uint32_t swrst_s1b : 1; /* [ 11], r/w, 0x0 */
+ uint32_t swrst_s1c : 1; /* [ 12], r/w, 0x0 */
+ uint32_t swrst_s1d : 1; /* [ 13], r/w, 0x0 */
+ uint32_t swrst_s1e : 1; /* [ 14], r/w, 0x0 */
+ uint32_t swrst_s1f : 1; /* [ 15], r/w, 0x0 */
+ uint32_t swrst_s1a0 : 1; /* [ 16], r/w, 0x0 */
+ uint32_t swrst_s1a1 : 1; /* [ 17], r/w, 0x0 */
+ uint32_t swrst_s1a2 : 1; /* [ 18], r/w, 0x0 */
+ uint32_t swrst_s1a3 : 1; /* [ 19], r/w, 0x0 */
+ uint32_t swrst_s1a4 : 1; /* [ 20], r/w, 0x0 */
+ uint32_t swrst_s1a5 : 1; /* [ 21], r/w, 0x0 */
+ uint32_t swrst_s1a6 : 1; /* [ 22], r/w, 0x0 */
+ uint32_t swrst_s1a7 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } swrst_cfg1;
+
+ /* 0x18 : swrst_cfg2 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_ctrl_pwron_rst : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_ctrl_cpu_reset : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_ctrl_sys_reset : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t reg_ctrl_reset_dummy : 4; /* [ 7: 4], r/w, 0x0 */
+ uint32_t reserved_8_23 : 16; /* [23: 8], rsvd, 0x0 */
+ uint32_t pka_clk_sel : 1; /* [ 24], r/w, 0x0 */
+ uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } swrst_cfg2;
+
+ /* 0x1C : swrst_cfg3 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } swrst_cfg3;
+
+ /* 0x20 : cgen_cfg0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t cgen_m : 8; /* [ 7: 0], r/w, 0xff */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } cgen_cfg0;
+
+ /* 0x24 : cgen_cfg1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t cgen_s1 : 16; /* [15: 0], r/w, 0xffff */
+ uint32_t cgen_s1a : 8; /* [23:16], r/w, 0xff */
+ uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } cgen_cfg1;
+
+ /* 0x28 : cgen_cfg2 */
+
+ union
+ {
+ struct
+ {
+ uint32_t cgen_s2 : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t cgen_s3 : 1; /* [ 4], r/w, 0x1 */
+ uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } cgen_cfg2;
+
+ /* 0x2C : cgen_cfg3 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } cgen_cfg3;
+
+ /* 0x30 : MBIST_CTL */
+
+ union
+ {
+ struct
+ {
+ uint32_t irom_mbist_mode : 1; /* [ 0], r/w, 0x0 */
+ uint32_t hsram_mbist_mode : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tag_mbist_mode : 1; /* [ 2], r/w, 0x0 */
+ uint32_t ocram_mbist_mode : 1; /* [ 3], r/w, 0x0 */
+ uint32_t wifi_mbist_mode : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reserved_5_30 : 26; /* [30: 5], rsvd, 0x0 */
+ uint32_t reg_mbist_rst_n : 1; /* [ 31], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } MBIST_CTL;
+
+ /* 0x34 : MBIST_STAT */
+
+ union
+ {
+ struct
+ {
+ uint32_t irom_mbist_done : 1; /* [ 0], r, 0x0 */
+ uint32_t hsram_mbist_done : 1; /* [ 1], r, 0x0 */
+ uint32_t tag_mbist_done : 1; /* [ 2], r, 0x0 */
+ uint32_t ocram_mbist_done : 1; /* [ 3], r, 0x0 */
+ uint32_t wifi_mbist_done : 1; /* [ 4], r, 0x0 */
+ uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */
+ uint32_t irom_mbist_fail : 1; /* [ 16], r, 0x0 */
+ uint32_t hsram_mbist_fail : 1; /* [ 17], r, 0x0 */
+ uint32_t tag_mbist_fail : 1; /* [ 18], r, 0x0 */
+ uint32_t ocram_mbist_fail : 1; /* [ 19], r, 0x0 */
+ uint32_t wifi_mbist_fail : 1; /* [ 20], r, 0x0 */
+ uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } MBIST_STAT;
+
+ /* 0x38 reserved */
+
+ uint8_t reserved_0x38[24];
+
+ /* 0x50 : bmx_cfg1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t bmx_timeout_en : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t bmx_arb_mode : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t bmx_err_en : 1; /* [ 8], r/w, 0x0 */
+ uint32_t bmx_busy_option_dis : 1; /* [ 9], r/w, 0x0 */
+ uint32_t bmx_gating_dis : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t hsel_option : 4; /* [15:12], r/w, 0x0 */
+ uint32_t pds_apb_cfg : 8; /* [23:16], r/w, 0x0 */
+ uint32_t hbn_apb_cfg : 8; /* [31:24], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } bmx_cfg1;
+
+ /* 0x54 : bmx_cfg2 */
+
+ union
+ {
+ struct
+ {
+ uint32_t bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
+ uint32_t bmx_err_dec : 1; /* [ 4], r, 0x0 */
+ uint32_t bmx_err_tz : 1; /* [ 5], r, 0x0 */
+ uint32_t reserved_6_27 : 22; /* [27: 6], rsvd, 0x0 */
+ uint32_t bmx_dbg_sel : 4; /* [31:28], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } bmx_cfg2;
+
+ /* 0x58 : bmx_err_addr */
+
+ union
+ {
+ struct
+ {
+ uint32_t bmx_err_addr : 32; /* [31: 0], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } bmx_err_addr;
+
+ /* 0x5C : bmx_dbg_out */
+
+ union
+ {
+ struct
+ {
+ uint32_t bmx_dbg_out : 32; /* [31: 0], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } bmx_dbg_out;
+
+ /* 0x60 : rsv0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } rsv0;
+
+ /* 0x64 : rsv1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } rsv1;
+
+ /* 0x68 : rsv2 */
+
+ union
+ {
+ struct
+ {
+ uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } rsv2;
+
+ /* 0x6C : rsv3 */
+
+ union
+ {
+ struct
+ {
+ uint32_t rsvd_31_0 : 32; /* [31: 0], rsvd, 0xffffffffL */
+ } bf;
+ uint32_t word;
+ } rsv3;
+
+ /* 0x70 : sram_ret */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_sram_ret : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } sram_ret;
+
+ /* 0x74 : sram_slp */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_sram_slp : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } sram_slp;
+
+ /* 0x78 : sram_parm */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_sram_parm : 32; /* [31: 0], r/w, 0xc0c0c0c */
+ } bf;
+ uint32_t word;
+ } sram_parm;
+
+ /* 0x7C : seam_misc */
+
+ union
+ {
+ struct
+ {
+ uint32_t em_sel : 4; /* [ 3: 0], r/w, 0x3 */
+ uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } seam_misc;
+
+ /* 0x80 : glb_parm */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_bd_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_ext_rst_smt : 1; /* [ 1], r/w, 0x0 */
+ uint32_t jtag_swap_set : 6; /* [ 7: 2], r/w, 0x0 */
+ uint32_t swap_sflash_io_3_io_0 : 1; /* [ 8], r/w, 0x1 */
+ uint32_t sel_embedded_sflash : 1; /* [ 9], r/w, 0x1 */
+ uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */
+ uint32_t reg_spi_0_master_mode : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg_spi_0_swap : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */
+ uint32_t reg_cci_use_jtag_pin : 1; /* [ 15], r/w, 0x1 */
+ uint32_t reg_cci_use_sdio_pin : 1; /* [ 16], r/w, 0x1 */
+ uint32_t p1_adc_test_with_cci : 1; /* [ 17], r/w, 0x0 */
+ uint32_t p2_dac_test_with_cci : 1; /* [ 18], r/w, 0x0 */
+ uint32_t p3_cci_use_io_2_5 : 1; /* [ 19], r/w, 0x0 */
+ uint32_t p4_adc_test_with_jtag : 1; /* [ 20], r/w, 0x0 */
+ uint32_t p5_dac_test_with_jtag : 1; /* [ 21], r/w, 0x0 */
+ uint32_t p6_sdio_use_io_0_5 : 1; /* [ 22], r/w, 0x0 */
+ uint32_t p7_jtag_use_io_2_5 : 1; /* [ 23], r/w, 0x0 */
+ uint32_t uart_swap_set : 3; /* [26:24], r/w, 0x0 */
+ uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } glb_parm;
+
+ /* 0x84 reserved */
+
+ uint8_t reserved_0x84[12];
+
+ /* 0x90 : CPU_CLK_CFG */
+
+ union
+ {
+ struct
+ {
+ uint32_t cpu_rtc_div : 17; /* [16: 0], r/w, 0x10 */
+ uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */
+ uint32_t cpu_rtc_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t cpu_rtc_sel : 1; /* [ 19], r/w, 0x1 */
+ uint32_t debug_ndreset_gate : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } CPU_CLK_CFG;
+
+ /* 0x94 reserved */
+
+ uint8_t reserved_0x94[16];
+
+ /* 0xA4 : GPADC_32M_SRC_CTRL */
+
+ union
+ {
+ struct
+ {
+ uint32_t gpadc_32m_clk_div : 6; /* [ 5: 0], r/w, 0x2 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t gpadc_32m_clk_sel : 1; /* [ 7], r/w, 0x0 */
+ uint32_t gpadc_32m_div_en : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPADC_32M_SRC_CTRL;
+
+ /* 0xA8 : DIG32K_WAKEUP_CTRL */
+
+ union
+ {
+ struct
+ {
+ uint32_t dig_32k_div : 11; /* [10: 0], r/w, 0x3e8 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t dig_32k_en : 1; /* [ 12], r/w, 0x1 */
+ uint32_t dig_32k_comp : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t dig_512k_div : 7; /* [22:16], r/w, 0x3e */
+ uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
+ uint32_t dig_512k_en : 1; /* [ 24], r/w, 0x1 */
+ uint32_t dig_512k_comp : 1; /* [ 25], r/w, 0x1 */
+ uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
+ uint32_t dig_clk_src_sel : 1; /* [ 28], r/w, 0x0 */
+ uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */
+ uint32_t reg_en_platform_wakeup : 1; /* [ 31], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } DIG32K_WAKEUP_CTRL;
+
+ /* 0xAC : WIFI_BT_COEX_CTRL */
+
+ union
+ {
+ struct
+ {
+ uint32_t coex_bt_channel : 7; /* [ 6: 0], r/w, 0x0 */
+ uint32_t coex_bt_pti : 4; /* [10: 7], r/w, 0x0 */
+ uint32_t coex_bt_bw : 1; /* [ 11], r/w, 0x0 */
+ uint32_t en_gpio_bt_coex : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } WIFI_BT_COEX_CTRL;
+
+ /* 0xb0 reserved */
+
+ uint8_t reserved_0xb0[16];
+
+ /* 0xC0 : UART_SIG_SEL_0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t uart_sig_0_sel : 4; /* [ 3: 0], r/w, 0x0 */
+ uint32_t uart_sig_1_sel : 4; /* [ 7: 4], r/w, 0x1 */
+ uint32_t uart_sig_2_sel : 4; /* [11: 8], r/w, 0x2 */
+ uint32_t uart_sig_3_sel : 4; /* [15:12], r/w, 0x3 */
+ uint32_t uart_sig_4_sel : 4; /* [19:16], r/w, 0x4 */
+ uint32_t uart_sig_5_sel : 4; /* [23:20], r/w, 0x5 */
+ uint32_t uart_sig_6_sel : 4; /* [27:24], r/w, 0x6 */
+ uint32_t uart_sig_7_sel : 4; /* [31:28], r/w, 0x7 */
+ } bf;
+ uint32_t word;
+ } UART_SIG_SEL_0;
+
+ /* 0xc4 reserved */
+
+ uint8_t reserved_0xc4[12];
+
+ /* 0xD0 : DBG_SEL_LL */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_dbg_ll_ctrl : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } DBG_SEL_LL;
+
+ /* 0xD4 : DBG_SEL_LH */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_dbg_lh_ctrl : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } DBG_SEL_LH;
+
+ /* 0xD8 : DBG_SEL_HL */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_dbg_hl_ctrl : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } DBG_SEL_HL;
+
+ /* 0xDC : DBG_SEL_HH */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_dbg_hh_ctrl : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } DBG_SEL_HH;
+
+ /* 0xE0 : debug */
+
+ union
+ {
+ struct
+ {
+ uint32_t debug_oe : 1; /* [ 0], r/w, 0x0 */
+ uint32_t debug_i : 31; /* [31: 1], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } debug;
+
+ /* 0xe4 reserved */
+
+ uint8_t reserved_0xe4[28];
+
+ /* 0x100 : GPIO_CFGCTL0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_0_func_sel : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t real_gpio_0_func_sel : 4; /* [15:12], r, 0x1 */
+ uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_1_func_sel : 4; /* [27:24], r/w, 0x1 */
+ uint32_t real_gpio_1_func_sel : 4; /* [31:28], r, 0x1 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL0;
+
+ /* 0x104 : GPIO_CFGCTL1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_2_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_2_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_2_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_2_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_2_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_2_func_sel : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t real_gpio_2_func_sel : 4; /* [15:12], r, 0x1 */
+ uint32_t reg_gpio_3_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_3_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_3_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_3_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_3_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_3_func_sel : 4; /* [27:24], r/w, 0x1 */
+ uint32_t real_gpio_3_func_sel : 4; /* [31:28], r, 0x1 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL1;
+
+ /* 0x108 : GPIO_CFGCTL2 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_4_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_4_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_4_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_4_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_4_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_4_func_sel : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t real_gpio_4_func_sel : 4; /* [15:12], r, 0x1 */
+ uint32_t reg_gpio_5_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_5_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_5_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_5_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_5_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_5_func_sel : 4; /* [27:24], r/w, 0x1 */
+ uint32_t real_gpio_5_func_sel : 4; /* [31:28], r, 0x1 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL2;
+
+ /* 0x10C : GPIO_CFGCTL3 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_6_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_6_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_6_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_6_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_6_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_6_func_sel : 4; /* [11: 8], r/w, 0xb */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t reg_gpio_7_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_7_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_7_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_7_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_7_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_7_func_sel : 4; /* [27:24], r/w, 0xb */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL3;
+
+ /* 0x110 : GPIO_CFGCTL4 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_8_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_8_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_8_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_8_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_8_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_8_func_sel : 4; /* [11: 8], r/w, 0xb */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t reg_gpio_9_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_9_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_9_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_9_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_9_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_9_func_sel : 4; /* [27:24], r/w, 0xb */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL4;
+
+ /* 0x114 : GPIO_CFGCTL5 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_10_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_10_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_10_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_10_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_10_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_10_func_sel : 4; /* [11: 8], r/w, 0xb */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t reg_gpio_11_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_11_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_11_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_11_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_11_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_11_func_sel : 4; /* [27:24], r/w, 0xe */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL5;
+
+ /* 0x118 : GPIO_CFGCTL6 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_12_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_12_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_12_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_12_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_12_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_12_func_sel : 4; /* [11: 8], r/w, 0xe */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t reg_gpio_13_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_13_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_13_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_13_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_13_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_13_func_sel : 4; /* [27:24], r/w, 0xb */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL6;
+
+ /* 0x11C : GPIO_CFGCTL7 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_14_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_14_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_14_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_14_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_14_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_14_func_sel : 4; /* [11: 8], r/w, 0xe */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t reg_gpio_15_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_15_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_15_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_15_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_15_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_15_func_sel : 4; /* [27:24], r/w, 0xb */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL7;
+
+ /* 0x120 : GPIO_CFGCTL8 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_16_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_16_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_16_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_16_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_16_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_16_func_sel : 4; /* [11: 8], r/w, 0xb */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t reg_gpio_17_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_17_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_17_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_17_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_17_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_17_func_sel : 4; /* [27:24], r/w, 0xe */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL8;
+
+ /* 0x124 : GPIO_CFGCTL9 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_18_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_18_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_18_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_18_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_18_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_18_func_sel : 4; /* [11: 8], r/w, 0xb */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t reg_gpio_19_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_19_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_19_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_19_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_19_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_19_func_sel : 4; /* [27:24], r/w, 0xb */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL9;
+
+ /* 0x128 : GPIO_CFGCTL10 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_20_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_20_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_20_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_20_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_20_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_20_func_sel : 4; /* [11: 8], r/w, 0xb */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t reg_gpio_21_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_21_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_21_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_21_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_21_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_21_func_sel : 4; /* [27:24], r/w, 0xb */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL10;
+
+ /* 0x12C : GPIO_CFGCTL11 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_22_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_22_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_22_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_22_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_22_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_22_func_sel : 4; /* [11: 8], r/w, 0xb */
+ uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
+ uint32_t reg_gpio_23_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_23_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_23_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_23_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_23_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL11;
+
+ /* 0x130 : GPIO_CFGCTL12 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_24_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_24_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_24_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_24_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_24_pd : 1; /* [ 5], r/w, 0x1 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_25_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_25_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_25_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_25_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_25_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL12;
+
+ /* 0x134 : GPIO_CFGCTL13 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_26_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_26_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_26_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_26_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_26_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_27_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_27_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_27_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_27_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_27_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL13;
+
+ /* 0x138 : GPIO_CFGCTL14 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_28_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_28_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_28_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_28_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_28_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL14;
+
+ /* 0x13c reserved */
+
+ uint8_t reserved_0x13c[68];
+
+ /* 0x180 : GPIO_CFGCTL30 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_0_i : 1; /* [ 0], r, 0x0 */
+ uint32_t reg_gpio_1_i : 1; /* [ 1], r, 0x0 */
+ uint32_t reg_gpio_2_i : 1; /* [ 2], r, 0x0 */
+ uint32_t reg_gpio_3_i : 1; /* [ 3], r, 0x0 */
+ uint32_t reg_gpio_4_i : 1; /* [ 4], r, 0x0 */
+ uint32_t reg_gpio_5_i : 1; /* [ 5], r, 0x0 */
+ uint32_t reg_gpio_6_i : 1; /* [ 6], r, 0x0 */
+ uint32_t reg_gpio_7_i : 1; /* [ 7], r, 0x0 */
+ uint32_t reg_gpio_8_i : 1; /* [ 8], r, 0x0 */
+ uint32_t reg_gpio_9_i : 1; /* [ 9], r, 0x0 */
+ uint32_t reg_gpio_10_i : 1; /* [ 10], r, 0x0 */
+ uint32_t reg_gpio_11_i : 1; /* [ 11], r, 0x0 */
+ uint32_t reg_gpio_12_i : 1; /* [ 12], r, 0x0 */
+ uint32_t reg_gpio_13_i : 1; /* [ 13], r, 0x0 */
+ uint32_t reg_gpio_14_i : 1; /* [ 14], r, 0x0 */
+ uint32_t reg_gpio_15_i : 1; /* [ 15], r, 0x0 */
+ uint32_t reg_gpio_16_i : 1; /* [ 16], r, 0x0 */
+ uint32_t reg_gpio_17_i : 1; /* [ 17], r, 0x0 */
+ uint32_t reg_gpio_18_i : 1; /* [ 18], r, 0x0 */
+ uint32_t reg_gpio_19_i : 1; /* [ 19], r, 0x0 */
+ uint32_t reg_gpio_20_i : 1; /* [ 20], r, 0x0 */
+ uint32_t reg_gpio_21_i : 1; /* [ 21], r, 0x0 */
+ uint32_t reg_gpio_22_i : 1; /* [ 22], r, 0x0 */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL30;
+
+ /* 0x184 : GPIO_CFGCTL31 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL31;
+
+ /* 0x188 : GPIO_CFGCTL32 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_0_o : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_1_o : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_gpio_2_o : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_gpio_3_o : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reg_gpio_4_o : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_5_o : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_6_o : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg_gpio_7_o : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg_gpio_8_o : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg_gpio_9_o : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reg_gpio_10_o : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reg_gpio_11_o : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reg_gpio_12_o : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg_gpio_13_o : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reg_gpio_14_o : 1; /* [ 14], r/w, 0x0 */
+ uint32_t reg_gpio_15_o : 1; /* [ 15], r/w, 0x0 */
+ uint32_t reg_gpio_16_o : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reg_gpio_17_o : 1; /* [ 17], r/w, 0x0 */
+ uint32_t reg_gpio_18_o : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reg_gpio_19_o : 1; /* [ 19], r/w, 0x0 */
+ uint32_t reg_gpio_20_o : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_21_o : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reg_gpio_22_o : 1; /* [ 22], r/w, 0x0 */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL32;
+
+ /* 0x18C : GPIO_CFGCTL33 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL33;
+
+ /* 0x190 : GPIO_CFGCTL34 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_0_oe : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reg_gpio_1_oe : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reg_gpio_2_oe : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reg_gpio_3_oe : 1; /* [ 3], r/w, 0x0 */
+ uint32_t reg_gpio_4_oe : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_5_oe : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reg_gpio_6_oe : 1; /* [ 6], r/w, 0x0 */
+ uint32_t reg_gpio_7_oe : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reg_gpio_8_oe : 1; /* [ 8], r/w, 0x0 */
+ uint32_t reg_gpio_9_oe : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reg_gpio_10_oe : 1; /* [ 10], r/w, 0x0 */
+ uint32_t reg_gpio_11_oe : 1; /* [ 11], r/w, 0x0 */
+ uint32_t reg_gpio_12_oe : 1; /* [ 12], r/w, 0x0 */
+ uint32_t reg_gpio_13_oe : 1; /* [ 13], r/w, 0x0 */
+ uint32_t reg_gpio_14_oe : 1; /* [ 14], r/w, 0x0 */
+ uint32_t reg_gpio_15_oe : 1; /* [ 15], r/w, 0x0 */
+ uint32_t reg_gpio_16_oe : 1; /* [ 16], r/w, 0x0 */
+ uint32_t reg_gpio_17_oe : 1; /* [ 17], r/w, 0x0 */
+ uint32_t reg_gpio_18_oe : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reg_gpio_19_oe : 1; /* [ 19], r/w, 0x0 */
+ uint32_t reg_gpio_20_oe : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_21_oe : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reg_gpio_22_oe : 1; /* [ 22], r/w, 0x0 */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL34;
+
+ /* 0x194 : GPIO_CFGCTL35 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL35;
+
+ /* 0x198 reserved */
+
+ uint8_t reserved_0x198[8];
+
+ /* 0x1A0 : GPIO_INT_MASK1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_int_mask1 : 32; /* [31: 0], r/w, 0xffffffffL */
+ } bf;
+ uint32_t word;
+ } GPIO_INT_MASK1;
+
+ /* 0x1a4 reserved */
+
+ uint8_t reserved_0x1a4[4];
+
+ /* 0x1A8 : GPIO_INT_STAT1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t gpio_int_stat1 : 32; /* [31: 0], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_INT_STAT1;
+
+ /* 0x1ac reserved */
+
+ uint8_t reserved_0x1ac[4];
+
+ /* 0x1B0 : GPIO_INT_CLR1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_int_clr1 : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_INT_CLR1;
+
+ /* 0x1b4 reserved */
+
+ uint8_t reserved_0x1b4[12];
+
+ /* 0x1C0 : GPIO_INT_MODE_SET1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_int_mode_set1 : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_INT_MODE_SET1;
+
+ /* 0x1C4 : GPIO_INT_MODE_SET2 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_int_mode_set2 : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_INT_MODE_SET2;
+
+ /* 0x1C8 : GPIO_INT_MODE_SET3 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_int_mode_set3 : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } GPIO_INT_MODE_SET3;
+
+ /* 0x1cc reserved */
+
+ uint8_t reserved_0x1cc[88];
+
+ /* 0x224 : led_driver */
+
+ union
+ {
+ struct
+ {
+ uint32_t led_din_reg : 1; /* [ 0], r/w, 0x0 */
+ uint32_t led_din_sel : 1; /* [ 1], r/w, 0x0 */
+ uint32_t led_din_polarity_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t leddrv_ibias : 4; /* [ 7: 4], r/w, 0x8 */
+ uint32_t ir_rx_gpio_sel : 2; /* [ 9: 8], r/w, 0x0 */
+ uint32_t reserved_10_30 : 21; /* [30:10], rsvd, 0x0 */
+ uint32_t pu_leddrv : 1; /* [ 31], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } led_driver;
+
+ /* 0x228 reserved */
+
+ uint8_t reserved_0x228[224];
+
+ /* 0x308 : gpdac_ctrl */
+
+ union
+ {
+ struct
+ {
+ uint32_t gpdaca_rstn_ana : 1; /* [ 0], r/w, 0x1 */
+ uint32_t gpdacb_rstn_ana : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reserved_2_6 : 5; /* [ 6: 2], rsvd, 0x0 */
+ uint32_t gpdac_test_en : 1; /* [ 7], r/w, 0x0 */
+ uint32_t gpdac_ref_sel : 1; /* [ 8], r/w, 0x0 */
+ uint32_t gpdac_test_sel : 3; /* [11: 9], r/w, 0x0 */
+ uint32_t reserved_12_23 : 12; /* [23:12], rsvd, 0x0 */
+ uint32_t gpdac_reserved : 8; /* [31:24], r/w, 0xf */
+ } bf;
+ uint32_t word;
+ } gpdac_ctrl;
+
+ /* 0x30C : gpdac_actrl */
+
+ union
+ {
+ struct
+ {
+ uint32_t gpdac_a_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t gpdac_ioa_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */
+ uint32_t gpdac_a_rng : 2; /* [19:18], r/w, 0x3 */
+ uint32_t gpdac_a_outmux : 3; /* [22:20], r/w, 0x0 */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } gpdac_actrl;
+
+ /* 0x310 : gpdac_bctrl */
+
+ union
+ {
+ struct
+ {
+ uint32_t gpdac_b_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t gpdac_iob_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t reserved_2_17 : 16; /* [17: 2], rsvd, 0x0 */
+ uint32_t gpdac_b_rng : 2; /* [19:18], r/w, 0x3 */
+ uint32_t gpdac_b_outmux : 3; /* [22:20], r/w, 0x0 */
+ uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } gpdac_bctrl;
+
+ /* 0x314 : gpdac_data */
+
+ union
+ {
+ struct
+ {
+ uint32_t gpdac_b_data : 10; /* [ 9: 0], r/w, 0x0 */
+ uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
+ uint32_t gpdac_a_data : 10; /* [25:16], r/w, 0x0 */
+ uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } gpdac_data;
+
+ /* 0x318 reserved */
+
+ uint8_t reserved_0x318[3048];
+
+ /* 0xF00 : tzc_glb_ctrl_0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t tzc_glb_swrst_s00_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_glb_swrst_s01_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
+ uint32_t tzc_glb_swrst_s30_lock : 1; /* [ 8], r, 0x0 */
+ uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
+ uint32_t tzc_glb_ctrl_pwron_rst_lock : 1; /* [ 12], r, 0x0 */
+ uint32_t tzc_glb_ctrl_cpu_reset_lock : 1; /* [ 13], r, 0x0 */
+ uint32_t tzc_glb_ctrl_sys_reset_lock : 1; /* [ 14], r, 0x0 */
+ uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; /* [ 15], r, 0x0 */
+ uint32_t reserved_16_24 : 9; /* [24:16], rsvd, 0x0 */
+ uint32_t tzc_glb_misc_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_glb_sram_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t tzc_glb_l2c_lock : 1; /* [ 27], r, 0x0 */
+ uint32_t tzc_glb_bmx_lock : 1; /* [ 28], r, 0x0 */
+ uint32_t tzc_glb_dbg_lock : 1; /* [ 29], r, 0x0 */
+ uint32_t tzc_glb_mbist_lock : 1; /* [ 30], r, 0x0 */
+ uint32_t tzc_glb_clk_lock : 1; /* [ 31], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } tzc_glb_ctrl_0;
+
+ /* 0xF04 : tzc_glb_ctrl_1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t tzc_glb_swrst_s20_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_glb_swrst_s21_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_glb_swrst_s22_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_glb_swrst_s23_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_glb_swrst_s24_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_glb_swrst_s25_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_glb_swrst_s26_lock : 1; /* [ 6], r, 0x0 */
+ uint32_t tzc_glb_swrst_s27_lock : 1; /* [ 7], r, 0x0 */
+ uint32_t tzc_glb_swrst_s28_lock : 1; /* [ 8], r, 0x0 */
+ uint32_t tzc_glb_swrst_s29_lock : 1; /* [ 9], r, 0x0 */
+ uint32_t tzc_glb_swrst_s2a_lock : 1; /* [ 10], r, 0x0 */
+ uint32_t tzc_glb_swrst_s2b_lock : 1; /* [ 11], r, 0x0 */
+ uint32_t tzc_glb_swrst_s2c_lock : 1; /* [ 12], r, 0x0 */
+ uint32_t tzc_glb_swrst_s2d_lock : 1; /* [ 13], r, 0x0 */
+ uint32_t tzc_glb_swrst_s2e_lock : 1; /* [ 14], r, 0x0 */
+ uint32_t tzc_glb_swrst_s2f_lock : 1; /* [ 15], r, 0x0 */
+ uint32_t tzc_glb_swrst_s10_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_glb_swrst_s11_lock : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_glb_swrst_s12_lock : 1; /* [ 18], r, 0x0 */
+ uint32_t tzc_glb_swrst_s13_lock : 1; /* [ 19], r, 0x0 */
+ uint32_t tzc_glb_swrst_s14_lock : 1; /* [ 20], r, 0x0 */
+ uint32_t tzc_glb_swrst_s15_lock : 1; /* [ 21], r, 0x0 */
+ uint32_t tzc_glb_swrst_s16_lock : 1; /* [ 22], r, 0x0 */
+ uint32_t tzc_glb_swrst_s17_lock : 1; /* [ 23], r, 0x0 */
+ uint32_t tzc_glb_swrst_s18_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_glb_swrst_s19_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_glb_swrst_s1a_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t tzc_glb_swrst_s1b_lock : 1; /* [ 27], r, 0x0 */
+ uint32_t tzc_glb_swrst_s1c_lock : 1; /* [ 28], r, 0x0 */
+ uint32_t tzc_glb_swrst_s1d_lock : 1; /* [ 29], r, 0x0 */
+ uint32_t tzc_glb_swrst_s1e_lock : 1; /* [ 30], r, 0x0 */
+ uint32_t tzc_glb_swrst_s1f_lock : 1; /* [ 31], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } tzc_glb_ctrl_1;
+
+ /* 0xF08 : tzc_glb_ctrl_2 */
+
+ union
+ {
+ struct
+ {
+ uint32_t tzc_glb_gpio_0_lock : 1; /* [ 0], r, 0x0 */
+ uint32_t tzc_glb_gpio_1_lock : 1; /* [ 1], r, 0x0 */
+ uint32_t tzc_glb_gpio_2_lock : 1; /* [ 2], r, 0x0 */
+ uint32_t tzc_glb_gpio_3_lock : 1; /* [ 3], r, 0x0 */
+ uint32_t tzc_glb_gpio_4_lock : 1; /* [ 4], r, 0x0 */
+ uint32_t tzc_glb_gpio_5_lock : 1; /* [ 5], r, 0x0 */
+ uint32_t tzc_glb_gpio_6_lock : 1; /* [ 6], r, 0x0 */
+ uint32_t tzc_glb_gpio_7_lock : 1; /* [ 7], r, 0x0 */
+ uint32_t tzc_glb_gpio_8_lock : 1; /* [ 8], r, 0x0 */
+ uint32_t tzc_glb_gpio_9_lock : 1; /* [ 9], r, 0x0 */
+ uint32_t tzc_glb_gpio_10_lock : 1; /* [ 10], r, 0x0 */
+ uint32_t tzc_glb_gpio_11_lock : 1; /* [ 11], r, 0x0 */
+ uint32_t tzc_glb_gpio_12_lock : 1; /* [ 12], r, 0x0 */
+ uint32_t tzc_glb_gpio_13_lock : 1; /* [ 13], r, 0x0 */
+ uint32_t tzc_glb_gpio_14_lock : 1; /* [ 14], r, 0x0 */
+ uint32_t tzc_glb_gpio_15_lock : 1; /* [ 15], r, 0x0 */
+ uint32_t tzc_glb_gpio_16_lock : 1; /* [ 16], r, 0x0 */
+ uint32_t tzc_glb_gpio_17_lock : 1; /* [ 17], r, 0x0 */
+ uint32_t tzc_glb_gpio_18_lock : 1; /* [ 18], r, 0x0 */
+ uint32_t tzc_glb_gpio_19_lock : 1; /* [ 19], r, 0x0 */
+ uint32_t tzc_glb_gpio_20_lock : 1; /* [ 20], r, 0x0 */
+ uint32_t tzc_glb_gpio_21_lock : 1; /* [ 21], r, 0x0 */
+ uint32_t tzc_glb_gpio_22_lock : 1; /* [ 22], r, 0x0 */
+ uint32_t tzc_glb_gpio_23_lock : 1; /* [ 23], r, 0x0 */
+ uint32_t tzc_glb_gpio_24_lock : 1; /* [ 24], r, 0x0 */
+ uint32_t tzc_glb_gpio_25_lock : 1; /* [ 25], r, 0x0 */
+ uint32_t tzc_glb_gpio_26_lock : 1; /* [ 26], r, 0x0 */
+ uint32_t tzc_glb_gpio_27_lock : 1; /* [ 27], r, 0x0 */
+ uint32_t tzc_glb_gpio_28_lock : 1; /* [ 28], r, 0x0 */
+ uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } tzc_glb_ctrl_2;
+
+ /* 0xF0C : tzc_glb_ctrl_3 */
+
+ union
+ {
+ struct
+ {
+ uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } tzc_glb_ctrl_3;
+};
+
+typedef volatile struct glb_reg_s glb_reg_t;
+
+struct glb_gpio_reg_s
+{
+ /* 0x0 : GPIO_CFGCTL */
+
+ union
+ {
+ struct
+ {
+ uint32_t reg_gpio_0_ie : 1; /* [ 0], r/w, 0x1 */
+ uint32_t reg_gpio_0_smt : 1; /* [ 1], r/w, 0x1 */
+ uint32_t reg_gpio_0_drv : 2; /* [ 3: 2], r/w, 0x0 */
+ uint32_t reg_gpio_0_pu : 1; /* [ 4], r/w, 0x0 */
+ uint32_t reg_gpio_0_pd : 1; /* [ 5], r/w, 0x0 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t reg_gpio_0_func_sel : 4; /* [11: 8], r/w, 0x1 */
+ uint32_t real_gpio_0_func_sel : 4; /* [15:12], r, 0x1 */
+ uint32_t reg_gpio_1_ie : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reg_gpio_1_smt : 1; /* [ 17], r/w, 0x1 */
+ uint32_t reg_gpio_1_drv : 2; /* [19:18], r/w, 0x0 */
+ uint32_t reg_gpio_1_pu : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reg_gpio_1_pd : 1; /* [ 21], r/w, 0x0 */
+ uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
+ uint32_t reg_gpio_1_func_sel : 4; /* [27:24], r/w, 0x1 */
+ uint32_t real_gpio_1_func_sel : 4; /* [31:28], r, 0x1 */
+ } bf;
+ uint32_t word;
+ } GPIO_CFGCTL;
+};
+
+typedef volatile struct glb_gpio_reg_s glb_gpio_reg_t;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: <Inline function name>
+ *
+ * Description:
+ * Description of the operation of the inline function.
+ *
+ * Input Parameters:
+ * A list of input parameters, one-per-line, appears here along with a
+ * description of each input parameter.
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: <Global function name>
+ *
+ * Description:
+ * Select UART signal function.
+ *
+ * Input Parameters:
+ * sig: UART signal
+ * fun: UART function
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void glb_uart_fun_sel(enum glb_uart_sig_e sig, enum glb_uart_sig_fun_e fun);
+
+/****************************************************************************
+ * Name: glb_ahb_slave1_reset
+ *
+ * Description:
+ * Select UART signal function.
+ *
+ * Input Parameters:
+ * sig: UART signal
+ * fun: UART function
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void glb_ahb_slave1_reset(enum bl_ahb_slave1_e slave1);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GLB_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_gpio.h b/arch/risc-v/src/bl602/hardware/bl602_gpio.h
new file mode 100644
index 0000000000..2b21aedf74
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_gpio.h
@@ -0,0 +1,507 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIO_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hardware/bl602_common.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Input Floating Mode */
+
+#define GPIO_MODE_INPUT ((uint32_t)0x00000000U)
+
+/* Output Push Pull Mode */
+
+#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U)
+
+/* Alternate function */
+
+#define GPIO_MODE_AF ((uint32_t)0x00000002U)
+
+/* GPIO pull up */
+
+#define GPIO_PULL_UP ((uint32_t)0x00000000U)
+
+/* GPIO pull down */
+
+#define GPIO_PULL_DOWN ((uint32_t)0x00000001U)
+
+/* GPIO no pull up or down */
+
+#define GPIO_PULL_NONE ((uint32_t)0x00000002U)
+
+/* GPIO0 function definition */
+
+#define GPIO0_FUN_SDIO_CLK 1
+#define GPIO0_FUN_SF_D1 2
+#define GPIO0_FUN_UNUSED3 3
+#define GPIO0_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO0_FUN_UNUSED5 5
+#define GPIO0_FUN_I2C_SCL 6
+#define GPIO0_FUN_UART_SIG0 7
+#define GPIO0_FUN_PWM_CH0 8
+#define GPIO0_FUN_FEM_GPIO_0 9
+#define GPIO0_FUN_ATEST_IN 10
+#define GPIO0_FUN_SWGPIO_0 11
+#define GPIO0_FUN_E21_TMS 14
+
+/* GPIO1 function definition */
+
+#define GPIO1_FUN_SDIO_CMD 1
+#define GPIO1_FUN_SF_D2 2
+#define GPIO1_FUN_UNUSED3 3
+#define GPIO1_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO1_FUN_UNUSED5 5
+#define GPIO1_FUN_I2C_SDA 6
+#define GPIO1_FUN_UART_SIG1 7
+#define GPIO1_FUN_PWM_CH1 8
+#define GPIO1_FUN_FEM_GPIO_1 9
+#define GPIO1_FUN_ATEST_IP 10
+#define GPIO1_FUN_SWGPIO_1 11
+#define GPIO1_FUN_E21_TDI 14
+
+/* GPIO2 function definition */
+
+#define GPIO2_FUN_SDIO_DAT0 1
+#define GPIO2_FUN_SF_D3 2
+#define GPIO2_FUN_UNUSED3 3
+#define GPIO2_FUN_SPI_SS 4
+#define GPIO2_FUN_UNUSED5 5
+#define GPIO2_FUN_I2C_SCL 6
+#define GPIO2_FUN_UART_SIG2 7
+#define GPIO2_FUN_PWM_CH2 8
+#define GPIO2_FUN_FEM_GPIO_2 9
+#define GPIO2_FUN_ATEST_QN 10
+#define GPIO2_FUN_SWGPIO_2 11
+#define GPIO2_FUN_E21_TCK 14
+
+/* GPIO3 function definition */
+
+#define GPIO3_FUN_SDIO_DAT1 1
+#define GPIO3_FUN_UNUSED2 2
+#define GPIO3_FUN_UNUSED3 3
+#define GPIO3_FUN_SPI_SCLK 4
+#define GPIO3_FUN_UNUSED5 5
+#define GPIO3_FUN_I2C_SDA 6
+#define GPIO3_FUN_UART_SIG3 7
+#define GPIO3_FUN_PWM_CH3 8
+#define GPIO3_FUN_FEM_GPIO_3 9
+#define GPIO3_FUN_ATEST_QP 10
+#define GPIO3_FUN_SWGPIO_3 11
+#define GPIO3_FUN_E21_TDO 14
+
+/* GPIO4 function definition */
+
+#define GPIO4_FUN_SDIO_DAT2 1
+#define GPIO4_FUN_UNUSED2 2
+#define GPIO4_FUN_UNUSED3 3
+#define GPIO4_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO4_FUN_UNUSED5 5
+#define GPIO4_FUN_I2C_SCL 6
+#define GPIO4_FUN_UART_SIG4 7
+#define GPIO4_FUN_PWM_CH4 8
+#define GPIO4_FUN_FEM_GPIO_0 9
+#define GPIO4_FUN_GPIP_CH1 10
+#define GPIO4_FUN_SWGPIO_4 11
+#define GPIO4_FUN_E21_TMS 14
+
+/* GPIO5 function definition */
+
+#define GPIO5_FUN_SDIO_DAT3 1
+#define GPIO5_FUN_UNUSED2 2
+#define GPIO5_FUN_UNUSED3 3
+#define GPIO5_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO5_FUN_UNUSED5 5
+#define GPIO5_FUN_I2C_SDA 6
+#define GPIO5_FUN_UART_SIG5 7
+#define GPIO5_FUN_PWM_CH0 8
+#define GPIO5_FUN_FEM_GPIO_1 9
+#define GPIO5_FUN_GPIP_CH4 10
+#define GPIO5_FUN_SWGPIO_5 11
+#define GPIO5_FUN_E21_TDI 14
+
+/* GPIO6 function definition */
+
+#define GPIO6_FUN_UNUSED1 1
+#define GPIO6_FUN_UNUSED2 2
+#define GPIO6_FUN_UNUSED3 3
+#define GPIO6_FUN_SPI_SS 4
+#define GPIO6_FUN_UNUSED5 5
+#define GPIO6_FUN_I2C_SCL 6
+#define GPIO6_FUN_UART_SIG6 7
+#define GPIO6_FUN_PWM_CH1 8
+#define GPIO6_FUN_FEM_GPIO_2 9
+#define GPIO6_FUN_GPIP_CH5 10
+#define GPIO6_FUN_SWGPIO_6 11
+#define GPIO6_FUN_E21_TCK 14
+
+/* GPIO7 function definition */
+
+#define GPIO7_FUN_UNUSED1 1
+#define GPIO7_FUN_UNUSED2 2
+#define GPIO7_FUN_UNUSED3 3
+#define GPIO7_FUN_SPI_SCLK 4
+#define GPIO7_FUN_UNUSED5 5
+#define GPIO7_FUN_I2C_SDA 6
+#define GPIO7_FUN_UART_SIG7 7
+#define GPIO7_FUN_PWM_CH2 8
+#define GPIO7_FUN_FEM_GPIO_3 9
+#define GPIO7_FUN_UNUSED10 10
+#define GPIO7_FUN_SWGPIO_7 11
+#define GPIO7_FUN_E21_TDO 14
+
+/* GPIO8 function definition */
+
+#define GPIO8_FUN_UNUSED1 1
+#define GPIO8_FUN_UNUSED2 2
+#define GPIO8_FUN_UNUSED3 3
+#define GPIO8_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO8_FUN_UNUSED5 5
+#define GPIO8_FUN_I2C_SCL 6
+#define GPIO8_FUN_UART_SIG0 7
+#define GPIO8_FUN_PWM_CH3 8
+#define GPIO8_FUN_FEM_GPIO_0 9
+#define GPIO8_FUN_UNUSED10 10
+#define GPIO8_FUN_SWGPIO_8 11
+#define GPIO8_FUN_E21_TMS 14
+
+/* GPIO9 function definition */
+
+#define GPIO9_FUN_UNUSED1 1
+#define GPIO9_FUN_UNUSED2 2
+#define GPIO9_FUN_UNUSED3 3
+#define GPIO9_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO9_FUN_UNUSED5 5
+#define GPIO9_FUN_I2C_SDA 6
+#define GPIO9_FUN_UART_SIG1 7
+#define GPIO9_FUN_PWM_CH4 8
+#define GPIO9_FUN_FEM_GPIO_1 9
+#define GPIO9_FUN_GPIP_CH6_GPIP_CH7 10
+#define GPIO9_FUN_SWGPIO_9 11
+#define GPIO9_FUN_E21_TDI 14
+
+/* GPIO10 function definition */
+
+#define GPIO10_FUN_UNUSED1 1
+#define GPIO10_FUN_UNUSED2 2
+#define GPIO10_FUN_UNUSED3 3
+#define GPIO10_FUN_SPI_SS 4
+#define GPIO10_FUN_UNUSED5 5
+#define GPIO10_FUN_I2C_SCL 6
+#define GPIO10_FUN_UART_SIG2 7
+#define GPIO10_FUN_PWM_CH0 8
+#define GPIO10_FUN_FEM_GPIO_2 9
+#define GPIO10_FUN_MICBIAS_GPIP_CH8_GPIP_CH9 10
+#define GPIO10_FUN_SWGPIO_10 11
+#define GPIO10_FUN_E21_TCK 14
+
+/* GPIO11 function definition */
+
+#define GPIO11_FUN_UNUSED1 1
+#define GPIO11_FUN_UNUSED2 2
+#define GPIO11_FUN_UNUSED3 3
+#define GPIO11_FUN_SPI_SCLK 4
+#define GPIO11_FUN_UNUSED5 5
+#define GPIO11_FUN_I2C_SDA 6
+#define GPIO11_FUN_UART_SIG3 7
+#define GPIO11_FUN_PWM_CH1 8
+#define GPIO11_FUN_FEM_GPIO_3 9
+#define GPIO11_FUN_IRLED_OUT_GPIP_CH10 10
+#define GPIO11_FUN_SWGPIO_11 11
+#define GPIO11_FUN_E21_TDO 14
+
+/* GPIO12 function definition */
+
+#define GPIO12_FUN_UNUSED1 1
+#define GPIO12_FUN_UNUSED2 2
+#define GPIO12_FUN_UNUSED3 3
+#define GPIO12_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO12_FUN_UNUSED5 5
+#define GPIO12_FUN_I2C_SCL 6
+#define GPIO12_FUN_UART_SIG4 7
+#define GPIO12_FUN_PWM_CH2 8
+#define GPIO12_FUN_FEM_GPIO_0 9
+#define GPIO12_FUN_GPIP_CH0_GPADC_VREF_EXT 10
+#define GPIO12_FUN_SWGPIO_12 11
+#define GPIO12_FUN_E21_TMS 14
+
+/* GPIO13 function definition */
+
+#define GPIO13_FUN_UNUSED1 1
+#define GPIO13_FUN_UNUSED2 2
+#define GPIO13_FUN_UNUSED3 3
+#define GPIO13_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO13_FUN_UNUSED5 5
+#define GPIO13_FUN_I2C_SDA 6
+#define GPIO13_FUN_UART_SIG5 7
+#define GPIO13_FUN_PWM_CH3 8
+#define GPIO13_FUN_FEM_GPIO_1 9
+#define GPIO13_FUN_GPIP_CH3 10
+#define GPIO13_FUN_SWGPIO_13 11
+#define GPIO13_FUN_E21_TDI 14
+
+/* GPIO14 function definition */
+
+#define GPIO14_FUN_UNUSED1 1
+#define GPIO14_FUN_UNUSED2 2
+#define GPIO14_FUN_UNUSED3 3
+#define GPIO14_FUN_SPI_SS 4
+#define GPIO14_FUN_UNUSED5 5
+#define GPIO14_FUN_I2C_SCL 6
+#define GPIO14_FUN_UART_SIG6 7
+#define GPIO14_FUN_PWM_CH4 8
+#define GPIO14_FUN_FEM_GPIO_2 9
+#define GPIO14_FUN_GPIP_CH2 10
+#define GPIO14_FUN_SWGPIO_14 11
+#define GPIO14_FUN_E21_TCK 14
+
+/* GPIO15 function definition */
+
+#define GPIO15_FUN_UNUSED1 1
+#define GPIO15_FUN_UNUSED2 2
+#define GPIO15_FUN_UNUSED3 3
+#define GPIO15_FUN_SPI_SCLK 4
+#define GPIO15_FUN_UNUSED5 5
+#define GPIO15_FUN_I2C_SDA 6
+#define GPIO15_FUN_UART_SIG7 7
+#define GPIO15_FUN_PWM_CH0 8
+#define GPIO15_FUN_FEM_GPIO_3 9
+#define GPIO15_FUN_PSW_IRRCV_OUT_GPIP_CH11 10
+#define GPIO15_FUN_SWGPIO_15 11
+#define GPIO15_FUN_E21_TDO 14
+
+/* GPIO16 function definition */
+
+#define GPIO16_FUN_UNUSED1 1
+#define GPIO16_FUN_UNUSED2 2
+#define GPIO16_FUN_UNUSED3 3
+#define GPIO16_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO16_FUN_UNUSED5 5
+#define GPIO16_FUN_I2C_SCL 6
+#define GPIO16_FUN_UART_SIG0 7
+#define GPIO16_FUN_PWM_CH1 8
+#define GPIO16_FUN_FEM_GPIO_0 9
+#define GPIO16_FUN_UNUSED10 10
+#define GPIO16_FUN_SWGPIO_16 11
+#define GPIO16_FUN_E21_TMS 14
+
+/* GPIO17 function definition */
+
+#define GPIO17_FUN_UNUSED1 1
+#define GPIO17_FUN_SF_D3 2
+#define GPIO17_FUN_UNUSED3 3
+#define GPIO17_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO17_FUN_UNUSED5 5
+#define GPIO17_FUN_I2C_SDA 6
+#define GPIO17_FUN_UART_SIG1 7
+#define GPIO17_FUN_PWM_CH2 8
+#define GPIO17_FUN_FEM_GPIO_1 9
+#define GPIO17_FUN_PMIP_DC_TP_OUT 10
+#define GPIO17_FUN_SWGPIO_17 11
+#define GPIO17_FUN_E21_TDI 14
+
+/* GPIO18 function definition */
+
+#define GPIO18_FUN_UNUSED1 1
+#define GPIO18_FUN_SF_D2 2
+#define GPIO18_FUN_UNUSED3 3
+#define GPIO18_FUN_SPI_SS 4
+#define GPIO18_FUN_UNUSED5 5
+#define GPIO18_FUN_I2C_SCL 6
+#define GPIO18_FUN_UART_SIG2 7
+#define GPIO18_FUN_PWM_CH3 8
+#define GPIO18_FUN_FEM_GPIO_2 9
+#define GPIO18_FUN_UNUSED10 10
+#define GPIO18_FUN_SWGPIO_18 11
+#define GPIO18_FUN_E21_TCK 14
+
+/* GPIO19 function definition */
+
+#define GPIO19_FUN_UNUSED1 1
+#define GPIO19_FUN_SF_D1 2
+#define GPIO19_FUN_UNUSED3 3
+#define GPIO19_FUN_SPI_SCLK 4
+#define GPIO19_FUN_UNUSED5 5
+#define GPIO19_FUN_I2C_SDA 6
+#define GPIO19_FUN_UART_SIG3 7
+#define GPIO19_FUN_PWM_CH4 8
+#define GPIO19_FUN_FEM_GPIO_3 9
+#define GPIO19_FUN_UNUSED10 10
+#define GPIO19_FUN_SWGPIO_19 11
+#define GPIO19_FUN_E21_TDO 14
+
+/* GPIO20 function definition */
+
+#define GPIO20_FUN_UNUSED1 1
+#define GPIO20_FUN_SF_D0 2
+#define GPIO20_FUN_UNUSED3 3
+#define GPIO20_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO20_FUN_UNUSED5 5
+#define GPIO20_FUN_I2C_SCL 6
+#define GPIO20_FUN_UART_SIG4 7
+#define GPIO20_FUN_PWM_CH0 8
+#define GPIO20_FUN_FEM_GPIO_0 9
+#define GPIO20_FUN_UNUSED10 10
+#define GPIO20_FUN_SWGPIO_20 11
+#define GPIO20_FUN_E21_TMS 14
+
+/* GPIO21 function definition */
+
+#define GPIO21_FUN_UNUSED1 1
+#define GPIO21_FUN_SF_CS 2
+#define GPIO21_FUN_UNUSED3 3
+#define GPIO21_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO21_FUN_UNUSED5 5
+#define GPIO21_FUN_I2C_SDA 6
+#define GPIO21_FUN_UART_SIG5 7
+#define GPIO21_FUN_PWM_CH1 8
+#define GPIO21_FUN_FEM_GPIO_1 9
+#define GPIO21_FUN_UNUSED10 10
+#define GPIO21_FUN_SWGPIO_21 11
+#define GPIO21_FUN_E21_TDI 14
+
+/* GPIO22 function definition */
+
+#define GPIO22_FUN_UNUSED1 1
+#define GPIO22_FUN_SF_CLK_OUT 2
+#define GPIO22_FUN_UNUSED3 3
+#define GPIO22_FUN_SPI_SS 4
+#define GPIO22_FUN_UNUSED5 5
+#define GPIO22_FUN_I2C_SCL 6
+#define GPIO22_FUN_UART_SIG6 7
+#define GPIO22_FUN_PWM_CH2 8
+#define GPIO22_FUN_FEM_GPIO_2 9
+#define GPIO22_FUN_UNUSED10 10
+#define GPIO22_FUN_SWGPIO_22 11
+#define GPIO22_FUN_E21_TCK 14
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+enum gpio_pins_e
+{
+ GLB_GPIO_PIN_0 = 0,
+ GLB_GPIO_PIN_1,
+ GLB_GPIO_PIN_2,
+ GLB_GPIO_PIN_3,
+ GLB_GPIO_PIN_4,
+ GLB_GPIO_PIN_5,
+ GLB_GPIO_PIN_6,
+ GLB_GPIO_PIN_7,
+ GLB_GPIO_PIN_8,
+ GLB_GPIO_PIN_9,
+ GLB_GPIO_PIN_10,
+ GLB_GPIO_PIN_11,
+ GLB_GPIO_PIN_12,
+ GLB_GPIO_PIN_13,
+ GLB_GPIO_PIN_14,
+ GLB_GPIO_PIN_15,
+ GLB_GPIO_PIN_16,
+ GLB_GPIO_PIN_17,
+ GLB_GPIO_PIN_18,
+ GLB_GPIO_PIN_19,
+ GLB_GPIO_PIN_20,
+ GLB_GPIO_PIN_21,
+ GLB_GPIO_PIN_22,
+ GLB_GPIO_PIN_MAX
+};
+
+enum gpio_fun_e
+{
+ GPIO_FUN_SDIO = 1,
+ GPIO_FUN_FLASH = 2,
+ GPIO_FUN_SPI = 4,
+ GPIO_FUN_I2C = 6,
+ GPIO_FUN_UART = 7,
+ GPIO_FUN_PWM = 8,
+ GPIO_FUN_EXT_PA = 8,
+ GPIO_FUN_ANALOG = 10,
+ GPIO_FUN_SWGPIO = 11,
+ GPIO_FUN_JTAG = 14
+};
+
+struct gpio_cfg_s
+{
+ enum gpio_pins_e gpio_pin;
+ enum gpio_fun_e gpio_fun;
+ int gpio_mode;
+ int pull_type;
+ int drive;
+ int smt_ctrl;
+};
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: gpio_init
+ *
+ * Description:
+ * Init a gpio pin.
+ *
+ * Input Parameters:
+ * cfg: gpio configuration
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+EXTERN void gpio_init(struct gpio_cfg_s *cfg);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIO_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_hbn.h b/arch/risc-v/src/bl602/hardware/bl602_hbn.h
new file mode 100644
index 0000000000..4493110b2a
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_hbn.h
@@ -0,0 +1,1024 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_hbn.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_HBN_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_HBN_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hardware/bl602_common.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* 0x0 : HBN_CTL */
+
+#define HBN_CTL_OFFSET (0x0)
+#define HBN_RTC_CTL HBN_RTC_CTL
+#define HBN_RTC_CTL_POS (0U)
+#define HBN_RTC_CTL_LEN (7U)
+#define HBN_RTC_CTL_MSK (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)
+#define HBN_RTC_CTL_UMSK (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS))
+#define HBN_MODE HBN_MODE
+#define HBN_MODE_POS (7U)
+#define HBN_MODE_LEN (1U)
+#define HBN_MODE_MSK (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)
+#define HBN_MODE_UMSK (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS))
+#define HBN_TRAP_MODE HBN_TRAP_MODE
+#define HBN_TRAP_MODE_POS (8U)
+#define HBN_TRAP_MODE_LEN (1U)
+#define HBN_TRAP_MODE_MSK \
+ (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)
+#define HBN_TRAP_MODE_UMSK \
+ (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS))
+#define HBN_PWRDN_HBN_CORE HBN_PWRDN_HBN_CORE
+#define HBN_PWRDN_HBN_CORE_POS (9U)
+#define HBN_PWRDN_HBN_CORE_LEN (1U)
+#define HBN_PWRDN_HBN_CORE_MSK \
+ (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)
+#define HBN_PWRDN_HBN_CORE_UMSK \
+ (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS))
+#define HBN_PWRDN_HBN_RTC HBN_PWRDN_HBN_RTC
+#define HBN_PWRDN_HBN_RTC_POS (11U)
+#define HBN_PWRDN_HBN_RTC_LEN (1U)
+#define HBN_PWRDN_HBN_RTC_MSK \
+ (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)
+#define HBN_PWRDN_HBN_RTC_UMSK \
+ (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS))
+#define HBN_SW_RST HBN_SW_RST
+#define HBN_SW_RST_POS (12U)
+#define HBN_SW_RST_LEN (1U)
+#define HBN_SW_RST_MSK (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)
+#define HBN_SW_RST_UMSK (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS))
+#define HBN_DIS_PWR_OFF_LDO11 HBN_DIS_PWR_OFF_LDO11
+#define HBN_DIS_PWR_OFF_LDO11_POS (13U)
+#define HBN_DIS_PWR_OFF_LDO11_LEN (1U)
+#define HBN_DIS_PWR_OFF_LDO11_MSK \
+ (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)
+#define HBN_DIS_PWR_OFF_LDO11_UMSK \
+ (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS))
+#define HBN_DIS_PWR_OFF_LDO11_RT HBN_DIS_PWR_OFF_LDO11_RT
+#define HBN_DIS_PWR_OFF_LDO11_RT_POS (14U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_LEN (1U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_MSK \
+ (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)
+#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK \
+ (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) \
+ << HBN_DIS_PWR_OFF_LDO11_RT_POS))
+#define HBN_LDO11_RT_VOUT_SEL HBN_LDO11_RT_VOUT_SEL
+#define HBN_LDO11_RT_VOUT_SEL_POS (15U)
+#define HBN_LDO11_RT_VOUT_SEL_LEN (4U)
+#define HBN_LDO11_RT_VOUT_SEL_MSK \
+ (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)
+#define HBN_LDO11_RT_VOUT_SEL_UMSK \
+ (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS))
+#define HBN_LDO11_AON_VOUT_SEL HBN_LDO11_AON_VOUT_SEL
+#define HBN_LDO11_AON_VOUT_SEL_POS (19U)
+#define HBN_LDO11_AON_VOUT_SEL_LEN (4U)
+#define HBN_LDO11_AON_VOUT_SEL_MSK \
+ (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)
+#define HBN_LDO11_AON_VOUT_SEL_UMSK \
+ (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS))
+#define HBN_PU_DCDC18_AON HBN_PU_DCDC18_AON
+#define HBN_PU_DCDC18_AON_POS (23U)
+#define HBN_PU_DCDC18_AON_LEN (1U)
+#define HBN_PU_DCDC18_AON_MSK \
+ (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)
+#define HBN_PU_DCDC18_AON_UMSK \
+ (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS))
+#define HBN_RTC_DLY_OPTION HBN_RTC_DLY_OPTION
+#define HBN_RTC_DLY_OPTION_POS (24U)
+#define HBN_RTC_DLY_OPTION_LEN (1U)
+#define HBN_RTC_DLY_OPTION_MSK \
+ (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)
+#define HBN_RTC_DLY_OPTION_UMSK \
+ (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS))
+#define HBN_PWR_ON_OPTION HBN_PWR_ON_OPTION
+#define HBN_PWR_ON_OPTION_POS (25U)
+#define HBN_PWR_ON_OPTION_LEN (1U)
+#define HBN_PWR_ON_OPTION_MSK \
+ (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)
+#define HBN_PWR_ON_OPTION_UMSK \
+ (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS))
+#define HBN_SRAM_SLP_OPTION HBN_SRAM_SLP_OPTION
+#define HBN_SRAM_SLP_OPTION_POS (26U)
+#define HBN_SRAM_SLP_OPTION_LEN (1U)
+#define HBN_SRAM_SLP_OPTION_MSK \
+ (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)
+#define HBN_SRAM_SLP_OPTION_UMSK \
+ (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS))
+#define HBN_SRAM_SLP HBN_SRAM_SLP
+#define HBN_SRAM_SLP_POS (27U)
+#define HBN_SRAM_SLP_LEN (1U)
+#define HBN_SRAM_SLP_MSK (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)
+#define HBN_SRAM_SLP_UMSK \
+ (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS))
+#define HBN_STATE HBN_STATE
+#define HBN_STATE_POS (28U)
+#define HBN_STATE_LEN (4U)
+#define HBN_STATE_MSK (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)
+#define HBN_STATE_UMSK (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS))
+
+/* 0x4 : HBN_TIME_L */
+
+#define HBN_TIME_L_OFFSET (0x4)
+#define HBN_TIME_L HBN_TIME_L
+#define HBN_TIME_L_POS (0U)
+#define HBN_TIME_L_LEN (32U)
+#define HBN_TIME_L_MSK (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)
+#define HBN_TIME_L_UMSK (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS))
+
+/* 0x8 : HBN_TIME_H */
+
+#define HBN_TIME_H_OFFSET (0x8)
+#define HBN_TIME_H HBN_TIME_H
+#define HBN_TIME_H_POS (0U)
+#define HBN_TIME_H_LEN (8U)
+#define HBN_TIME_H_MSK (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)
+#define HBN_TIME_H_UMSK (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS))
+
+/* 0xC : RTC_TIME_L */
+
+#define HBN_RTC_TIME_L_OFFSET (0xC)
+#define HBN_RTC_TIME_LATCH_L HBN_RTC_TIME_LATCH_L
+#define HBN_RTC_TIME_LATCH_L_POS (0U)
+#define HBN_RTC_TIME_LATCH_L_LEN (32U)
+#define HBN_RTC_TIME_LATCH_L_MSK \
+ (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)
+#define HBN_RTC_TIME_LATCH_L_UMSK \
+ (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS))
+
+/* 0x10 : RTC_TIME_H */
+
+#define HBN_RTC_TIME_H_OFFSET (0x10)
+#define HBN_RTC_TIME_LATCH_H HBN_RTC_TIME_LATCH_H
+#define HBN_RTC_TIME_LATCH_H_POS (0U)
+#define HBN_RTC_TIME_LATCH_H_LEN (8U)
+#define HBN_RTC_TIME_LATCH_H_MSK \
+ (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)
+#define HBN_RTC_TIME_LATCH_H_UMSK \
+ (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS))
+#define HBN_RTC_TIME_LATCH HBN_RTC_TIME_LATCH
+#define HBN_RTC_TIME_LATCH_POS (31U)
+#define HBN_RTC_TIME_LATCH_LEN (1U)
+#define HBN_RTC_TIME_LATCH_MSK \
+ (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)
+#define HBN_RTC_TIME_LATCH_UMSK \
+ (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS))
+
+/* 0x14 : HBN_IRQ_MODE */
+
+#define HBN_IRQ_MODE_OFFSET (0x14)
+#define HBN_PIN_WAKEUP_MODE HBN_PIN_WAKEUP_MODE
+#define HBN_PIN_WAKEUP_MODE_POS (0U)
+#define HBN_PIN_WAKEUP_MODE_LEN (3U)
+#define HBN_PIN_WAKEUP_MODE_MSK \
+ (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)
+#define HBN_PIN_WAKEUP_MODE_UMSK \
+ (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS))
+#define HBN_PIN_WAKEUP_MASK HBN_PIN_WAKEUP_MASK
+#define HBN_PIN_WAKEUP_MASK_POS (3U)
+#define HBN_PIN_WAKEUP_MASK_LEN (2U)
+#define HBN_PIN_WAKEUP_MASK_MSK \
+ (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)
+#define HBN_PIN_WAKEUP_MASK_UMSK \
+ (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS))
+#define HBN_REG_AON_PAD_IE_SMT HBN_REG_AON_PAD_IE_SMT
+#define HBN_REG_AON_PAD_IE_SMT_POS (8U)
+#define HBN_REG_AON_PAD_IE_SMT_LEN (1U)
+#define HBN_REG_AON_PAD_IE_SMT_MSK \
+ (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)
+#define HBN_REG_AON_PAD_IE_SMT_UMSK \
+ (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS))
+#define HBN_REG_EN_HW_PU_PD HBN_REG_EN_HW_PU_PD
+#define HBN_REG_EN_HW_PU_PD_POS (16U)
+#define HBN_REG_EN_HW_PU_PD_LEN (1U)
+#define HBN_REG_EN_HW_PU_PD_MSK \
+ (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)
+#define HBN_REG_EN_HW_PU_PD_UMSK \
+ (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS))
+#define HBN_IRQ_BOR_EN HBN_IRQ_BOR_EN
+#define HBN_IRQ_BOR_EN_POS (18U)
+#define HBN_IRQ_BOR_EN_LEN (1U)
+#define HBN_IRQ_BOR_EN_MSK \
+ (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)
+#define HBN_IRQ_BOR_EN_UMSK \
+ (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS))
+#define HBN_IRQ_ACOMP0_EN HBN_IRQ_ACOMP0_EN
+#define HBN_IRQ_ACOMP0_EN_POS (20U)
+#define HBN_IRQ_ACOMP0_EN_LEN (2U)
+#define HBN_IRQ_ACOMP0_EN_MSK \
+ (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)
+#define HBN_IRQ_ACOMP0_EN_UMSK \
+ (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS))
+#define HBN_IRQ_ACOMP1_EN HBN_IRQ_ACOMP1_EN
+#define HBN_IRQ_ACOMP1_EN_POS (22U)
+#define HBN_IRQ_ACOMP1_EN_LEN (2U)
+#define HBN_IRQ_ACOMP1_EN_MSK \
+ (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)
+#define HBN_IRQ_ACOMP1_EN_UMSK \
+ (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS))
+#define HBN_PIN_WAKEUP_SEL HBN_PIN_WAKEUP_SEL
+#define HBN_PIN_WAKEUP_SEL_POS (24U)
+#define HBN_PIN_WAKEUP_SEL_LEN (3U)
+#define HBN_PIN_WAKEUP_SEL_MSK \
+ (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)
+#define HBN_PIN_WAKEUP_SEL_UMSK \
+ (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS))
+#define HBN_PIN_WAKEUP_EN HBN_PIN_WAKEUP_EN
+#define HBN_PIN_WAKEUP_EN_POS (27U)
+#define HBN_PIN_WAKEUP_EN_LEN (1U)
+#define HBN_PIN_WAKEUP_EN_MSK \
+ (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)
+#define HBN_PIN_WAKEUP_EN_UMSK \
+ (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS))
+
+/* 0x18 : HBN_IRQ_STAT */
+
+#define HBN_IRQ_STAT_OFFSET (0x18)
+#define HBN_IRQ_STAT HBN_IRQ_STAT
+#define HBN_IRQ_STAT_POS (0U)
+#define HBN_IRQ_STAT_LEN (32U)
+#define HBN_IRQ_STAT_MSK (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)
+#define HBN_IRQ_STAT_UMSK \
+ (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS))
+
+/* 0x1C : HBN_IRQ_CLR */
+
+#define HBN_IRQ_CLR_OFFSET (0x1C)
+#define HBN_IRQ_CLR HBN_IRQ_CLR
+#define HBN_IRQ_CLR_POS (0U)
+#define HBN_IRQ_CLR_LEN (32U)
+#define HBN_IRQ_CLR_MSK (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)
+#define HBN_IRQ_CLR_UMSK (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS))
+
+/* 0x20 : HBN_PIR_CFG */
+
+#define HBN_PIR_CFG_OFFSET (0x20)
+#define HBN_PIR_HPF_SEL HBN_PIR_HPF_SEL
+#define HBN_PIR_HPF_SEL_POS (0U)
+#define HBN_PIR_HPF_SEL_LEN (2U)
+#define HBN_PIR_HPF_SEL_MSK \
+ (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)
+#define HBN_PIR_HPF_SEL_UMSK \
+ (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS))
+#define HBN_PIR_LPF_SEL HBN_PIR_LPF_SEL
+#define HBN_PIR_LPF_SEL_POS (2U)
+#define HBN_PIR_LPF_SEL_LEN (1U)
+#define HBN_PIR_LPF_SEL_MSK \
+ (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)
+#define HBN_PIR_LPF_SEL_UMSK \
+ (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS))
+#define HBN_PIR_DIS HBN_PIR_DIS
+#define HBN_PIR_DIS_POS (4U)
+#define HBN_PIR_DIS_LEN (2U)
+#define HBN_PIR_DIS_MSK (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)
+#define HBN_PIR_DIS_UMSK (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS))
+#define HBN_PIR_EN HBN_PIR_EN
+#define HBN_PIR_EN_POS (7U)
+#define HBN_PIR_EN_LEN (1U)
+#define HBN_PIR_EN_MSK (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)
+#define HBN_PIR_EN_UMSK (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS))
+#define HBN_GPADC_CGEN HBN_GPADC_CGEN
+#define HBN_GPADC_CGEN_POS (8U)
+#define HBN_GPADC_CGEN_LEN (1U)
+#define HBN_GPADC_CGEN_MSK \
+ (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)
+#define HBN_GPADC_CGEN_UMSK \
+ (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS))
+#define HBN_GPADC_NOSYNC HBN_GPADC_NOSYNC
+#define HBN_GPADC_NOSYNC_POS (9U)
+#define HBN_GPADC_NOSYNC_LEN (1U)
+#define HBN_GPADC_NOSYNC_MSK \
+ (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)
+#define HBN_GPADC_NOSYNC_UMSK \
+ (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS))
+
+/* 0x24 : HBN_PIR_VTH */
+
+#define HBN_PIR_VTH_OFFSET (0x24)
+#define HBN_PIR_VTH HBN_PIR_VTH
+#define HBN_PIR_VTH_POS (0U)
+#define HBN_PIR_VTH_LEN (14U)
+#define HBN_PIR_VTH_MSK (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)
+#define HBN_PIR_VTH_UMSK (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS))
+
+/* 0x28 : HBN_PIR_INTERVAL */
+
+#define HBN_PIR_INTERVAL_OFFSET (0x28)
+#define HBN_PIR_INTERVAL HBN_PIR_INTERVAL
+#define HBN_PIR_INTERVAL_POS (0U)
+#define HBN_PIR_INTERVAL_LEN (12U)
+#define HBN_PIR_INTERVAL_MSK \
+ (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)
+#define HBN_PIR_INTERVAL_UMSK \
+ (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS))
+
+/* 0x2C : HBN_BOR_CFG */
+
+#define HBN_BOR_CFG_OFFSET (0x2C)
+#define HBN_BOR_SEL HBN_BOR_SEL
+#define HBN_BOR_SEL_POS (0U)
+#define HBN_BOR_SEL_LEN (1U)
+#define HBN_BOR_SEL_MSK (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)
+#define HBN_BOR_SEL_UMSK (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS))
+#define HBN_BOR_VTH HBN_BOR_VTH
+#define HBN_BOR_VTH_POS (1U)
+#define HBN_BOR_VTH_LEN (1U)
+#define HBN_BOR_VTH_MSK (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)
+#define HBN_BOR_VTH_UMSK (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS))
+#define HBN_PU_BOR HBN_PU_BOR
+#define HBN_PU_BOR_POS (2U)
+#define HBN_PU_BOR_LEN (1U)
+#define HBN_PU_BOR_MSK (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)
+#define HBN_PU_BOR_UMSK (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS))
+#define HBN_R_BOR_OUT HBN_R_BOR_OUT
+#define HBN_R_BOR_OUT_POS (3U)
+#define HBN_R_BOR_OUT_LEN (1U)
+#define HBN_R_BOR_OUT_MSK \
+ (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)
+#define HBN_R_BOR_OUT_UMSK \
+ (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS))
+
+/* 0x30 : HBN_GLB */
+
+#define HBN_GLB_OFFSET (0x30)
+#define HBN_ROOT_CLK_SEL HBN_ROOT_CLK_SEL
+#define HBN_ROOT_CLK_SEL_POS (0U)
+#define HBN_ROOT_CLK_SEL_LEN (2U)
+#define HBN_ROOT_CLK_SEL_MSK \
+ (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)
+#define HBN_ROOT_CLK_SEL_UMSK \
+ (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS))
+#define HBN_UART_CLK_SEL HBN_UART_CLK_SEL
+#define HBN_UART_CLK_SEL_POS (2U)
+#define HBN_UART_CLK_SEL_LEN (1U)
+#define HBN_UART_CLK_SEL_MSK \
+ (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)
+#define HBN_UART_CLK_SEL_UMSK \
+ (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS))
+#define HBN_F32K_SEL HBN_F32K_SEL
+#define HBN_F32K_SEL_POS (3U)
+#define HBN_F32K_SEL_LEN (2U)
+#define HBN_F32K_SEL_MSK (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)
+#define HBN_F32K_SEL_UMSK \
+ (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS))
+#define HBN_PU_RC32K HBN_PU_RC32K
+#define HBN_PU_RC32K_POS (5U)
+#define HBN_PU_RC32K_LEN (1U)
+#define HBN_PU_RC32K_MSK (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)
+#define HBN_PU_RC32K_UMSK \
+ (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS))
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON HBN_SW_LDO11SOC_VOUT_SEL_AON
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS (16U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN (4U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK \
+ (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) \
+ << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK \
+ (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) \
+ << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
+#define HBN_SW_LDO11_RT_VOUT_SEL HBN_SW_LDO11_RT_VOUT_SEL
+#define HBN_SW_LDO11_RT_VOUT_SEL_POS (24U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_LEN (4U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_MSK \
+ (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)
+#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK \
+ (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) \
+ << HBN_SW_LDO11_RT_VOUT_SEL_POS))
+#define HBN_SW_LDO11_AON_VOUT_SEL HBN_SW_LDO11_AON_VOUT_SEL
+#define HBN_SW_LDO11_AON_VOUT_SEL_POS (28U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_LEN (4U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_MSK \
+ (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) \
+ << HBN_SW_LDO11_AON_VOUT_SEL_POS)
+#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK \
+ (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) \
+ << HBN_SW_LDO11_AON_VOUT_SEL_POS))
+
+/* 0x34 : HBN_SRAM */
+
+#define HBN_SRAM_OFFSET (0x34)
+#define HBN_RETRAM_RET HBN_RETRAM_RET
+#define HBN_RETRAM_RET_POS (6U)
+#define HBN_RETRAM_RET_LEN (1U)
+#define HBN_RETRAM_RET_MSK \
+ (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)
+#define HBN_RETRAM_RET_UMSK \
+ (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS))
+#define HBN_RETRAM_SLP HBN_RETRAM_SLP
+#define HBN_RETRAM_SLP_POS (7U)
+#define HBN_RETRAM_SLP_LEN (1U)
+#define HBN_RETRAM_SLP_MSK \
+ (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)
+#define HBN_RETRAM_SLP_UMSK \
+ (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS))
+
+/* 0x100 : HBN_RSV0 */
+
+#define HBN_RSV0_OFFSET (0x100)
+#define HBN_RSV0 HBN_RSV0
+#define HBN_RSV0_POS (0U)
+#define HBN_RSV0_LEN (32U)
+#define HBN_RSV0_MSK (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)
+#define HBN_RSV0_UMSK (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS))
+
+/* 0x104 : HBN_RSV1 */
+
+#define HBN_RSV1_OFFSET (0x104)
+#define HBN_RSV1 HBN_RSV1
+#define HBN_RSV1_POS (0U)
+#define HBN_RSV1_LEN (32U)
+#define HBN_RSV1_MSK (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)
+#define HBN_RSV1_UMSK (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS))
+
+/* 0x108 : HBN_RSV2 */
+
+#define HBN_RSV2_OFFSET (0x108)
+#define HBN_RSV2 HBN_RSV2
+#define HBN_RSV2_POS (0U)
+#define HBN_RSV2_LEN (32U)
+#define HBN_RSV2_MSK (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)
+#define HBN_RSV2_UMSK (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS))
+
+/* 0x10C : HBN_RSV3 */
+
+#define HBN_RSV3_OFFSET (0x10C)
+#define HBN_RSV3 HBN_RSV3
+#define HBN_RSV3_POS (0U)
+#define HBN_RSV3_LEN (32U)
+#define HBN_RSV3_MSK (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)
+#define HBN_RSV3_UMSK (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS))
+
+/* 0x200 : rc32k_ctrl0 */
+
+#define HBN_RC32K_CTRL0_OFFSET (0x200)
+#define HBN_RC32K_CAL_DONE HBN_RC32K_CAL_DONE
+#define HBN_RC32K_CAL_DONE_POS (0U)
+#define HBN_RC32K_CAL_DONE_LEN (1U)
+#define HBN_RC32K_CAL_DONE_MSK \
+ (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)
+#define HBN_RC32K_CAL_DONE_UMSK \
+ (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS))
+#define HBN_RC32K_RDY HBN_RC32K_RDY
+#define HBN_RC32K_RDY_POS (1U)
+#define HBN_RC32K_RDY_LEN (1U)
+#define HBN_RC32K_RDY_MSK \
+ (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)
+#define HBN_RC32K_RDY_UMSK \
+ (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS))
+#define HBN_RC32K_CAL_INPROGRESS HBN_RC32K_CAL_INPROGRESS
+#define HBN_RC32K_CAL_INPROGRESS_POS (2U)
+#define HBN_RC32K_CAL_INPROGRESS_LEN (1U)
+#define HBN_RC32K_CAL_INPROGRESS_MSK \
+ (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)
+#define HBN_RC32K_CAL_INPROGRESS_UMSK \
+ (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) \
+ << HBN_RC32K_CAL_INPROGRESS_POS))
+#define HBN_RC32K_CAL_DIV HBN_RC32K_CAL_DIV
+#define HBN_RC32K_CAL_DIV_POS (3U)
+#define HBN_RC32K_CAL_DIV_LEN (2U)
+#define HBN_RC32K_CAL_DIV_MSK \
+ (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)
+#define HBN_RC32K_CAL_DIV_UMSK \
+ (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS))
+#define HBN_RC32K_CAL_PRECHARGE HBN_RC32K_CAL_PRECHARGE
+#define HBN_RC32K_CAL_PRECHARGE_POS (5U)
+#define HBN_RC32K_CAL_PRECHARGE_LEN (1U)
+#define HBN_RC32K_CAL_PRECHARGE_MSK \
+ (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)
+#define HBN_RC32K_CAL_PRECHARGE_UMSK \
+ (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) \
+ << HBN_RC32K_CAL_PRECHARGE_POS))
+#define HBN_RC32K_DIG_CODE_FR_CAL HBN_RC32K_DIG_CODE_FR_CAL
+#define HBN_RC32K_DIG_CODE_FR_CAL_POS (6U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_LEN (10U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_MSK \
+ (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) \
+ << HBN_RC32K_DIG_CODE_FR_CAL_POS)
+#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK \
+ (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) \
+ << HBN_RC32K_DIG_CODE_FR_CAL_POS))
+#define HBN_RC32K_VREF_DLY HBN_RC32K_VREF_DLY
+#define HBN_RC32K_VREF_DLY_POS (16U)
+#define HBN_RC32K_VREF_DLY_LEN (2U)
+#define HBN_RC32K_VREF_DLY_MSK \
+ (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)
+#define HBN_RC32K_VREF_DLY_UMSK \
+ (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS))
+#define HBN_RC32K_ALLOW_CAL HBN_RC32K_ALLOW_CAL
+#define HBN_RC32K_ALLOW_CAL_POS (18U)
+#define HBN_RC32K_ALLOW_CAL_LEN (1U)
+#define HBN_RC32K_ALLOW_CAL_MSK \
+ (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)
+#define HBN_RC32K_ALLOW_CAL_UMSK \
+ (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS))
+#define HBN_RC32K_EXT_CODE_EN HBN_RC32K_EXT_CODE_EN
+#define HBN_RC32K_EXT_CODE_EN_POS (19U)
+#define HBN_RC32K_EXT_CODE_EN_LEN (1U)
+#define HBN_RC32K_EXT_CODE_EN_MSK \
+ (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)
+#define HBN_RC32K_EXT_CODE_EN_UMSK \
+ (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS))
+#define HBN_RC32K_CAL_EN HBN_RC32K_CAL_EN
+#define HBN_RC32K_CAL_EN_POS (20U)
+#define HBN_RC32K_CAL_EN_LEN (1U)
+#define HBN_RC32K_CAL_EN_MSK \
+ (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)
+#define HBN_RC32K_CAL_EN_UMSK \
+ (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS))
+#define HBN_RC32K_CODE_FR_EXT HBN_RC32K_CODE_FR_EXT
+#define HBN_RC32K_CODE_FR_EXT_POS (22U)
+#define HBN_RC32K_CODE_FR_EXT_LEN (10U)
+#define HBN_RC32K_CODE_FR_EXT_MSK \
+ (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)
+#define HBN_RC32K_CODE_FR_EXT_UMSK \
+ (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS))
+
+/* 0x204 : xtal32k */
+
+#define HBN_XTAL32K_OFFSET (0x204)
+#define HBN_XTAL32K_EXT_SEL HBN_XTAL32K_EXT_SEL
+#define HBN_XTAL32K_EXT_SEL_POS (2U)
+#define HBN_XTAL32K_EXT_SEL_LEN (1U)
+#define HBN_XTAL32K_EXT_SEL_MSK \
+ (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)
+#define HBN_XTAL32K_EXT_SEL_UMSK \
+ (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS))
+#define HBN_XTAL32K_AMP_CTRL HBN_XTAL32K_AMP_CTRL
+#define HBN_XTAL32K_AMP_CTRL_POS (3U)
+#define HBN_XTAL32K_AMP_CTRL_LEN (2U)
+#define HBN_XTAL32K_AMP_CTRL_MSK \
+ (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)
+#define HBN_XTAL32K_AMP_CTRL_UMSK \
+ (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS))
+#define HBN_XTAL32K_REG HBN_XTAL32K_REG
+#define HBN_XTAL32K_REG_POS (5U)
+#define HBN_XTAL32K_REG_LEN (2U)
+#define HBN_XTAL32K_REG_MSK \
+ (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)
+#define HBN_XTAL32K_REG_UMSK \
+ (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS))
+#define HBN_XTAL32K_OUTBUF_STRE HBN_XTAL32K_OUTBUF_STRE
+#define HBN_XTAL32K_OUTBUF_STRE_POS (7U)
+#define HBN_XTAL32K_OUTBUF_STRE_LEN (1U)
+#define HBN_XTAL32K_OUTBUF_STRE_MSK \
+ (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)
+#define HBN_XTAL32K_OUTBUF_STRE_UMSK \
+ (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) \
+ << HBN_XTAL32K_OUTBUF_STRE_POS))
+#define HBN_XTAL32K_OTF_SHORT HBN_XTAL32K_OTF_SHORT
+#define HBN_XTAL32K_OTF_SHORT_POS (8U)
+#define HBN_XTAL32K_OTF_SHORT_LEN (1U)
+#define HBN_XTAL32K_OTF_SHORT_MSK \
+ (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)
+#define HBN_XTAL32K_OTF_SHORT_UMSK \
+ (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS))
+#define HBN_XTAL32K_INV_STRE HBN_XTAL32K_INV_STRE
+#define HBN_XTAL32K_INV_STRE_POS (9U)
+#define HBN_XTAL32K_INV_STRE_LEN (2U)
+#define HBN_XTAL32K_INV_STRE_MSK \
+ (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)
+#define HBN_XTAL32K_INV_STRE_UMSK \
+ (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS))
+#define HBN_XTAL32K_CAPBANK HBN_XTAL32K_CAPBANK
+#define HBN_XTAL32K_CAPBANK_POS (11U)
+#define HBN_XTAL32K_CAPBANK_LEN (6U)
+#define HBN_XTAL32K_CAPBANK_MSK \
+ (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)
+#define HBN_XTAL32K_CAPBANK_UMSK \
+ (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS))
+#define HBN_XTAL32K_AC_CAP_SHORT HBN_XTAL32K_AC_CAP_SHORT
+#define HBN_XTAL32K_AC_CAP_SHORT_POS (17U)
+#define HBN_XTAL32K_AC_CAP_SHORT_LEN (1U)
+#define HBN_XTAL32K_AC_CAP_SHORT_MSK \
+ (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)
+#define HBN_XTAL32K_AC_CAP_SHORT_UMSK \
+ (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) \
+ << HBN_XTAL32K_AC_CAP_SHORT_POS))
+#define HBN_PU_XTAL32K_BUF HBN_PU_XTAL32K_BUF
+#define HBN_PU_XTAL32K_BUF_POS (18U)
+#define HBN_PU_XTAL32K_BUF_LEN (1U)
+#define HBN_PU_XTAL32K_BUF_MSK \
+ (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)
+#define HBN_PU_XTAL32K_BUF_UMSK \
+ (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS))
+#define HBN_PU_XTAL32K HBN_PU_XTAL32K
+#define HBN_PU_XTAL32K_POS (19U)
+#define HBN_PU_XTAL32K_LEN (1U)
+#define HBN_PU_XTAL32K_MSK \
+ (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)
+#define HBN_PU_XTAL32K_UMSK \
+ (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS))
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+/* HBN UART clock type definition */
+
+enum hbn_uart_clk_type_e
+{
+ HBN_UART_CLK_FCLK = 0, /* Select FCLK as UART clock */
+ HBN_UART_CLK_160M /* Select 160M as UART clock */
+};
+
+struct hbn_reg_s
+{
+ /* 0x0 : HBN_CTL */
+
+ union
+ {
+ struct
+ {
+ uint32_t rtc_ctl : 7; /* [ 6: 0], r/w, 0x0 */
+ uint32_t hbn_mode : 1; /* [ 7], w, 0x0 */
+ uint32_t trap_mode : 1; /* [ 8], r, 0x0 */
+ uint32_t pwrdn_hbn_core : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */
+ uint32_t pwrdn_hbn_rtc : 1; /* [ 11], r/w, 0x0 */
+ uint32_t sw_rst : 1; /* [ 12], r/w, 0x0 */
+ uint32_t hbn_dis_pwr_off_ldo11 : 1; /* [ 13], r/w, 0x0 */
+ uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [ 14], r/w, 0x0 */
+ uint32_t hbn_ldo11_rt_vout_sel : 4; /* [18:15], r/w, 0xa */
+ uint32_t hbn_ldo11_aon_vout_sel : 4; /* [22:19], r/w, 0xa */
+ uint32_t pu_dcdc18_aon : 1; /* [ 23], r/w, 0x1 */
+ uint32_t rtc_dly_option : 1; /* [ 24], r/w, 0x0 */
+ uint32_t pwr_on_option : 1; /* [ 25], r/w, 0x0 */
+ uint32_t sram_slp_option : 1; /* [ 26], r/w, 0x0 */
+ uint32_t sram_slp : 1; /* [ 27], r, 0x0 */
+ uint32_t hbn_state : 4; /* [31:28], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_CTL;
+
+ /* 0x4 : HBN_TIME_L */
+
+ union
+ {
+ struct
+ {
+ uint32_t hbn_time_l : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_TIME_L;
+
+ /* 0x8 : HBN_TIME_H */
+
+ union
+ {
+ struct
+ {
+ uint32_t hbn_time_h : 8; /* [ 7: 0], r/w, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_TIME_H;
+
+ /* 0xC : RTC_TIME_L */
+
+ union
+ {
+ struct
+ {
+ uint32_t rtc_time_latch_l : 32; /* [31: 0], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } RTC_TIME_L;
+
+ /* 0x10 : RTC_TIME_H */
+
+ union
+ {
+ struct
+ {
+ uint32_t rtc_time_latch_h : 8; /* [ 7: 0], r, 0x0 */
+ uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */
+ uint32_t rtc_time_latch : 1; /* [ 31], w, 0x0 */
+ } bf;
+ uint32_t word;
+ } RTC_TIME_H;
+
+ /* 0x14 : HBN_IRQ_MODE */
+
+ union
+ {
+ struct
+ {
+ uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0], r/w, 0x5 */
+ uint32_t hbn_pin_wakeup_mask : 2; /* [ 4: 3], r/w, 0x0 */
+ uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */
+ uint32_t reg_aon_pad_ie_smt : 1; /* [ 8], r/w, 0x1 */
+ uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */
+ uint32_t reg_en_hw_pu_pd : 1; /* [ 16], r/w, 0x1 */
+ uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */
+ uint32_t irq_bor_en : 1; /* [ 18], r/w, 0x0 */
+ uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
+ uint32_t irq_acomp0_en : 2; /* [21:20], r/w, 0x0 */
+ uint32_t irq_acomp1_en : 2; /* [23:22], r/w, 0x0 */
+ uint32_t pin_wakeup_sel : 3; /* [26:24], r/w, 0x3 */
+ uint32_t pin_wakeup_en : 1; /* [ 27], r/w, 0x0 */
+ uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_IRQ_MODE;
+
+ /* 0x18 : HBN_IRQ_STAT */
+
+ union
+ {
+ struct
+ {
+ uint32_t irq_stat : 32; /* [31: 0], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_IRQ_STAT;
+
+ /* 0x1C : HBN_IRQ_CLR */
+
+ union
+ {
+ struct
+ {
+ uint32_t irq_clr : 32; /* [31: 0], w, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_IRQ_CLR;
+
+ /* 0x20 : HBN_PIR_CFG */
+
+ union
+ {
+ struct
+ {
+ uint32_t pir_hpf_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t pir_lpf_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t pir_dis : 2; /* [ 5: 4], r/w, 0x0 */
+ uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t pir_en : 1; /* [ 7], r/w, 0x0 */
+ uint32_t gpadc_cgen : 1; /* [ 8], r/w, 0x0 */
+ uint32_t gpadc_nosync : 1; /* [ 9], r/w, 0x0 */
+ uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_PIR_CFG;
+
+ /* 0x24 : HBN_PIR_VTH */
+
+ union
+ {
+ struct
+ {
+ uint32_t pir_vth : 14; /* [13: 0], r/w, 0x3ff */
+ uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_PIR_VTH;
+
+ /* 0x28 : HBN_PIR_INTERVAL */
+
+ union
+ {
+ struct
+ {
+ uint32_t pir_interval : 12; /* [11: 0], r/w, 0xa3d */
+ uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_PIR_INTERVAL;
+
+ /* 0x2C : HBN_BOR_CFG */
+
+ union
+ {
+ struct
+ {
+ uint32_t bor_sel : 1; /* [ 0], r/w, 0x0 */
+ uint32_t bor_vth : 1; /* [ 1], r/w, 0x1 */
+ uint32_t pu_bor : 1; /* [ 2], r/w, 0x0 */
+ uint32_t r_bor_out : 1; /* [ 3], r, 0x0 */
+ uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_BOR_CFG;
+
+ /* 0x30 : HBN_GLB */
+
+ union
+ {
+ struct
+ {
+ uint32_t hbn_root_clk_sel : 2; /* [ 1: 0], r/w, 0x0 */
+ uint32_t hbn_uart_clk_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t hbn_f32k_sel : 2; /* [ 4: 3], r/w, 0x0 */
+ uint32_t hbn_pu_rc32k : 1; /* [ 5], r/w, 0x1 */
+ uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
+ uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16], r/w, 0xa */
+ uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */
+ uint32_t sw_ldo11_rt_vout_sel : 4; /* [27:24], r/w, 0xa */
+ uint32_t sw_ldo11_aon_vout_sel : 4; /* [31:28], r/w, 0xa */
+ } bf;
+ uint32_t word;
+ } HBN_GLB;
+
+ /* 0x34 : HBN_SRAM */
+
+ union
+ {
+ struct
+ {
+ uint32_t reserved_0_5 : 6; /* [ 5: 0], rsvd, 0x0 */
+ uint32_t retram_ret : 1; /* [ 6], r/w, 0x0 */
+ uint32_t retram_slp : 1; /* [ 7], r/w, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_SRAM;
+
+ /* 0x38 reserved */
+
+ uint8_t reserved_0x38[200];
+
+ /* 0x100 : HBN_RSV0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t HBN_RSV0 : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_RSV0;
+
+ /* 0x104 : HBN_RSV1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t HBN_RSV1 : 32; /* [31: 0], r/w, 0xffffffffL */
+ } bf;
+ uint32_t word;
+ } HBN_RSV1;
+
+ /* 0x108 : HBN_RSV2 */
+
+ union
+ {
+ struct
+ {
+ uint32_t HBN_RSV2 : 32; /* [31: 0], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } HBN_RSV2;
+
+ /* 0x10C : HBN_RSV3 */
+
+ union
+ {
+ struct
+ {
+ uint32_t HBN_RSV3 : 32; /* [31: 0], r/w, 0xffffffffL */
+ } bf;
+ uint32_t word;
+ } HBN_RSV3;
+
+ /* 0x110 reserved */
+
+ uint8_t reserved_0x110[240];
+
+ /* 0x200 : rc32k_ctrl0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t rc32k_cal_done : 1; /* [ 0], r, 0x1 */
+ uint32_t rc32k_rdy : 1; /* [ 1], r, 0x1 */
+ uint32_t rc32k_cal_inprogress : 1; /* [ 2], r, 0x0 */
+ uint32_t rc32k_cal_div : 2; /* [ 4: 3], r/w, 0x3 */
+ uint32_t rc32k_cal_precharge : 1; /* [ 5], r, 0x0 */
+ uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6], r, 0x200 */
+ uint32_t rc32k_vref_dly : 2; /* [17:16], r/w, 0x0 */
+ uint32_t rc32k_allow_cal : 1; /* [ 18], r/w, 0x0 */
+ uint32_t rc32k_ext_code_en : 1; /* [ 19], r/w, 0x1 */
+ uint32_t rc32k_cal_en : 1; /* [ 20], r/w, 0x0 */
+ uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */
+ uint32_t rc32k_code_fr_ext : 10; /* [31:22], r/w, 0x140 */
+ } bf;
+ uint32_t word;
+ } rc32k_ctrl0;
+
+ /* 0x204 : xtal32k */
+
+ union
+ {
+ struct
+ {
+ uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
+ uint32_t xtal32k_ext_sel : 1; /* [ 2], r/w, 0x0 */
+ uint32_t xtal32k_amp_ctrl : 2; /* [ 4: 3], r/w, 0x1 */
+ uint32_t xtal32k_reg : 2; /* [ 6: 5], r/w, 0x1 */
+ uint32_t xtal32k_outbuf_stre : 1; /* [ 7], r/w, 0x0 */
+ uint32_t xtal32k_otf_short : 1; /* [ 8], r/w, 0x0 */
+ uint32_t xtal32k_inv_stre : 2; /* [10: 9], r/w, 0x1 */
+ uint32_t xtal32k_capbank : 6; /* [16:11], r/w, 0x20 */
+ uint32_t xtal32k_ac_cap_short : 1; /* [ 17], r/w, 0x1 */
+ uint32_t pu_xtal32k_buf : 1; /* [ 18], r/w, 0x1 */
+ uint32_t pu_xtal32k : 1; /* [ 19], r/w, 0x1 */
+ uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } xtal32k;
+};
+
+typedef volatile struct hbn_reg hbn_reg_t;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: <Inline function name>
+ *
+ * Description:
+ * Description of the operation of the inline function.
+ *
+ * Input Parameters:
+ * A list of input parameters, one-per-line, appears here along with a
+ * description of each input parameter.
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: hbn_set_uart_clk_sel
+ *
+ * Description:
+ * Select uart clock source.
+ *
+ * Input Parameters:
+ * clk_sel: uart clock type selection
+ *
+ * Returned Value:
+ * Description of the value returned by this function (if any),
+ * including an enumeration of all possible error values.
+ *
+ * Assumptions/Limitations:
+ * Anything else that one might need to know to use this function.
+ *
+ ****************************************************************************/
+
+EXTERN void hbn_set_uart_clk_sel(enum hbn_uart_clk_type_e clk_sel);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_HBN_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_timer.h b/arch/risc-v/src/bl602/hardware/bl602_timer.h
new file mode 100644
index 0000000000..f71755895b
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_timer.h
@@ -0,0 +1,664 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_timer.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_TIMER_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_TIMER_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hardware/bl602_common.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* 0x0 : TCCR */
+
+#define TIMER_TCCR_OFFSET (0x0)
+#define TIMER_CS_1 TIMER_CS_1
+#define TIMER_CS_1_POS (2U)
+#define TIMER_CS_1_LEN (2U)
+#define TIMER_CS_1_MSK (((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS)
+#define TIMER_CS_1_UMSK (~(((1U << TIMER_CS_1_LEN) - 1) << TIMER_CS_1_POS))
+#define TIMER_CS_2 TIMER_CS_2
+#define TIMER_CS_2_POS (5U)
+#define TIMER_CS_2_LEN (2U)
+#define TIMER_CS_2_MSK (((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS)
+#define TIMER_CS_2_UMSK (~(((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS))
+#define TIMER_CS_WDT TIMER_CS_WDT
+#define TIMER_CS_WDT_POS (8U)
+#define TIMER_CS_WDT_LEN (2U)
+#define TIMER_CS_WDT_MSK (((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS)
+#define TIMER_CS_WDT_UMSK \
+ (~(((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS))
+
+/* 0x10 : TMR2_0 */
+
+#define TIMER_TMR2_0_OFFSET (0x10)
+#define TIMER_TMR TIMER_TMR
+#define TIMER_TMR_POS (0U)
+#define TIMER_TMR_LEN (32U)
+#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x14 : TMR2_1 */
+
+#define TIMER_TMR2_1_OFFSET (0x14)
+#define TIMER_TMR TIMER_TMR
+#define TIMER_TMR_POS (0U)
+#define TIMER_TMR_LEN (32U)
+#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x18 : TMR2_2 */
+
+#define TIMER_TMR2_2_OFFSET (0x18)
+#define TIMER_TMR TIMER_TMR
+#define TIMER_TMR_POS (0U)
+#define TIMER_TMR_LEN (32U)
+#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x1C : TMR3_0 */
+
+#define TIMER_TMR3_0_OFFSET (0x1C)
+#define TIMER_TMR TIMER_TMR
+#define TIMER_TMR_POS (0U)
+#define TIMER_TMR_LEN (32U)
+#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x20 : TMR3_1 */
+
+#define TIMER_TMR3_1_OFFSET (0x20)
+#define TIMER_TMR TIMER_TMR
+#define TIMER_TMR_POS (0U)
+#define TIMER_TMR_LEN (32U)
+#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x24 : TMR3_2 */
+
+#define TIMER_TMR3_2_OFFSET (0x24)
+#define TIMER_TMR TIMER_TMR
+#define TIMER_TMR_POS (0U)
+#define TIMER_TMR_LEN (32U)
+#define TIMER_TMR_MSK (((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS)
+#define TIMER_TMR_UMSK (~(((1U << TIMER_TMR_LEN) - 1) << TIMER_TMR_POS))
+
+/* 0x2C : TCR2 */
+
+#define TIMER_TCR2_OFFSET (0x2C)
+#define TIMER_TCR TIMER_TCR
+#define TIMER_TCR_POS (0U)
+#define TIMER_TCR_LEN (32U)
+#define TIMER_TCR_MSK (((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS)
+#define TIMER_TCR_UMSK (~(((1U << TIMER_TCR_LEN) - 1) << TIMER_TCR_POS))
+
+/* 0x30 : TCR3 */
+
+#define TIMER_TCR3_OFFSET (0x30)
+#define TIMER_TCR3_COUNTER TIMER_TCR3_COUNTER
+#define TIMER_TCR3_COUNTER_POS (0U)
+#define TIMER_TCR3_COUNTER_LEN (32U)
+#define TIMER_TCR3_COUNTER_MSK \
+ (((1U << TIMER_TCR3_COUNTER_LEN) - 1) << TIMER_TCR3_COUNTER_POS)
+#define TIMER_TCR3_COUNTER_UMSK \
+ (~(((1U << TIMER_TCR3_COUNTER_LEN) - 1) << TIMER_TCR3_COUNTER_POS))
+
+/* 0x38 : TMSR2 */
+
+#define TIMER_TMSR2_OFFSET (0x38)
+#define TIMER_TMSR_0 TIMER_TMSR_0
+#define TIMER_TMSR_0_POS (0U)
+#define TIMER_TMSR_0_LEN (1U)
+#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
+#define TIMER_TMSR_0_UMSK \
+ (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
+#define TIMER_TMSR_1 TIMER_TMSR_1
+#define TIMER_TMSR_1_POS (1U)
+#define TIMER_TMSR_1_LEN (1U)
+#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
+#define TIMER_TMSR_1_UMSK \
+ (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
+#define TIMER_TMSR_2 TIMER_TMSR_2
+#define TIMER_TMSR_2_POS (2U)
+#define TIMER_TMSR_2_LEN (1U)
+#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
+#define TIMER_TMSR_2_UMSK \
+ (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))
+
+/* 0x3C : TMSR3 */
+
+#define TIMER_TMSR3_OFFSET (0x3C)
+#define TIMER_TMSR_0 TIMER_TMSR_0
+#define TIMER_TMSR_0_POS (0U)
+#define TIMER_TMSR_0_LEN (1U)
+#define TIMER_TMSR_0_MSK (((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS)
+#define TIMER_TMSR_0_UMSK \
+ (~(((1U << TIMER_TMSR_0_LEN) - 1) << TIMER_TMSR_0_POS))
+#define TIMER_TMSR_1 TIMER_TMSR_1
+#define TIMER_TMSR_1_POS (1U)
+#define TIMER_TMSR_1_LEN (1U)
+#define TIMER_TMSR_1_MSK (((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS)
+#define TIMER_TMSR_1_UMSK \
+ (~(((1U << TIMER_TMSR_1_LEN) - 1) << TIMER_TMSR_1_POS))
+#define TIMER_TMSR_2 TIMER_TMSR_2
+#define TIMER_TMSR_2_POS (2U)
+#define TIMER_TMSR_2_LEN (1U)
+#define TIMER_TMSR_2_MSK (((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS)
+#define TIMER_TMSR_2_UMSK \
+ (~(((1U << TIMER_TMSR_2_LEN) - 1) << TIMER_TMSR_2_POS))
+
+/* 0x44 : TIER2 */
+
+#define TIMER_TIER2_OFFSET (0x44)
+#define TIMER_TIER_0 TIMER_TIER_0
+#define TIMER_TIER_0_POS (0U)
+#define TIMER_TIER_0_LEN (1U)
+#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
+#define TIMER_TIER_0_UMSK \
+ (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
+#define TIMER_TIER_1 TIMER_TIER_1
+#define TIMER_TIER_1_POS (1U)
+#define TIMER_TIER_1_LEN (1U)
+#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
+#define TIMER_TIER_1_UMSK \
+ (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
+#define TIMER_TIER_2 TIMER_TIER_2
+#define TIMER_TIER_2_POS (2U)
+#define TIMER_TIER_2_LEN (1U)
+#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
+#define TIMER_TIER_2_UMSK \
+ (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))
+
+/* 0x48 : TIER3 */
+
+#define TIMER_TIER3_OFFSET (0x48)
+#define TIMER_TIER_0 TIMER_TIER_0
+#define TIMER_TIER_0_POS (0U)
+#define TIMER_TIER_0_LEN (1U)
+#define TIMER_TIER_0_MSK (((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS)
+#define TIMER_TIER_0_UMSK \
+ (~(((1U << TIMER_TIER_0_LEN) - 1) << TIMER_TIER_0_POS))
+#define TIMER_TIER_1 TIMER_TIER_1
+#define TIMER_TIER_1_POS (1U)
+#define TIMER_TIER_1_LEN (1U)
+#define TIMER_TIER_1_MSK (((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS)
+#define TIMER_TIER_1_UMSK \
+ (~(((1U << TIMER_TIER_1_LEN) - 1) << TIMER_TIER_1_POS))
+#define TIMER_TIER_2 TIMER_TIER_2
+#define TIMER_TIER_2_POS (2U)
+#define TIMER_TIER_2_LEN (1U)
+#define TIMER_TIER_2_MSK (((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS)
+#define TIMER_TIER_2_UMSK \
+ (~(((1U << TIMER_TIER_2_LEN) - 1) << TIMER_TIER_2_POS))
+
+/* 0x50 : TPLVR2 */
+
+#define TIMER_TPLVR2_OFFSET (0x50)
+#define TIMER_TPLVR TIMER_TPLVR
+#define TIMER_TPLVR_POS (0U)
+#define TIMER_TPLVR_LEN (32U)
+#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
+#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))
+
+/* 0x54 : TPLVR3 */
+#define TIMER_TPLVR3_OFFSET (0x54)
+#define TIMER_TPLVR TIMER_TPLVR
+#define TIMER_TPLVR_POS (0U)
+#define TIMER_TPLVR_LEN (32U)
+#define TIMER_TPLVR_MSK (((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS)
+#define TIMER_TPLVR_UMSK (~(((1U << TIMER_TPLVR_LEN) - 1) << TIMER_TPLVR_POS))
+
+/* 0x5C : TPLCR2 */
+
+#define TIMER_TPLCR2_OFFSET (0x5C)
+#define TIMER_TPLCR TIMER_TPLCR
+#define TIMER_TPLCR_POS (0U)
+#define TIMER_TPLCR_LEN (2U)
+#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
+#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))
+
+/* 0x60 : TPLCR3 */
+
+#define TIMER_TPLCR3_OFFSET (0x60)
+#define TIMER_TPLCR TIMER_TPLCR
+#define TIMER_TPLCR_POS (0U)
+#define TIMER_TPLCR_LEN (2U)
+#define TIMER_TPLCR_MSK (((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS)
+#define TIMER_TPLCR_UMSK (~(((1U << TIMER_TPLCR_LEN) - 1) << TIMER_TPLCR_POS))
+
+/* 0x64 : WMER */
+
+#define TIMER_WMER_OFFSET (0x64)
+#define TIMER_WE TIMER_WE
+#define TIMER_WE_POS (0U)
+#define TIMER_WE_LEN (1U)
+#define TIMER_WE_MSK (((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS)
+#define TIMER_WE_UMSK (~(((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS))
+#define TIMER_WRIE TIMER_WRIE
+#define TIMER_WRIE_POS (1U)
+#define TIMER_WRIE_LEN (1U)
+#define TIMER_WRIE_MSK (((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS)
+#define TIMER_WRIE_UMSK (~(((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS))
+
+/* 0x68 : WMR */
+
+#define TIMER_WMR_OFFSET (0x68)
+#define TIMER_WMR TIMER_WMR
+#define TIMER_WMR_POS (0U)
+#define TIMER_WMR_LEN (16U)
+#define TIMER_WMR_MSK (((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS)
+#define TIMER_WMR_UMSK (~(((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS))
+
+/* 0x6C : WVR */
+
+#define TIMER_WVR_OFFSET (0x6C)
+#define TIMER_WVR TIMER_WVR
+#define TIMER_WVR_POS (0U)
+#define TIMER_WVR_LEN (16U)
+#define TIMER_WVR_MSK (((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS)
+#define TIMER_WVR_UMSK (~(((1U << TIMER_WVR_LEN) - 1) << TIMER_WVR_POS))
+
+/* 0x70 : WSR */
+
+#define TIMER_WSR_OFFSET (0x70)
+#define TIMER_WTS TIMER_WTS
+#define TIMER_WTS_POS (0U)
+#define TIMER_WTS_LEN (1U)
+#define TIMER_WTS_MSK (((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS)
+#define TIMER_WTS_UMSK (~(((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS))
+
+/* 0x78 : TICR2 */
+
+#define TIMER_TICR2_OFFSET (0x78)
+#define TIMER_TCLR_0 TIMER_TCLR_0
+#define TIMER_TCLR_0_POS (0U)
+#define TIMER_TCLR_0_LEN (1U)
+#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
+#define TIMER_TCLR_0_UMSK \
+ (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
+#define TIMER_TCLR_1 TIMER_TCLR_1
+#define TIMER_TCLR_1_POS (1U)
+#define TIMER_TCLR_1_LEN (1U)
+#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
+#define TIMER_TCLR_1_UMSK \
+ (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
+#define TIMER_TCLR_2 TIMER_TCLR_2
+#define TIMER_TCLR_2_POS (2U)
+#define TIMER_TCLR_2_LEN (1U)
+#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
+#define TIMER_TCLR_2_UMSK \
+ (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))
+
+/* 0x7C : TICR3 */
+
+#define TIMER_TICR3_OFFSET (0x7C)
+#define TIMER_TCLR_0 TIMER_TCLR_0
+#define TIMER_TCLR_0_POS (0U)
+#define TIMER_TCLR_0_LEN (1U)
+#define TIMER_TCLR_0_MSK (((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS)
+#define TIMER_TCLR_0_UMSK \
+ (~(((1U << TIMER_TCLR_0_LEN) - 1) << TIMER_TCLR_0_POS))
+#define TIMER_TCLR_1 TIMER_TCLR_1
+#define TIMER_TCLR_1_POS (1U)
+#define TIMER_TCLR_1_LEN (1U)
+#define TIMER_TCLR_1_MSK (((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS)
+#define TIMER_TCLR_1_UMSK \
+ (~(((1U << TIMER_TCLR_1_LEN) - 1) << TIMER_TCLR_1_POS))
+#define TIMER_TCLR_2 TIMER_TCLR_2
+#define TIMER_TCLR_2_POS (2U)
+#define TIMER_TCLR_2_LEN (1U)
+#define TIMER_TCLR_2_MSK (((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS)
+#define TIMER_TCLR_2_UMSK \
+ (~(((1U << TIMER_TCLR_2_LEN) - 1) << TIMER_TCLR_2_POS))
+
+/* 0x80 : WICR */
+
+#define TIMER_WICR_OFFSET (0x80)
+#define TIMER_WICLR TIMER_WICLR
+#define TIMER_WICLR_POS (0U)
+#define TIMER_WICLR_LEN (1U)
+#define TIMER_WICLR_MSK (((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS)
+#define TIMER_WICLR_UMSK (~(((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS))
+
+/* 0x84 : TCER */
+
+#define TIMER_TCER_OFFSET (0x84)
+#define TIMER2_EN TIMER2_EN
+#define TIMER2_EN_POS (1U)
+#define TIMER2_EN_LEN (1U)
+#define TIMER2_EN_MSK (((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS)
+#define TIMER2_EN_UMSK (~(((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS))
+#define TIMER3_EN TIMER3_EN
+#define TIMER3_EN_POS (2U)
+#define TIMER3_EN_LEN (1U)
+#define TIMER3_EN_MSK (((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS)
+#define TIMER3_EN_UMSK (~(((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS))
+
+/* 0x88 : TCMR */
+
+#define TIMER_TCMR_OFFSET (0x88)
+#define TIMER2_MODE TIMER2_MODE
+#define TIMER2_MODE_POS (1U)
+#define TIMER2_MODE_LEN (1U)
+#define TIMER2_MODE_MSK (((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS)
+#define TIMER2_MODE_UMSK (~(((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS))
+#define TIMER3_MODE TIMER3_MODE
+#define TIMER3_MODE_POS (2U)
+#define TIMER3_MODE_LEN (1U)
+#define TIMER3_MODE_MSK (((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS)
+#define TIMER3_MODE_UMSK (~(((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS))
+
+/* 0x90 : TILR2 */
+
+#define TIMER_TILR2_OFFSET (0x90)
+#define TIMER_TILR_0 TIMER_TILR_0
+#define TIMER_TILR_0_POS (0U)
+#define TIMER_TILR_0_LEN (1U)
+#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
+#define TIMER_TILR_0_UMSK \
+ (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
+#define TIMER_TILR_1 TIMER_TILR_1
+#define TIMER_TILR_1_POS (1U)
+#define TIMER_TILR_1_LEN (1U)
+#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
+#define TIMER_TILR_1_UMSK \
+ (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
+#define TIMER_TILR_2 TIMER_TILR_2
+#define TIMER_TILR_2_POS (2U)
+#define TIMER_TILR_2_LEN (1U)
+#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
+#define TIMER_TILR_2_UMSK \
+ (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))
+
+/* 0x94 : TILR3 */
+
+#define TIMER_TILR3_OFFSET (0x94)
+#define TIMER_TILR_0 TIMER_TILR_0
+#define TIMER_TILR_0_POS (0U)
+#define TIMER_TILR_0_LEN (1U)
+#define TIMER_TILR_0_MSK (((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS)
+#define TIMER_TILR_0_UMSK \
+ (~(((1U << TIMER_TILR_0_LEN) - 1) << TIMER_TILR_0_POS))
+#define TIMER_TILR_1 TIMER_TILR_1
+#define TIMER_TILR_1_POS (1U)
+#define TIMER_TILR_1_LEN (1U)
+#define TIMER_TILR_1_MSK (((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS)
+#define TIMER_TILR_1_UMSK \
+ (~(((1U << TIMER_TILR_1_LEN) - 1) << TIMER_TILR_1_POS))
+#define TIMER_TILR_2 TIMER_TILR_2
+#define TIMER_TILR_2_POS (2U)
+#define TIMER_TILR_2_LEN (1U)
+#define TIMER_TILR_2_MSK (((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS)
+#define TIMER_TILR_2_UMSK \
+ (~(((1U << TIMER_TILR_2_LEN) - 1) << TIMER_TILR_2_POS))
+
+/* 0x98 : WCR */
+
+#define TIMER_WCR_OFFSET (0x98)
+#define TIMER_WCR TIMER_WCR
+#define TIMER_WCR_POS (0U)
+#define TIMER_WCR_LEN (1U)
+#define TIMER_WCR_MSK (((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS)
+#define TIMER_WCR_UMSK (~(((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS))
+
+/* 0x9C : WFAR */
+
+#define TIMER_WFAR_OFFSET (0x9C)
+#define TIMER_WFAR TIMER_WFAR
+#define TIMER_WFAR_POS (0U)
+#define TIMER_WFAR_LEN (16U)
+#define TIMER_WFAR_MSK (((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS)
+#define TIMER_WFAR_UMSK (~(((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS))
+
+/* 0xA0 : WSAR */
+
+#define TIMER_WSAR_OFFSET (0xA0)
+#define TIMER_WSAR TIMER_WSAR
+#define TIMER_WSAR_POS (0U)
+#define TIMER_WSAR_LEN (16U)
+#define TIMER_WSAR_MSK (((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS)
+#define TIMER_WSAR_UMSK (~(((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS))
+
+/* 0xA8 : TCVWR2 */
+
+#define TIMER_TCVWR2_OFFSET (0xA8)
+#define TIMER_TCVWR TIMER_TCVWR
+#define TIMER_TCVWR_POS (0U)
+#define TIMER_TCVWR_LEN (32U)
+#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
+#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))
+
+/* 0xAC : TCVWR3 */
+
+#define TIMER_TCVWR3_OFFSET (0xAC)
+#define TIMER_TCVWR TIMER_TCVWR
+#define TIMER_TCVWR_POS (0U)
+#define TIMER_TCVWR_LEN (32U)
+#define TIMER_TCVWR_MSK (((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS)
+#define TIMER_TCVWR_UMSK (~(((1U << TIMER_TCVWR_LEN) - 1) << TIMER_TCVWR_POS))
+
+/* 0xB4 : TCVSYN2 */
+
+#define TIMER_TCVSYN2_OFFSET (0xB4)
+#define TIMER_TCVSYN2 TIMER_TCVSYN2
+#define TIMER_TCVSYN2_POS (0U)
+#define TIMER_TCVSYN2_LEN (32U)
+#define TIMER_TCVSYN2_MSK \
+ (((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS)
+#define TIMER_TCVSYN2_UMSK \
+ (~(((1U << TIMER_TCVSYN2_LEN) - 1) << TIMER_TCVSYN2_POS))
+
+/* 0xB8 : TCVSYN3 */
+
+#define TIMER_TCVSYN3_OFFSET (0xB8)
+#define TIMER_TCVSYN3 TIMER_TCVSYN3
+#define TIMER_TCVSYN3_POS (0U)
+#define TIMER_TCVSYN3_LEN (32U)
+#define TIMER_TCVSYN3_MSK \
+ (((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS)
+#define TIMER_TCVSYN3_UMSK \
+ (~(((1U << TIMER_TCVSYN3_LEN) - 1) << TIMER_TCVSYN3_POS))
+
+/* 0xBC : TCDR */
+
+#define TIMER_TCDR_OFFSET (0xBC)
+#define TIMER_TCDR2 TIMER_TCDR2
+#define TIMER_TCDR2_POS (8U)
+#define TIMER_TCDR2_LEN (8U)
+#define TIMER_TCDR2_MSK (((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS)
+#define TIMER_TCDR2_UMSK (~(((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS))
+#define TIMER_TCDR3 TIMER_TCDR3
+#define TIMER_TCDR3_POS (16U)
+#define TIMER_TCDR3_LEN (8U)
+#define TIMER_TCDR3_MSK (((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS)
+#define TIMER_TCDR3_UMSK (~(((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS))
+#define TIMER_WCDR TIMER_WCDR
+#define TIMER_WCDR_POS (24U)
+#define TIMER_WCDR_LEN (8U)
+#define TIMER_WCDR_MSK (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)
+#define TIMER_WCDR_UMSK (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS))
+
+#define WDT_ENABLE_ACCESS() \
+ { \
+ BL_WR_REG(TIMER_BASE, \
+ TIMER_WFAR, \
+ BL_SET_REG_BITS_VAL( \
+ BL_RD_REG(TIMER_BASE, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \
+ BL_WR_REG(TIMER_BASE, \
+ TIMER_WSAR, \
+ BL_SET_REG_BITS_VAL( \
+ BL_RD_REG(TIMER_BASE, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \
+ }
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+/* TIMER channel type definition */
+
+enum timer_chan_e
+{
+ TIMER_CH0, /* TIMER channel 0 port define */
+ TIMER_CH1, /* TIMER channel 1 port define */
+ TIMER_CH_MAX
+};
+typedef enum timer_chan_e timer_chan_t;
+
+/* TIMER clock source type definition */
+
+enum timer_clksrc_e
+{
+ TIMER_CLKSRC_FCLK, /* TIMER clock source :System CLK */
+ TIMER_CLKSRC_32K, /* TIMER clock source :32K CLK */
+ TIMER_CLKSRC_1K, /* TIMER clock source :1K CLK,Only for Timer not for
+ * Watchdog */
+ TIMER_CLKSRC_XTAL /* TIMER clock source :XTAL CLK */
+};
+typedef enum timer_clksrc_e timer_clksrc_t;
+
+/* TIMER match compare ID type definition */
+
+enum timer_comp_id_e
+{
+ TIMER_COMP_ID_0, /* TIMER match compare ID 0 define */
+ TIMER_COMP_ID_1, /* TIMER match compare ID 1 define */
+ TIMER_COMP_ID_2 /* TIMER match compare ID 2 define */
+};
+typedef enum timer_comp_id_e timer_comp_id_t;
+
+/* TIMER preload source type definition */
+
+enum timer_preload_trig_e
+{
+ TIMER_PRELOAD_TRIG_NONE, /* TIMER no preload source, just free run */
+ TIMER_PRELOAD_TRIG_COMP0, /* TIMER count register preload triggered by
+ * comparator 0 */
+ TIMER_PRELOAD_TRIG_COMP1, /* TIMER count register preload triggered by
+ * comparator 1 */
+ TIMER_PRELOAD_TRIG_COMP2 /* TIMER count register preload triggered by
+ * comparator 2 */
+};
+typedef enum timer_preload_trig_e timer_preload_trig_t;
+
+/* TIMER count register run mode type definition */
+
+enum timer_countmode_e
+{
+ TIMER_COUNT_PRELOAD, /* TIMER count register preload from comparator
+ * register */
+ TIMER_COUNT_FREERUN /* TIMER count register free run */
+};
+typedef enum timer_countmode_e timer_countmode_t;
+
+/* TIMER interrupt type definition */
+
+enum timer_int_e
+{
+ TIMER_INT_COMP_0, /* Comparator 0 match cause interrupt */
+ TIMER_INT_COMP_1, /* Comparator 1 match cause interrupt */
+ TIMER_INT_COMP_2, /* Comparator 2 match cause interrupt */
+ TIMER_INT_ALL
+};
+typedef enum timer_int_e timer_int_t;
+
+/* Watchdog timer interrupt type definition */
+
+enum wdt_int_e
+{
+ WDT_INT, /* Comparator 0 match cause interrupt */
+ WDT_INT_ALL
+};
+typedef enum wdt_int_e wdt_int_t;
+
+/* TIMER configuration structure type definition */
+
+struct timer_cfg_s
+{
+ timer_chan_t timer_ch; /* Timer channel */
+ timer_clksrc_t clk_src; /* Timer clock source */
+ timer_preload_trig_t
+ pl_trig_src; /* Timer count register preload trigger source slelect */
+ timer_countmode_t count_mode; /* Timer count mode */
+ uint8_t clock_division; /* Timer clock divison value */
+ uint32_t match_val0; /* Timer match 0 value 0 */
+ uint32_t match_val1; /* Timer match 1 value 0 */
+ uint32_t match_val2; /* Timer match 2 value 0 */
+ uint32_t pre_load_val; /* Timer preload value */
+};
+typedef struct timer_cfg_s timer_cfg_t;
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+EXTERN uint32_t timer_getcompvalue(timer_chan_t timer_ch,
+ timer_comp_id_t cmp_no);
+EXTERN void timer_setcompvalue(timer_chan_t timer_ch,
+ timer_comp_id_t cmp_no,
+ uint32_t val);
+EXTERN uint32_t timer_getcountervalue(timer_chan_t timer_ch);
+EXTERN uint32_t timer_getmatchstatus(timer_chan_t timer_ch,
+ timer_comp_id_t cmp_no);
+EXTERN uint32_t timer_getpreloadvalue(timer_chan_t timer_ch);
+EXTERN void timer_setpreloadvalue(timer_chan_t timer_ch, uint32_t val);
+EXTERN void timer_setpreloadtrigsrc(timer_chan_t timer_ch,
+ timer_preload_trig_t pl_src);
+EXTERN void timer_setcountmode(timer_chan_t timer_ch,
+ timer_countmode_t count_mode);
+EXTERN void timer_clearintstatus(timer_chan_t timer_ch,
+ timer_comp_id_t cmp_no);
+EXTERN void timer_init(timer_cfg_t *timer_cfg);
+EXTERN void timer_enable(timer_chan_t timer_ch);
+EXTERN void timer_disable(timer_chan_t timer_ch);
+EXTERN void timer_intmask(timer_chan_t timer_ch,
+ timer_int_t int_type, uint32_t int_mask);
+EXTERN void wdt_set_clock(timer_clksrc_t clk_src, uint8_t div);
+EXTERN uint32_t wdt_getmatchvalue(void);
+EXTERN void wdt_setcompvalue(uint16_t val);
+EXTERN uint16_t wdt_getcountervalue(void);
+EXTERN void wdt_resetcountervalue(void);
+EXTERN uint32_t wdt_getresetstatus(void);
+EXTERN void wdt_clearresetstatus(void);
+EXTERN void wdt_enable(void);
+EXTERN void wdt_disable(void);
+EXTERN void wdt_intmask(wdt_int_t int_type, uint32_t int_mask);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_GPIO_H */
diff --git a/arch/risc-v/src/bl602/hardware/bl602_uart.h b/arch/risc-v/src/bl602/hardware/bl602_uart.h
new file mode 100644
index 0000000000..7166432850
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/bl602_uart.h
@@ -0,0 +1,1010 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/bl602_uart.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_UART_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_UART_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "hardware/bl602_common.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* 0x0 : utx_config */
+
+#define UART_UTX_CONFIG_OFFSET (0x0)
+#define UART_CR_UTX_EN UART_CR_UTX_EN
+#define UART_CR_UTX_EN_POS (0U)
+#define UART_CR_UTX_EN_LEN (1U)
+#define UART_CR_UTX_EN_MSK \
+ (((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS)
+#define UART_CR_UTX_EN_UMSK \
+ (~(((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS))
+#define UART_CR_UTX_CTS_EN UART_CR_UTX_CTS_EN
+#define UART_CR_UTX_CTS_EN_POS (1U)
+#define UART_CR_UTX_CTS_EN_LEN (1U)
+#define UART_CR_UTX_CTS_EN_MSK \
+ (((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS)
+#define UART_CR_UTX_CTS_EN_UMSK \
+ (~(((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS))
+#define UART_CR_UTX_FRM_EN UART_CR_UTX_FRM_EN
+#define UART_CR_UTX_FRM_EN_POS (2U)
+#define UART_CR_UTX_FRM_EN_LEN (1U)
+#define UART_CR_UTX_FRM_EN_MSK \
+ (((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS)
+#define UART_CR_UTX_FRM_EN_UMSK \
+ (~(((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS))
+#define UART_CR_UTX_PRT_EN UART_CR_UTX_PRT_EN
+#define UART_CR_UTX_PRT_EN_POS (4U)
+#define UART_CR_UTX_PRT_EN_LEN (1U)
+#define UART_CR_UTX_PRT_EN_MSK \
+ (((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS)
+#define UART_CR_UTX_PRT_EN_UMSK \
+ (~(((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS))
+#define UART_CR_UTX_PRT_SEL UART_CR_UTX_PRT_SEL
+#define UART_CR_UTX_PRT_SEL_POS (5U)
+#define UART_CR_UTX_PRT_SEL_LEN (1U)
+#define UART_CR_UTX_PRT_SEL_MSK \
+ (((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS)
+#define UART_CR_UTX_PRT_SEL_UMSK \
+ (~(((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS))
+#define UART_CR_UTX_IR_EN UART_CR_UTX_IR_EN
+#define UART_CR_UTX_IR_EN_POS (6U)
+#define UART_CR_UTX_IR_EN_LEN (1U)
+#define UART_CR_UTX_IR_EN_MSK \
+ (((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS)
+#define UART_CR_UTX_IR_EN_UMSK \
+ (~(((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS))
+#define UART_CR_UTX_IR_INV UART_CR_UTX_IR_INV
+#define UART_CR_UTX_IR_INV_POS (7U)
+#define UART_CR_UTX_IR_INV_LEN (1U)
+#define UART_CR_UTX_IR_INV_MSK \
+ (((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS)
+#define UART_CR_UTX_IR_INV_UMSK \
+ (~(((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS))
+#define UART_CR_UTX_BIT_CNT_D UART_CR_UTX_BIT_CNT_D
+#define UART_CR_UTX_BIT_CNT_D_POS (8U)
+#define UART_CR_UTX_BIT_CNT_D_LEN (3U)
+#define UART_CR_UTX_BIT_CNT_D_MSK \
+ (((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS)
+#define UART_CR_UTX_BIT_CNT_D_UMSK \
+ (~(((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS))
+#define UART_CR_UTX_BIT_CNT_P UART_CR_UTX_BIT_CNT_P
+#define UART_CR_UTX_BIT_CNT_P_POS (12U)
+#define UART_CR_UTX_BIT_CNT_P_LEN (2U)
+#define UART_CR_UTX_BIT_CNT_P_MSK \
+ (((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS)
+#define UART_CR_UTX_BIT_CNT_P_UMSK \
+ (~(((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS))
+#define UART_CR_UTX_LEN UART_CR_UTX_LEN
+#define UART_CR_UTX_LEN_POS (16U)
+#define UART_CR_UTX_LEN_LEN (16U)
+#define UART_CR_UTX_LEN_MSK \
+ (((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS)
+#define UART_CR_UTX_LEN_UMSK \
+ (~(((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS))
+
+/* 0x4 : urx_config */
+
+#define UART_URX_CONFIG_OFFSET (0x4)
+#define UART_CR_URX_EN UART_CR_URX_EN
+#define UART_CR_URX_EN_POS (0U)
+#define UART_CR_URX_EN_LEN (1U)
+#define UART_CR_URX_EN_MSK \
+ (((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS)
+#define UART_CR_URX_EN_UMSK \
+ (~(((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS))
+#define UART_CR_URX_RTS_SW_MODE UART_CR_URX_RTS_SW_MODE
+#define UART_CR_URX_RTS_SW_MODE_POS (1U)
+#define UART_CR_URX_RTS_SW_MODE_LEN (1U)
+#define UART_CR_URX_RTS_SW_MODE_MSK \
+ (((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS)
+#define UART_CR_URX_RTS_SW_MODE_UMSK \
+ (~(((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) \
+ << UART_CR_URX_RTS_SW_MODE_POS))
+#define UART_CR_URX_RTS_SW_VAL UART_CR_URX_RTS_SW_VAL
+#define UART_CR_URX_RTS_SW_VAL_POS (2U)
+#define UART_CR_URX_RTS_SW_VAL_LEN (1U)
+#define UART_CR_URX_RTS_SW_VAL_MSK \
+ (((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS)
+#define UART_CR_URX_RTS_SW_VAL_UMSK \
+ (~(((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS))
+#define UART_CR_URX_ABR_EN UART_CR_URX_ABR_EN
+#define UART_CR_URX_ABR_EN_POS (3U)
+#define UART_CR_URX_ABR_EN_LEN (1U)
+#define UART_CR_URX_ABR_EN_MSK \
+ (((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS)
+#define UART_CR_URX_ABR_EN_UMSK \
+ (~(((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS))
+#define UART_CR_URX_PRT_EN UART_CR_URX_PRT_EN
+#define UART_CR_URX_PRT_EN_POS (4U)
+#define UART_CR_URX_PRT_EN_LEN (1U)
+#define UART_CR_URX_PRT_EN_MSK \
+ (((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS)
+#define UART_CR_URX_PRT_EN_UMSK \
+ (~(((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS))
+#define UART_CR_URX_PRT_SEL UART_CR_URX_PRT_SEL
+#define UART_CR_URX_PRT_SEL_POS (5U)
+#define UART_CR_URX_PRT_SEL_LEN (1U)
+#define UART_CR_URX_PRT_SEL_MSK \
+ (((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS)
+#define UART_CR_URX_PRT_SEL_UMSK \
+ (~(((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS))
+#define UART_CR_URX_IR_EN UART_CR_URX_IR_EN
+#define UART_CR_URX_IR_EN_POS (6U)
+#define UART_CR_URX_IR_EN_LEN (1U)
+#define UART_CR_URX_IR_EN_MSK \
+ (((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS)
+#define UART_CR_URX_IR_EN_UMSK \
+ (~(((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS))
+#define UART_CR_URX_IR_INV UART_CR_URX_IR_INV
+#define UART_CR_URX_IR_INV_POS (7U)
+#define UART_CR_URX_IR_INV_LEN (1U)
+#define UART_CR_URX_IR_INV_MSK \
+ (((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS)
+#define UART_CR_URX_IR_INV_UMSK \
+ (~(((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS))
+#define UART_CR_URX_BIT_CNT_D UART_CR_URX_BIT_CNT_D
+#define UART_CR_URX_BIT_CNT_D_POS (8U)
+#define UART_CR_URX_BIT_CNT_D_LEN (3U)
+#define UART_CR_URX_BIT_CNT_D_MSK \
+ (((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS)
+#define UART_CR_URX_BIT_CNT_D_UMSK \
+ (~(((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS))
+#define UART_CR_URX_DEG_EN UART_CR_URX_DEG_EN
+#define UART_CR_URX_DEG_EN_POS (11U)
+#define UART_CR_URX_DEG_EN_LEN (1U)
+#define UART_CR_URX_DEG_EN_MSK \
+ (((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS)
+#define UART_CR_URX_DEG_EN_UMSK \
+ (~(((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS))
+#define UART_CR_URX_DEG_CNT UART_CR_URX_DEG_CNT
+#define UART_CR_URX_DEG_CNT_POS (12U)
+#define UART_CR_URX_DEG_CNT_LEN (4U)
+#define UART_CR_URX_DEG_CNT_MSK \
+ (((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS)
+#define UART_CR_URX_DEG_CNT_UMSK \
+ (~(((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS))
+#define UART_CR_URX_LEN UART_CR_URX_LEN
+#define UART_CR_URX_LEN_POS (16U)
+#define UART_CR_URX_LEN_LEN (16U)
+#define UART_CR_URX_LEN_MSK \
+ (((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS)
+#define UART_CR_URX_LEN_UMSK \
+ (~(((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS))
+
+/* 0x8 : uart_bit_prd */
+
+#define UART_BIT_PRD_OFFSET (0x8)
+#define UART_CR_UTX_BIT_PRD UART_CR_UTX_BIT_PRD
+#define UART_CR_UTX_BIT_PRD_POS (0U)
+#define UART_CR_UTX_BIT_PRD_LEN (16U)
+#define UART_CR_UTX_BIT_PRD_MSK \
+ (((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS)
+#define UART_CR_UTX_BIT_PRD_UMSK \
+ (~(((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS))
+#define UART_CR_URX_BIT_PRD UART_CR_URX_BIT_PRD
+#define UART_CR_URX_BIT_PRD_POS (16U)
+#define UART_CR_URX_BIT_PRD_LEN (16U)
+#define UART_CR_URX_BIT_PRD_MSK \
+ (((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS)
+#define UART_CR_URX_BIT_PRD_UMSK \
+ (~(((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS))
+
+/* 0xC : data_config */
+
+#define UART_DATA_CONFIG_OFFSET (0xC)
+#define UART_CR_UART_BIT_INV UART_CR_UART_BIT_INV
+#define UART_CR_UART_BIT_INV_POS (0U)
+#define UART_CR_UART_BIT_INV_LEN (1U)
+#define UART_CR_UART_BIT_INV_MSK \
+ (((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS)
+#define UART_CR_UART_BIT_INV_UMSK \
+ (~(((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS))
+
+/* 0x10 : utx_ir_position */
+
+#define UART_UTX_IR_POSITION_OFFSET (0x10)
+#define UART_CR_UTX_IR_POS_S UART_CR_UTX_IR_POS_S
+#define UART_CR_UTX_IR_POS_S_POS (0U)
+#define UART_CR_UTX_IR_POS_S_LEN (16U)
+#define UART_CR_UTX_IR_POS_S_MSK \
+ (((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS)
+#define UART_CR_UTX_IR_POS_S_UMSK \
+ (~(((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS))
+#define UART_CR_UTX_IR_POS_P UART_CR_UTX_IR_POS_P
+#define UART_CR_UTX_IR_POS_P_POS (16U)
+#define UART_CR_UTX_IR_POS_P_LEN (16U)
+#define UART_CR_UTX_IR_POS_P_MSK \
+ (((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS)
+#define UART_CR_UTX_IR_POS_P_UMSK \
+ (~(((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS))
+
+/* 0x14 : urx_ir_position */
+
+#define UART_URX_IR_POSITION_OFFSET (0x14)
+#define UART_CR_URX_IR_POS_S UART_CR_URX_IR_POS_S
+#define UART_CR_URX_IR_POS_S_POS (0U)
+#define UART_CR_URX_IR_POS_S_LEN (16U)
+#define UART_CR_URX_IR_POS_S_MSK \
+ (((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS)
+#define UART_CR_URX_IR_POS_S_UMSK \
+ (~(((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS))
+
+/* 0x18 : urx_rto_timer */
+
+#define UART_URX_RTO_TIMER_OFFSET (0x18)
+#define UART_CR_URX_RTO_VALUE UART_CR_URX_RTO_VALUE
+#define UART_CR_URX_RTO_VALUE_POS (0U)
+#define UART_CR_URX_RTO_VALUE_LEN (8U)
+#define UART_CR_URX_RTO_VALUE_MSK \
+ (((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS)
+#define UART_CR_URX_RTO_VALUE_UMSK \
+ (~(((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS))
+
+/* 0x20 : UART interrupt status */
+
+#define UART_INT_STS_OFFSET (0x20)
+#define UART_UTX_END_INT UART_UTX_END_INT
+#define UART_UTX_END_INT_POS (0U)
+#define UART_UTX_END_INT_LEN (1U)
+#define UART_UTX_END_INT_MSK \
+ (((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS)
+#define UART_UTX_END_INT_UMSK \
+ (~(((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS))
+#define UART_URX_END_INT UART_URX_END_INT
+#define UART_URX_END_INT_POS (1U)
+#define UART_URX_END_INT_LEN (1U)
+#define UART_URX_END_INT_MSK \
+ (((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS)
+#define UART_URX_END_INT_UMSK \
+ (~(((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS))
+#define UART_UTX_FIFO_INT UART_UTX_FIFO_INT
+#define UART_UTX_FIFO_INT_POS (2U)
+#define UART_UTX_FIFO_INT_LEN (1U)
+#define UART_UTX_FIFO_INT_MSK \
+ (((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS)
+#define UART_UTX_FIFO_INT_UMSK \
+ (~(((1U << UART_UTX_FIFO_INT_LEN) - 1) << UART_UTX_FIFO_INT_POS))
+#define UART_URX_FIFO_INT UART_URX_FIFO_INT
+#define UART_URX_FIFO_INT_POS (3U)
+#define UART_URX_FIFO_INT_LEN (1U)
+#define UART_URX_FIFO_INT_MSK \
+ (((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS)
+#define UART_URX_FIFO_INT_UMSK \
+ (~(((1U << UART_URX_FIFO_INT_LEN) - 1) << UART_URX_FIFO_INT_POS))
+#define UART_URX_RTO_INT UART_URX_RTO_INT
+#define UART_URX_RTO_INT_POS (4U)
+#define UART_URX_RTO_INT_LEN (1U)
+#define UART_URX_RTO_INT_MSK \
+ (((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS)
+#define UART_URX_RTO_INT_UMSK \
+ (~(((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS))
+#define UART_URX_PCE_INT UART_URX_PCE_INT
+#define UART_URX_PCE_INT_POS (5U)
+#define UART_URX_PCE_INT_LEN (1U)
+#define UART_URX_PCE_INT_MSK \
+ (((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS)
+#define UART_URX_PCE_INT_UMSK \
+ (~(((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS))
+#define UART_UTX_FER_INT UART_UTX_FER_INT
+#define UART_UTX_FER_INT_POS (6U)
+#define UART_UTX_FER_INT_LEN (1U)
+#define UART_UTX_FER_INT_MSK \
+ (((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS)
+#define UART_UTX_FER_INT_UMSK \
+ (~(((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS))
+#define UART_URX_FER_INT UART_URX_FER_INT
+#define UART_URX_FER_INT_POS (7U)
+#define UART_URX_FER_INT_LEN (1U)
+#define UART_URX_FER_INT_MSK \
+ (((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS)
+#define UART_URX_FER_INT_UMSK \
+ (~(((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS))
+
+/* 0x24 : UART interrupt mask */
+
+#define UART_INT_MASK_OFFSET (0x24)
+#define UART_CR_UTX_END_MASK UART_CR_UTX_END_MASK
+#define UART_CR_UTX_END_MASK_POS (0U)
+#define UART_CR_UTX_END_MASK_LEN (1U)
+#define UART_CR_UTX_END_MASK_MSK \
+ (((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS)
+#define UART_CR_UTX_END_MASK_UMSK \
+ (~(((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS))
+#define UART_CR_URX_END_MASK UART_CR_URX_END_MASK
+#define UART_CR_URX_END_MASK_POS (1U)
+#define UART_CR_URX_END_MASK_LEN (1U)
+#define UART_CR_URX_END_MASK_MSK \
+ (((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS)
+#define UART_CR_URX_END_MASK_UMSK \
+ (~(((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS))
+#define UART_CR_UTX_FIFO_MASK UART_CR_UTX_FIFO_MASK
+#define UART_CR_UTX_FIFO_MASK_POS (2U)
+#define UART_CR_UTX_FIFO_MASK_LEN (1U)
+#define UART_CR_UTX_FIFO_MASK_MSK \
+ (((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS)
+#define UART_CR_UTX_FIFO_MASK_UMSK \
+ (~(((1U << UART_CR_UTX_FIFO_MASK_LEN) - 1) << UART_CR_UTX_FIFO_MASK_POS))
+#define UART_CR_URX_FIFO_MASK UART_CR_URX_FIFO_MASK
+#define UART_CR_URX_FIFO_MASK_POS (3U)
+#define UART_CR_URX_FIFO_MASK_LEN (1U)
+#define UART_CR_URX_FIFO_MASK_MSK \
+ (((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS)
+#define UART_CR_URX_FIFO_MASK_UMSK \
+ (~(((1U << UART_CR_URX_FIFO_MASK_LEN) - 1) << UART_CR_URX_FIFO_MASK_POS))
+#define UART_CR_URX_RTO_MASK UART_CR_URX_RTO_MASK
+#define UART_CR_URX_RTO_MASK_POS (4U)
+#define UART_CR_URX_RTO_MASK_LEN (1U)
+#define UART_CR_URX_RTO_MASK_MSK \
+ (((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS)
+#define UART_CR_URX_RTO_MASK_UMSK \
+ (~(((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS))
+#define UART_CR_URX_PCE_MASK UART_CR_URX_PCE_MASK
+#define UART_CR_URX_PCE_MASK_POS (5U)
+#define UART_CR_URX_PCE_MASK_LEN (1U)
+#define UART_CR_URX_PCE_MASK_MSK \
+ (((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS)
+#define UART_CR_URX_PCE_MASK_UMSK \
+ (~(((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS))
+#define UART_CR_UTX_FER_MASK UART_CR_UTX_FER_MASK
+#define UART_CR_UTX_FER_MASK_POS (6U)
+#define UART_CR_UTX_FER_MASK_LEN (1U)
+#define UART_CR_UTX_FER_MASK_MSK \
+ (((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS)
+#define UART_CR_UTX_FER_MASK_UMSK \
+ (~(((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS))
+#define UART_CR_URX_FER_MASK UART_CR_URX_FER_MASK
+#define UART_CR_URX_FER_MASK_POS (7U)
+#define UART_CR_URX_FER_MASK_LEN (1U)
+#define UART_CR_URX_FER_MASK_MSK \
+ (((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS)
+#define UART_CR_URX_FER_MASK_UMSK \
+ (~(((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS))
+
+/* 0x28 : UART interrupt clear */
+
+#define UART_INT_CLEAR_OFFSET (0x28)
+#define UART_CR_UTX_END_CLR UART_CR_UTX_END_CLR
+#define UART_CR_UTX_END_CLR_POS (0U)
+#define UART_CR_UTX_END_CLR_LEN (1U)
+#define UART_CR_UTX_END_CLR_MSK \
+ (((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS)
+#define UART_CR_UTX_END_CLR_UMSK \
+ (~(((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS))
+#define UART_CR_URX_END_CLR UART_CR_URX_END_CLR
+#define UART_CR_URX_END_CLR_POS (1U)
+#define UART_CR_URX_END_CLR_LEN (1U)
+#define UART_CR_URX_END_CLR_MSK \
+ (((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS)
+#define UART_CR_URX_END_CLR_UMSK \
+ (~(((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS))
+#define UART_CR_URX_RTO_CLR UART_CR_URX_RTO_CLR
+#define UART_CR_URX_RTO_CLR_POS (4U)
+#define UART_CR_URX_RTO_CLR_LEN (1U)
+#define UART_CR_URX_RTO_CLR_MSK \
+ (((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS)
+#define UART_CR_URX_RTO_CLR_UMSK \
+ (~(((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS))
+#define UART_CR_URX_PCE_CLR UART_CR_URX_PCE_CLR
+#define UART_CR_URX_PCE_CLR_POS (5U)
+#define UART_CR_URX_PCE_CLR_LEN (1U)
+#define UART_CR_URX_PCE_CLR_MSK \
+ (((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS)
+#define UART_CR_URX_PCE_CLR_UMSK \
+ (~(((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS))
+
+/* 0x2C : UART interrupt enable */
+
+#define UART_INT_EN_OFFSET (0x2C)
+#define UART_CR_UTX_END_EN UART_CR_UTX_END_EN
+#define UART_CR_UTX_END_EN_POS (0U)
+#define UART_CR_UTX_END_EN_LEN (1U)
+#define UART_CR_UTX_END_EN_MSK \
+ (((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS)
+#define UART_CR_UTX_END_EN_UMSK \
+ (~(((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS))
+#define UART_CR_URX_END_EN UART_CR_URX_END_EN
+#define UART_CR_URX_END_EN_POS (1U)
+#define UART_CR_URX_END_EN_LEN (1U)
+#define UART_CR_URX_END_EN_MSK \
+ (((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS)
+#define UART_CR_URX_END_EN_UMSK \
+ (~(((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS))
+#define UART_CR_UTX_FIFO_EN UART_CR_UTX_FIFO_EN
+#define UART_CR_UTX_FIFO_EN_POS (2U)
+#define UART_CR_UTX_FIFO_EN_LEN (1U)
+#define UART_CR_UTX_FIFO_EN_MSK \
+ (((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS)
+#define UART_CR_UTX_FIFO_EN_UMSK \
+ (~(((1U << UART_CR_UTX_FIFO_EN_LEN) - 1) << UART_CR_UTX_FIFO_EN_POS))
+#define UART_CR_URX_FIFO_EN UART_CR_URX_FIFO_EN
+#define UART_CR_URX_FIFO_EN_POS (3U)
+#define UART_CR_URX_FIFO_EN_LEN (1U)
+#define UART_CR_URX_FIFO_EN_MSK \
+ (((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS)
+#define UART_CR_URX_FIFO_EN_UMSK \
+ (~(((1U << UART_CR_URX_FIFO_EN_LEN) - 1) << UART_CR_URX_FIFO_EN_POS))
+#define UART_CR_URX_RTO_EN UART_CR_URX_RTO_EN
+#define UART_CR_URX_RTO_EN_POS (4U)
+#define UART_CR_URX_RTO_EN_LEN (1U)
+#define UART_CR_URX_RTO_EN_MSK \
+ (((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS)
+#define UART_CR_URX_RTO_EN_UMSK \
+ (~(((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS))
+#define UART_CR_URX_PCE_EN UART_CR_URX_PCE_EN
+#define UART_CR_URX_PCE_EN_POS (5U)
+#define UART_CR_URX_PCE_EN_LEN (1U)
+#define UART_CR_URX_PCE_EN_MSK \
+ (((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS)
+#define UART_CR_URX_PCE_EN_UMSK \
+ (~(((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS))
+#define UART_CR_UTX_FER_EN UART_CR_UTX_FER_EN
+#define UART_CR_UTX_FER_EN_POS (6U)
+#define UART_CR_UTX_FER_EN_LEN (1U)
+#define UART_CR_UTX_FER_EN_MSK \
+ (((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS)
+#define UART_CR_UTX_FER_EN_UMSK \
+ (~(((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS))
+#define UART_CR_URX_FER_EN UART_CR_URX_FER_EN
+#define UART_CR_URX_FER_EN_POS (7U)
+#define UART_CR_URX_FER_EN_LEN (1U)
+#define UART_CR_URX_FER_EN_MSK \
+ (((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS)
+#define UART_CR_URX_FER_EN_UMSK \
+ (~(((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS))
+
+/* 0x30 : uart_status */
+
+#define UART_STATUS_OFFSET (0x30)
+#define UART_STS_UTX_BUS_BUSY UART_STS_UTX_BUS_BUSY
+#define UART_STS_UTX_BUS_BUSY_POS (0U)
+#define UART_STS_UTX_BUS_BUSY_LEN (1U)
+#define UART_STS_UTX_BUS_BUSY_MSK \
+ (((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS)
+#define UART_STS_UTX_BUS_BUSY_UMSK \
+ (~(((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS))
+#define UART_STS_URX_BUS_BUSY UART_STS_URX_BUS_BUSY
+#define UART_STS_URX_BUS_BUSY_POS (1U)
+#define UART_STS_URX_BUS_BUSY_LEN (1U)
+#define UART_STS_URX_BUS_BUSY_MSK \
+ (((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS)
+#define UART_STS_URX_BUS_BUSY_UMSK \
+ (~(((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS))
+
+/* 0x34 : sts_urx_abr_prd */
+
+#define UART_STS_URX_ABR_PRD_OFFSET (0x34)
+#define UART_STS_URX_ABR_PRD_START UART_STS_URX_ABR_PRD_START
+#define UART_STS_URX_ABR_PRD_START_POS (0U)
+#define UART_STS_URX_ABR_PRD_START_LEN (16U)
+#define UART_STS_URX_ABR_PRD_START_MSK \
+ (((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) \
+ << UART_STS_URX_ABR_PRD_START_POS)
+#define UART_STS_URX_ABR_PRD_START_UMSK \
+ (~(((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) \
+ << UART_STS_URX_ABR_PRD_START_POS))
+#define UART_STS_URX_ABR_PRD_0X55 UART_STS_URX_ABR_PRD_0X55
+#define UART_STS_URX_ABR_PRD_0X55_POS (16U)
+#define UART_STS_URX_ABR_PRD_0X55_LEN (16U)
+#define UART_STS_URX_ABR_PRD_0X55_MSK \
+ (((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) \
+ << UART_STS_URX_ABR_PRD_0X55_POS)
+#define UART_STS_URX_ABR_PRD_0X55_UMSK \
+ (~(((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) \
+ << UART_STS_URX_ABR_PRD_0X55_POS))
+
+/* 0x80 : uart_fifo_config_0 */
+
+#define UART_FIFO_CONFIG_0_OFFSET (0x80)
+#define UART_DMA_TX_EN UART_DMA_TX_EN
+#define UART_DMA_TX_EN_POS (0U)
+#define UART_DMA_TX_EN_LEN (1U)
+#define UART_DMA_TX_EN_MSK \
+ (((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS)
+#define UART_DMA_TX_EN_UMSK \
+ (~(((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS))
+#define UART_DMA_RX_EN UART_DMA_RX_EN
+#define UART_DMA_RX_EN_POS (1U)
+#define UART_DMA_RX_EN_LEN (1U)
+#define UART_DMA_RX_EN_MSK \
+ (((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS)
+#define UART_DMA_RX_EN_UMSK \
+ (~(((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS))
+#define UART_TX_FIFO_CLR UART_TX_FIFO_CLR
+#define UART_TX_FIFO_CLR_POS (2U)
+#define UART_TX_FIFO_CLR_LEN (1U)
+#define UART_TX_FIFO_CLR_MSK \
+ (((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS)
+#define UART_TX_FIFO_CLR_UMSK \
+ (~(((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS))
+#define UART_RX_FIFO_CLR UART_RX_FIFO_CLR
+#define UART_RX_FIFO_CLR_POS (3U)
+#define UART_RX_FIFO_CLR_LEN (1U)
+#define UART_RX_FIFO_CLR_MSK \
+ (((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS)
+#define UART_RX_FIFO_CLR_UMSK \
+ (~(((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS))
+#define UART_TX_FIFO_OVERFLOW UART_TX_FIFO_OVERFLOW
+#define UART_TX_FIFO_OVERFLOW_POS (4U)
+#define UART_TX_FIFO_OVERFLOW_LEN (1U)
+#define UART_TX_FIFO_OVERFLOW_MSK \
+ (((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS)
+#define UART_TX_FIFO_OVERFLOW_UMSK \
+ (~(((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS))
+#define UART_TX_FIFO_UNDERFLOW UART_TX_FIFO_UNDERFLOW
+#define UART_TX_FIFO_UNDERFLOW_POS (5U)
+#define UART_TX_FIFO_UNDERFLOW_LEN (1U)
+#define UART_TX_FIFO_UNDERFLOW_MSK \
+ (((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS)
+#define UART_TX_FIFO_UNDERFLOW_UMSK \
+ (~(((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS))
+#define UART_RX_FIFO_OVERFLOW UART_RX_FIFO_OVERFLOW
+#define UART_RX_FIFO_OVERFLOW_POS (6U)
+#define UART_RX_FIFO_OVERFLOW_LEN (1U)
+#define UART_RX_FIFO_OVERFLOW_MSK \
+ (((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS)
+#define UART_RX_FIFO_OVERFLOW_UMSK \
+ (~(((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS))
+#define UART_RX_FIFO_UNDERFLOW UART_RX_FIFO_UNDERFLOW
+#define UART_RX_FIFO_UNDERFLOW_POS (7U)
+#define UART_RX_FIFO_UNDERFLOW_LEN (1U)
+#define UART_RX_FIFO_UNDERFLOW_MSK \
+ (((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS)
+#define UART_RX_FIFO_UNDERFLOW_UMSK \
+ (~(((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS))
+
+/* 0x84 : uart_fifo_config_1 */
+
+#define UART_FIFO_CONFIG_1_OFFSET (0x84)
+#define UART_TX_FIFO_CNT UART_TX_FIFO_CNT
+#define UART_TX_FIFO_CNT_POS (0U)
+#define UART_TX_FIFO_CNT_LEN (6U)
+#define UART_TX_FIFO_CNT_MSK \
+ (((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS)
+#define UART_TX_FIFO_CNT_UMSK \
+ (~(((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS))
+#define UART_RX_FIFO_CNT UART_RX_FIFO_CNT
+#define UART_RX_FIFO_CNT_POS (8U)
+#define UART_RX_FIFO_CNT_LEN (6U)
+#define UART_RX_FIFO_CNT_MSK \
+ (((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS)
+#define UART_RX_FIFO_CNT_UMSK \
+ (~(((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS))
+#define UART_TX_FIFO_TH UART_TX_FIFO_TH
+#define UART_TX_FIFO_TH_POS (16U)
+#define UART_TX_FIFO_TH_LEN (5U)
+#define UART_TX_FIFO_TH_MSK \
+ (((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS)
+#define UART_TX_FIFO_TH_UMSK \
+ (~(((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS))
+#define UART_RX_FIFO_TH UART_RX_FIFO_TH
+#define UART_RX_FIFO_TH_POS (24U)
+#define UART_RX_FIFO_TH_LEN (5U)
+#define UART_RX_FIFO_TH_MSK \
+ (((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS)
+#define UART_RX_FIFO_TH_UMSK \
+ (~(((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS))
+
+/* 0x88 : uart_fifo_wdata */
+
+#define UART_FIFO_WDATA_OFFSET (0x88)
+#define UART_FIFO_WDATA UART_FIFO_WDATA
+#define UART_FIFO_WDATA_POS (0U)
+#define UART_FIFO_WDATA_LEN (8U)
+#define UART_FIFO_WDATA_MSK \
+ (((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS)
+#define UART_FIFO_WDATA_UMSK \
+ (~(((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS))
+
+/* 0x8C : uart_fifo_rdata */
+
+#define UART_FIFO_RDATA_OFFSET (0x8C)
+#define UART_FIFO_RDATA UART_FIFO_RDATA
+#define UART_FIFO_RDATA_POS (0U)
+#define UART_FIFO_RDATA_LEN (8U)
+#define UART_FIFO_RDATA_MSK \
+ (((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS)
+#define UART_FIFO_RDATA_UMSK \
+ (~(((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS))
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* UART port type definition */
+
+enum uart_id_e
+{
+ UART0_ID, /* UART0 port define */
+ UART1_ID, /* UART1 port define */
+ UART_ID_MAX /* UART MAX ID define */
+};
+
+/* UART direction type definition */
+
+enum uart_direction_e
+{
+ UART_TX, /* UART TX Direction */
+ UART_RX, /* UART RX Direction */
+ UART_TXRX /* UART TX and RX Direction */
+};
+
+/* UART parity type definition */
+
+enum uart_parity_e
+{
+ UART_PARITY_NONE, /* UART parity none define */
+ UART_PARITY_ODD, /* UART parity odd define */
+ UART_PARITY_EVEN /* UART parity even define */
+};
+
+/* UART data bits type definiton */
+
+enum uart_databits_e
+{
+ UART_DATABITS_5, /* UART data bits length:5 bits */
+ UART_DATABITS_6, /* UART data bits length:6 bits */
+ UART_DATABITS_7, /* UART data bits length:7 bits */
+ UART_DATABITS_8 /* UART data bits length:8 bits */
+};
+
+/* UART stop bits type definiton */
+
+enum uart_stopbits_e
+{
+ UART_STOPBITS_1, /* UART data stop bits length:1 bits */
+ UART_STOPBITS_1_5, /* UART data stop bits length:1.5 bits */
+ UART_STOPBITS_2 /* UART data stop bits length:2 bits */
+};
+
+/* UART each data byte is send out LSB-first or MSB-first type definiton */
+
+enum uart_bytebits_inverse_e
+{
+ UART_LSB_FIRST, /* UART each byte is send out LSB-first */
+ UART_MSB_FIRST /* UART each byte is send out MSB-first */
+};
+
+/* UART auto baudrate detection using codeword 0x55 or start bit definiton */
+
+enum uart_auto_baudrate_detection_e
+{
+ UART_AUTOBAUD_0X55, /* UART auto baudrate detection using codeword 0x55 */
+ UART_AUTOBAUD_STARTBIT /* UART auto baudrate detection using start bit */
+};
+
+/* UART interrupt type definition */
+
+enum uart_int_type_e
+{
+ UART_INT_TX_END, /* UART tx transfer end interrupt */
+ UART_INT_RX_END, /* UART rx transfer end interrupt */
+ UART_INT_TX_FIFO_REQ, /* UART tx fifo interrupt when tx fifo count
+ * reaches,auto clear */
+ UART_INT_RX_FIFO_REQ, /* UART rx fifo interrupt when rx fifo count
+ * reaches,auto clear */
+ UART_INT_RTO, /* UART rx time-out interrupt */
+ UART_INT_PCE, /* UART rx parity check error interrupt */
+ UART_INT_TX_FER, /* UART tx fifo overflow/underflow error interrupt */
+ UART_INT_RX_FER, /* UART rx fifo overflow/underflow error interrupt */
+ UART_INT_ALL /* All the interrupt */
+};
+
+/* UART overflow or underflow type definition */
+
+enum uart_overflow_e
+{
+ UART_TX_OVERFLOW, /* UART tx fifo overflow */
+ UART_TX_UNDERFLOW, /* UART tx fifo underflow */
+ UART_RX_OVERFLOW, /* UART rx fifo overflow */
+ UART_RX_UNDERFLOW /* UART rx fifo underflow */
+};
+
+struct uart_reg_s
+{
+ /* 0x0 : utx_config */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_utx_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t cr_utx_cts_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t cr_utx_frm_en : 1; /* [ 2], r/w, 0x0 */
+ uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t cr_utx_prt_en : 1; /* [ 4], r/w, 0x0 */
+ uint32_t cr_utx_prt_sel : 1; /* [ 5], r/w, 0x0 */
+ uint32_t cr_utx_ir_en : 1; /* [ 6], r/w, 0x0 */
+ uint32_t cr_utx_ir_inv : 1; /* [ 7], r/w, 0x0 */
+ uint32_t cr_utx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */
+ uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
+ uint32_t cr_utx_bit_cnt_p : 2; /* [13:12], r/w, 0x1 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t cr_utx_len : 16; /* [31:16], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } utx_config;
+
+ /* 0x4 : urx_config */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_urx_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t cr_urx_rts_sw_mode : 1; /* [ 1], r/w, 0x0 */
+ uint32_t cr_urx_rts_sw_val : 1; /* [ 2], r/w, 0x0 */
+ uint32_t cr_urx_abr_en : 1; /* [ 3], r/w, 0x0 */
+ uint32_t cr_urx_prt_en : 1; /* [ 4], r/w, 0x0 */
+ uint32_t cr_urx_prt_sel : 1; /* [ 5], r/w, 0x0 */
+ uint32_t cr_urx_ir_en : 1; /* [ 6], r/w, 0x0 */
+ uint32_t cr_urx_ir_inv : 1; /* [ 7], r/w, 0x0 */
+ uint32_t cr_urx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */
+ uint32_t cr_urx_deg_en : 1; /* [ 11], r/w, 0x0 */
+ uint32_t cr_urx_deg_cnt : 4; /* [15:12], r/w, 0x0 */
+ uint32_t cr_urx_len : 16; /* [31:16], r/w, 0x0 */
+ } bf;
+ uint32_t word;
+ } urx_config;
+
+ /* 0x8 : uart_bit_prd */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_utx_bit_prd : 16; /* [15: 0], r/w, 0xff */
+ uint32_t cr_urx_bit_prd : 16; /* [31:16], r/w, 0xff */
+ } bf;
+ uint32_t word;
+ } uart_bit_prd;
+
+ /* 0xC : data_config */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_uart_bit_inv : 1; /* [ 0], r/w, 0x0 */
+ uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } data_config;
+
+ /* 0x10 : utx_ir_position */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_utx_ir_pos_s : 16; /* [15: 0], r/w, 0x70 */
+ uint32_t cr_utx_ir_pos_p : 16; /* [31:16], r/w, 0x9f */
+ } bf;
+ uint32_t word;
+ } utx_ir_position;
+
+ /* 0x14 : urx_ir_position */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_urx_ir_pos_s : 16; /* [15: 0], r/w, 0x6f */
+ uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } urx_ir_position;
+
+ /* 0x18 : urx_rto_timer */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_urx_rto_value : 8; /* [ 7: 0], r/w, 0xf */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } urx_rto_timer;
+
+ /* 0x1c reserved */
+
+ uint8_t reserved_0x1c[4];
+
+ /* 0x20 : UART interrupt status */
+
+ union
+ {
+ struct
+ {
+ uint32_t utx_end_int : 1; /* [ 0], r, 0x0 */
+ uint32_t urx_end_int : 1; /* [ 1], r, 0x0 */
+ uint32_t utx_fifo_int : 1; /* [ 2], r, 0x0 */
+ uint32_t urx_fifo_int : 1; /* [ 3], r, 0x0 */
+ uint32_t urx_rto_int : 1; /* [ 4], r, 0x0 */
+ uint32_t urx_pce_int : 1; /* [ 5], r, 0x0 */
+ uint32_t utx_fer_int : 1; /* [ 6], r, 0x0 */
+ uint32_t urx_fer_int : 1; /* [ 7], r, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } uart_int_sts;
+
+ /* 0x24 : UART interrupt mask */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_utx_end_mask : 1; /* [ 0], r/w, 0x1 */
+ uint32_t cr_urx_end_mask : 1; /* [ 1], r/w, 0x1 */
+ uint32_t cr_utx_fifo_mask : 1; /* [ 2], r/w, 0x1 */
+ uint32_t cr_urx_fifo_mask : 1; /* [ 3], r/w, 0x1 */
+ uint32_t cr_urx_rto_mask : 1; /* [ 4], r/w, 0x1 */
+ uint32_t cr_urx_pce_mask : 1; /* [ 5], r/w, 0x1 */
+ uint32_t cr_utx_fer_mask : 1; /* [ 6], r/w, 0x1 */
+ uint32_t cr_urx_fer_mask : 1; /* [ 7], r/w, 0x1 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } uart_int_mask;
+
+ /* 0x28 : UART interrupt clear */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_utx_end_clr : 1; /* [ 0], w1c, 0x0 */
+ uint32_t cr_urx_end_clr : 1; /* [ 1], w1c, 0x0 */
+ uint32_t rsvd_2 : 1; /* [ 2], rsvd, 0x0 */
+ uint32_t rsvd_3 : 1; /* [ 3], rsvd, 0x0 */
+ uint32_t cr_urx_rto_clr : 1; /* [ 4], w1c, 0x0 */
+ uint32_t cr_urx_pce_clr : 1; /* [ 5], w1c, 0x0 */
+ uint32_t rsvd_6 : 1; /* [ 6], rsvd, 0x0 */
+ uint32_t rsvd_7 : 1; /* [ 7], rsvd, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } uart_int_clear;
+
+ /* 0x2C : UART interrupt enable */
+
+ union
+ {
+ struct
+ {
+ uint32_t cr_utx_end_en : 1; /* [ 0], r/w, 0x1 */
+ uint32_t cr_urx_end_en : 1; /* [ 1], r/w, 0x1 */
+ uint32_t cr_utx_fifo_en : 1; /* [ 2], r/w, 0x1 */
+ uint32_t cr_urx_fifo_en : 1; /* [ 3], r/w, 0x1 */
+ uint32_t cr_urx_rto_en : 1; /* [ 4], r/w, 0x1 */
+ uint32_t cr_urx_pce_en : 1; /* [ 5], r/w, 0x1 */
+ uint32_t cr_utx_fer_en : 1; /* [ 6], r/w, 0x1 */
+ uint32_t cr_urx_fer_en : 1; /* [ 7], r/w, 0x1 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } uart_int_en;
+
+ /* 0x30 : uart_status */
+
+ union
+ {
+ struct
+ {
+ uint32_t sts_utx_bus_busy : 1; /* [ 0], r, 0x0 */
+ uint32_t sts_urx_bus_busy : 1; /* [ 1], r, 0x0 */
+ uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } uart_status;
+
+ /* 0x34 : sts_urx_abr_prd */
+
+ union
+ {
+ struct
+ {
+ uint32_t
+ sts_urx_abr_prd_start : 16; /* [15: 0], r, 0x0 */
+ uint32_t
+ sts_urx_abr_prd_0x55 : 16; /* [31:16], r, 0x0 */
+ } bf;
+ uint32_t word;
+ } sts_urx_abr_prd;
+
+ /* 0x38 reserved */
+
+ uint8_t reserved_0x38[72];
+
+ /* 0x80 : uart_fifo_config_0 */
+
+ union
+ {
+ struct
+ {
+ uint32_t uart_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
+ uint32_t uart_dma_rx_en : 1; /* [ 1], r/w, 0x0 */
+ uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */
+ uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */
+ uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */
+ uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */
+ uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */
+ uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } uart_fifo_config_0;
+
+ /* 0x84 : uart_fifo_config_1 */
+
+ union
+ {
+ struct
+ {
+ uint32_t tx_fifo_cnt : 6; /* [ 5: 0], r, 0x20 */
+ uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
+ uint32_t rx_fifo_cnt : 6; /* [13: 8], r, 0x0 */
+ uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
+ uint32_t tx_fifo_th : 5; /* [20:16], r/w, 0x0 */
+ uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */
+ uint32_t rx_fifo_th : 5; /* [28:24], r/w, 0x0 */
+ uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } uart_fifo_config_1;
+
+ /* 0x88 : uart_fifo_wdata */
+
+ union
+ {
+ struct
+ {
+ uint32_t uart_fifo_wdata : 8; /* [ 7: 0], w, x */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } uart_fifo_wdata;
+
+ /* 0x8C : uart_fifo_rdata */
+
+ union
+ {
+ struct
+ {
+ uint32_t uart_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */
+ uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
+ } bf;
+ uint32_t word;
+ } uart_fifo_rdata;
+};
+
+typedef volatile struct uart_reg_s uart_reg_t;
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_BL602_UART_H */
diff --git a/arch/risc-v/src/bl602/hardware/clic.h b/arch/risc-v/src/bl602/hardware/clic.h
new file mode 100644
index 0000000000..00297990aa
--- /dev/null
+++ b/arch/risc-v/src/bl602/hardware/clic.h
@@ -0,0 +1,43 @@
+/****************************************************************************
+ * arch/risc-v/src/bl602/hardware/clic.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_BL602_HARDWARE_CLIC_H
+#define __ARCH_RISCV_SRC_BL602_HARDWARE_CLIC_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CLIC_CTRL_ADDR 0x02000000UL
+#define CLIC_HART0_ADDR 0x02800000UL
+
+#define CLIC_MSIP 0x0000
+#define CLIC_MSIP_size 0x4
+#define CLIC_MTIMECMP 0x4000
+#define CLIC_MTIMECMP_size 0x8
+#define CLIC_MTIME 0xBFF8
+#define CLIC_MTIME_size 0x8
+
+#define CLIC_INTIP 0x000
+#define CLIC_INTIE 0x400
+#define CLIC_INTCFG 0x800
+#define CLIC_CFG 0xc00
+
+#endif /* __ARCH_RISCV_SRC_BL602_HARDWARE_CLIC_H */
diff --git a/boards/Kconfig b/boards/Kconfig
index d0ab91e534..f23383836c 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -74,6 +74,13 @@ config ARCH_BOARD_AXOLOTI
Axoloti synthesizer board based on the STMicro STM32F427IGH6 MCU.
See: http://www.axoloti.com/
+config ARCH_BOARD_BL602EVB
+ bool "BouffaloLab BL602EVB Board"
+ depends on ARCH_CHIP_BL602
+ ---help---
+ This is the board configuration for the port of NuttX to the BouffaloLab BL602EVB
+ board. This board features the RISC-V rv32imfc core
+
config ARCH_BOARD_C5471EVM
bool "Spectrum Digital C5471 evaluation board"
depends on ARCH_CHIP_C5471
@@ -2192,6 +2199,7 @@ config ARCH_BOARD
default "avr32dev1" if ARCH_BOARD_AVR32DEV1
default "axoloti" if ARCH_BOARD_AXOLOTI
default "bambino-200e" if ARCH_BOARD_BAMBINO_200E
+ default "bl602evb" if ARCH_BOARD_BL602EVB
default "c5471evm" if ARCH_BOARD_C5471EVM
default "clicker2-stm32" if ARCH_BOARD_CLICKER2_STM32
default "cloudctrl" if ARCH_BOARD_CLOUDCTRL
@@ -3065,6 +3073,9 @@ endif
if ARCH_BOARD_Z80SIM
source "boards/z80/z80/z80sim/Kconfig"
endif
+if ARCH_BOARD_BL602EVB
+source "boards/risc-v/bl602/bl602evb/Kconfig"
+endif
config BOARD_CRASHDUMP
bool "Enable Board level logging of crash dumps"
diff --git a/boards/risc-v/bl602/bl602evb/Kconfig b/boards/risc-v/bl602/bl602evb/Kconfig
new file mode 100644
index 0000000000..a50ca564ee
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+if ARCH_BOARD_BL602EVB
+
+endif
diff --git a/boards/risc-v/bl602/bl602evb/README.txt b/boards/risc-v/bl602/bl602evb/README.txt
new file mode 100644
index 0000000000..e7bd857d01
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/README.txt
@@ -0,0 +1,28 @@
+1. Download and install toolchain
+
+ $ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz
+
+2. Follow instruction on https://github.com/enjoy-digital/litex to build the vexriscv softcore fpga gateware
+ and flash to arty_a7 board
+
+3. Configure and build NuttX
+
+ $ mkdir ./nuttx; cd ./nuttx
+ $ git clone https://bitbucket.org/nuttx/nuttx.git
+ $ git clone https://bitbucket.org/nuttx/apps.git
+ $ cd nuttx
+ $ make distclean
+ $ ./tools/configure.sh arty_a7:nsh
+ $ make V=1
+
+4. Setup tftp server on your laptop, copy nuttx.bin to your tftpboot directory and change its name to boot.bin
+
+5. Setup the wire connection(uart and tftp) between your board and laptop
+
+6. Run $ minicom -b 1000000 /dev/ttyUSB1 (the default baudrate on litex vexriscv is 1e6)
+ when you see the bios prompt "litex>", type "netboot" and enter soon comes the nsh prompt
+
+7. TODO
+
+ Support GPIO/SPI/I2C/RTC/WDT/PWM
+ Support RISC-V User mode
diff --git a/boards/risc-v/bl602/bl602evb/configs/demo/defconfig b/boards/risc-v/bl602/bl602evb/configs/demo/defconfig
new file mode 100644
index 0000000000..ab8ef23953
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/configs/demo/defconfig
@@ -0,0 +1,1242 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# NuttX/x86_64 Configuration
+#
+
+#
+# Build Setup
+#
+# CONFIG_EXPERIMENTAL is not set
+CONFIG_DEFAULT_SMALL=y
+CONFIG_DEFAULT_TASK_STACKSIZE=2048
+CONFIG_HOST_LINUX=y
+# CONFIG_HOST_MACOS is not set
+# CONFIG_HOST_WINDOWS is not set
+# CONFIG_HOST_OTHER is not set
+
+#
+# Build Configuration
+#
+CONFIG_APPS_DIR="../apps"
+CONFIG_BUILD_FLAT=y
+# CONFIG_BUILD_2PASS is not set
+
+#
+# Binary Output Formats
+#
+CONFIG_INTELHEX_BINARY=y
+# CONFIG_MOTOROLA_SREC is not set
+CONFIG_RAW_BINARY=y
+# CONFIG_UBOOT_UIMAGE is not set
+# CONFIG_DFU_BINARY is not set
+
+#
+# Customize Header Files
+#
+# CONFIG_ARCH_HAVE_STDINT_H is not set
+# CONFIG_ARCH_HAVE_STDBOOL_H is not set
+# CONFIG_ARCH_HAVE_MATH_H is not set
+# CONFIG_ARCH_FLOAT_H is not set
+CONFIG_ARCH_HAVE_STDARG_H=y
+# CONFIG_ARCH_STDARG_H is not set
+CONFIG_ARCH_HAVE_SETJMP=y
+# CONFIG_ARCH_SETJMP_H is not set
+CONFIG_ARCH_NONE_DEBUG_H=y
+# CONFIG_ARCH_DEBUG_H is not set
+# CONFIG_ARCH_CHIP_DEBUG_H is not set
+
+#
+# Debug Options
+#
+CONFIG_DEBUG_ALERT=y
+CONFIG_DEBUG_FEATURES=y
+
+#
+# Debug SYSLOG Output Controls
+#
+# CONFIG_DEBUG_ERROR is not set
+# CONFIG_DEBUG_ASSERTIONS is not set
+
+#
+# Subsystem Debug Options
+#
+# CONFIG_DEBUG_FS is not set
+# CONFIG_DEBUG_GRAPHICS is not set
+# CONFIG_DEBUG_LIB is not set
+# CONFIG_DEBUG_MM is not set
+# CONFIG_DEBUG_POWER is not set
+# CONFIG_DEBUG_SCHED is not set
+
+#
+# OS Function Debug Options
+#
+# CONFIG_DEBUG_IRQ is not set
+
+#
+# Driver Debug Options
+#
+# CONFIG_DEBUG_INPUT is not set
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_DEBUG_PWM is not set
+# CONFIG_DEBUG_TIMER is not set
+CONFIG_ARCH_HAVE_STACKCHECK=y
+CONFIG_STACK_COLORATION=y
+# CONFIG_STACK_CANARIES is not set
+# CONFIG_ARCH_HAVE_HEAPCHECK is not set
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_ARCH_HAVE_CUSTOMOPT=y
+# CONFIG_DEBUG_NOOPT is not set
+# CONFIG_DEBUG_CUSTOMOPT is not set
+CONFIG_DEBUG_FULLOPT=y
+
+#
+# System Type
+#
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_AVR is not set
+# CONFIG_ARCH_HC is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_MISOC is not set
+# CONFIG_ARCH_RENESAS is not set
+CONFIG_ARCH_RISCV=y
+# CONFIG_ARCH_SIM is not set
+# CONFIG_ARCH_X86 is not set
+# CONFIG_ARCH_X86_64 is not set
+# CONFIG_ARCH_XTENSA is not set
+# CONFIG_ARCH_Z16 is not set
+# CONFIG_ARCH_Z80 is not set
+# CONFIG_ARCH_OR1K is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_FAMILY="rv32im"
+CONFIG_ARCH_CHIP="bl602"
+
+#
+# RISC-V Options
+#
+# CONFIG_ARCH_CHIP_FE310 is not set
+# CONFIG_ARCH_CHIP_K210 is not set
+# CONFIG_ARCH_CHIP_LITEX is not set
+# CONFIG_ARCH_CHIP_NR5 is not set
+# CONFIG_ARCH_CHIP_GAP8 is not set
+CONFIG_ARCH_CHIP_BL602=y
+# CONFIG_ARCH_CHIP_RISCV_CUSTOM is not set
+# CONFIG_ARCH_RV32I is not set
+CONFIG_ARCH_RV32IM=y
+# CONFIG_ARCH_RV64GC is not set
+
+#
+# RV32IM Configuration Options
+#
+CONFIG_RV32IM_TOOLCHAIN_GNU_RVGL=y
+# CONFIG_RI5CY_GAP8_TOOLCHAIN is not set
+# CONFIG_RV32IM_HW_MULDIV is not set
+# CONFIG_RV32IM_SYSTEM_CSRRS_SUPPORT is not set
+CONFIG_RV32IM_CUSTOM_IRQ_SUPPORT=y
+
+#
+# BL602 Configuration Options
+#
+
+#
+# BL602 Peripheral Support
+#
+CONFIG_BL602_HAVE_UART0=y
+CONFIG_BL602_UART0=y
+CONFIG_BL602_UART0_TX_PIN=16
+CONFIG_BL602_UART0_RX_PIN=7
+CONFIG_BL602_UART0_RTS_PIN=-1
+CONFIG_BL602_UART0_CTS_PIN=-1
+CONFIG_BL602_HAVE_UART1=y
+CONFIG_BL602_UART1=y
+CONFIG_BL602_UART1_TX_PIN=4
+CONFIG_BL602_UART1_RX_PIN=1
+CONFIG_BL602_UART1_RTS_PIN=-2
+CONFIG_BL602_UART1_CTS_PIN=-1
+CONFIG_BL602_TIMER0=y
+# CONFIG_BL602_TIMER1 is not set
+CONFIG_ARCH_BOARD="bl602evb"
+# CONFIG_ARCH_CHIP_CUSTOM is not set
+# CONFIG_ARCH_TOOLCHAIN_IAR is not set
+CONFIG_ARCH_TOOLCHAIN_GNU=y
+# CONFIG_ARCH_GNU_NO_WEAKFUNCTIONS is not set
+# CONFIG_ARCH_SIZET_LONG is not set
+
+#
+# Architecture Options
+#
+# CONFIG_ARCH_NOINTC is not set
+# CONFIG_ARCH_VECNOTIRQ is not set
+# CONFIG_ARCH_HAVE_IRQTRIGGER is not set
+# CONFIG_ARCH_DMA is not set
+# CONFIG_ARCH_HAVE_IRQPRIO is not set
+# CONFIG_ARCH_ICACHE is not set
+# CONFIG_ARCH_DCACHE is not set
+# CONFIG_ARCH_L2CACHE is not set
+# CONFIG_ARCH_HAVE_ADDRENV is not set
+# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set
+# CONFIG_ARCH_HAVE_MODULE_TEXT is not set
+# CONFIG_ARCH_HAVE_MULTICPU is not set
+# CONFIG_ARCH_HAVE_VFORK is not set
+# CONFIG_ARCH_HAVE_FPU is not set
+# CONFIG_ARCH_HAVE_DPFPU is not set
+# CONFIG_ARCH_HAVE_MMU is not set
+# CONFIG_ARCH_HAVE_MPU is not set
+# CONFIG_ARCH_NAND_HWECC is not set
+# CONFIG_ARCH_HAVE_EXTCLK is not set
+# CONFIG_ARCH_HAVE_POWEROFF is not set
+# CONFIG_ARCH_HAVE_PROGMEM is not set
+# CONFIG_ARCH_HAVE_RESET is not set
+# CONFIG_ARCH_HAVE_TESTSET is not set
+# CONFIG_ARCH_HAVE_FETCHADD is not set
+# CONFIG_ARCH_HAVE_RTC_SUBSECONDS is not set
+CONFIG_ARCH_HAVE_SYSCALL_HOOKS=y
+CONFIG_ARCH_STACKDUMP=y
+# CONFIG_ARCH_IDLE_CUSTOM is not set
+# CONFIG_ARCH_HAVE_RAMFUNCS is not set
+# CONFIG_ARCH_HAVE_RAMVECTORS is not set
+# CONFIG_ARCH_MINIMAL_VECTORTABLE is not set
+
+#
+# Board Settings
+#
+CONFIG_BOARD_LOOPSPERMSEC=10000
+
+#
+# Interrupt options
+#
+CONFIG_ARCH_HAVE_INTERRUPTSTACK=y
+CONFIG_ARCH_INTERRUPTSTACK=8192
+# CONFIG_ARCH_HAVE_HIPRI_INTERRUPT is not set
+
+#
+# Boot options
+#
+# CONFIG_BOOT_RUNFROMEXTSRAM is not set
+CONFIG_BOOT_RUNFROMFLASH=y
+# CONFIG_BOOT_RUNFROMISRAM is not set
+# CONFIG_BOOT_RUNFROMSDRAM is not set
+# CONFIG_BOOT_COPYTORAM is not set
+
+#
+# Boot Memory Configuration
+#
+CONFIG_RAM_START=0xc0800000
+CONFIG_RAM_SIZE=134217728
+# CONFIG_ARCH_HAVE_SDRAM is not set
+
+#
+# Board Selection
+#
+CONFIG_ARCH_BOARD_BL602EVB=y
+# CONFIG_ARCH_BOARD_CUSTOM is not set
+
+#
+# Common Board Options
+#
+
+#
+# Board-Specific Options
+#
+# CONFIG_BOARD_CRASHDUMP is not set
+CONFIG_LIB_BOARDCTL=y
+# CONFIG_BOARDCTL_FINALINIT is not set
+# CONFIG_BOARDCTL_UNIQUEID is not set
+# CONFIG_BOARDCTL_MKRD is not set
+# CONFIG_BOARDCTL_ROMDISK is not set
+# CONFIG_BOARDCTL_APP_SYMTAB is not set
+# CONFIG_BOARDCTL_TESTSET is not set
+# CONFIG_BOARDCTL_IOCTL is not set
+
+#
+# RTOS Features
+#
+CONFIG_DISABLE_OS_API=y
+CONFIG_DISABLE_POSIX_TIMERS=y
+# CONFIG_DISABLE_PTHREAD is not set
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_DISABLE_ENVIRON=y
+
+#
+# Clocks and Timers
+#
+CONFIG_ARCH_HAVE_TICKLESS=y
+# CONFIG_SCHED_TICKLESS is not set
+CONFIG_USEC_PER_TICK=10000
+# CONFIG_SYSTEMTICK_HOOK is not set
+# CONFIG_SYSTEM_TIME64 is not set
+# CONFIG_CLOCK_MONOTONIC is not set
+CONFIG_ARCH_HAVE_TIMEKEEPING=y
+# CONFIG_JULIAN_TIME is not set
+CONFIG_START_YEAR=2020
+CONFIG_START_MONTH=3
+CONFIG_START_DAY=20
+CONFIG_PREALLOC_TIMERS=0
+
+#
+# Tasks and Scheduling
+#
+# CONFIG_SPINLOCK_IRQ is not set
+# CONFIG_IRQCHAIN is not set
+# CONFIG_IRQCOUNT is not set
+# CONFIG_INIT_NONE is not set
+CONFIG_INIT_ENTRYPOINT=y
+CONFIG_INIT_ARGS=""
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_USERMAIN_STACKSIZE=8192
+CONFIG_USERMAIN_PRIORITY=100
+CONFIG_RR_INTERVAL=200
+# CONFIG_SCHED_SPORADIC is not set
+CONFIG_TASK_NAME_SIZE=12
+CONFIG_MAX_TASKS=8
+# CONFIG_SCHED_HAVE_PARENT is not set
+CONFIG_SCHED_WAITPID=y
+# CONFIG_SCHED_USER_IDENTITY is not set
+
+#
+# Pthread Options
+#
+# CONFIG_PTHREAD_MUTEX_TYPES is not set
+# CONFIG_PTHREAD_MUTEX_ROBUST is not set
+CONFIG_PTHREAD_MUTEX_UNSAFE=y
+# CONFIG_PTHREAD_MUTEX_BOTH is not set
+# CONFIG_PTHREAD_CLEANUP is not set
+# CONFIG_CANCELLATION_POINTS is not set
+
+#
+# Performance Monitoring
+#
+# CONFIG_SCHED_SUSPENDSCHEDULER is not set
+# CONFIG_SCHED_RESUMESCHEDULER is not set
+# CONFIG_SCHED_IRQMONITOR is not set
+# CONFIG_SCHED_CRITMONITOR is not set
+CONFIG_SCHED_CPULOAD=y
+CONFIG_SCHED_CPULOAD_EXTCLK=y
+CONFIG_SCHED_CPULOAD_TICKSPERSEC=100
+CONFIG_CPULOAD_ONESHOT=y
+# CONFIG_CPULOAD_PERIOD is not set
+CONFIG_CPULOAD_ENTROPY=6
+CONFIG_SCHED_CPULOAD_TIMECONSTANT=2
+# CONFIG_SCHED_INSTRUMENTATION is not set
+
+#
+# Files and I/O
+#
+CONFIG_DEV_CONSOLE=y
+# CONFIG_FDCLONE_DISABLE is not set
+# CONFIG_FDCLONE_STDIO is not set
+# CONFIG_SDCLONE_DISABLE is not set
+CONFIG_NFILE_DESCRIPTORS=6
+CONFIG_FILE_STREAM=y
+CONFIG_NAME_MAX=32
+CONFIG_PATH_MAX=256
+# CONFIG_PRIORITY_INHERITANCE is not set
+
+#
+# RTOS hooks
+#
+# CONFIG_BOARD_EARLY_INITIALIZE is not set
+# CONFIG_BOARD_LATE_INITIALIZE is not set
+# CONFIG_SCHED_STARTHOOK is not set
+# CONFIG_SCHED_ATEXIT is not set
+# CONFIG_SCHED_ONEXIT is not set
+
+#
+# Signal Configuration
+#
+# CONFIG_SIG_DEFAULT is not set
+
+#
+# Signal Numbers
+#
+
+#
+# Standard Signal Numbers
+#
+CONFIG_SIG_SIGUSR1=1
+CONFIG_SIG_SIGUSR2=2
+CONFIG_SIG_SIGALRM=3
+CONFIG_SIG_PIPE=13
+
+#
+# Non-standard Signal Numbers
+#
+CONFIG_SIG_SIGCONDTIMEDOUT=16
+# CONFIG_MODULE is not set
+
+#
+# Work queue support
+#
+# CONFIG_SCHED_WORKQUEUE is not set
+# CONFIG_SCHED_HPWORK is not set
+# CONFIG_SCHED_LPWORK is not set
+
+#
+# Stack and heap information
+#
+CONFIG_IDLETHREAD_STACKSIZE=8192
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=8192
+# CONFIG_LIB_SYSCALL is not set
+
+#
+# Device Drivers
+#
+# CONFIG_DEV_SIMPLE_ADDRENV is not set
+CONFIG_DEV_NULL=y
+CONFIG_DEV_ZERO=y
+# CONFIG_DRVR_MKRD is not set
+
+#
+# Buffering
+#
+# CONFIG_DRVR_WRITEBUFFER is not set
+# CONFIG_DRVR_READAHEAD is not set
+# CONFIG_SPECIFIC_DRIVERS is not set
+# CONFIG_DEV_URANDOM is not set
+# CONFIG_DEV_LOOP is not set
+# CONFIG_ARCH_HAVE_CAN_ERRORS is not set
+# CONFIG_CAN is not set
+# CONFIG_ARCH_HAVE_I2CRESET is not set
+# CONFIG_I2C is not set
+# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set
+# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set
+# CONFIG_ARCH_HAVE_SPI_BITORDER is not set
+# CONFIG_SPI is not set
+# CONFIG_I2S is not set
+
+#
+# Timer Driver Support
+#
+# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set
+# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set
+CONFIG_PWM=y
+CONFIG_TIMER=y
+CONFIG_TIMER_ARCH=y
+CONFIG_ONESHOT=y
+CONFIG_ALARM_ARCH=y
+# CONFIG_RTC is not set
+# CONFIG_WATCHDOG is not set
+# CONFIG_ANALOG is not set
+# CONFIG_DRIVERS_AUDIO is not set
+# CONFIG_FB_CMAP is not set
+# CONFIG_FB_TRANSPARENCY is not set
+# CONFIG_FB_UPDATE is not set
+# CONFIG_FB_SYNC is not set
+# CONFIG_FB_OVERLAY is not set
+# CONFIG_DRIVERS_VIDEO is not set
+# CONFIG_BCH is not set
+CONFIG_INPUT=y
+# CONFIG_MOUSE is not set
+# CONFIG_INPUT_MAX11802 is not set
+# CONFIG_INPUT_TSC2007 is not set
+# CONFIG_INPUT_FT5X06 is not set
+# CONFIG_INPUT_ADS7843E is not set
+# CONFIG_INPUT_MXT is not set
+# CONFIG_INPUT_STMPE811 is not set
+# CONFIG_INPUT_CYPRESS_MBR3108 is not set
+# CONFIG_BUTTONS is not set
+# CONFIG_DJOYSTICK is not set
+# CONFIG_AJOYSTICK is not set
+# CONFIG_INPUT_NUNCHUCK is not set
+# CONFIG_INPUT_SPQ10KBD is not set
+
+#
+# IO Expander/GPIO Support
+#
+CONFIG_IOEXPANDER=y
+# CONFIG_IOEXPANDER_INT_ENABLE is not set
+CONFIG_IOEXPANDER_NPINS=16
+# CONFIG_IOEXPANDER_MULTIPIN is not set
+CONFIG_DEV_GPIO=y
+CONFIG_DEV_GPIO_NSIGNALS=1
+# CONFIG_GPIO_LOWER_HALF is not set
+
+#
+# LCD Driver Support
+#
+# CONFIG_LCD is not set
+
+#
+# Character/Segment LCD Devices
+#
+# CONFIG_SLCD is not set
+
+#
+# Other LCD-related Devices
+#
+# CONFIG_LCD_OTHER is not set
+
+#
+# LED Support
+#
+# CONFIG_USERLED is not set
+# CONFIG_LEDS_APA102 is not set
+# CONFIG_LEDS_MAX7219 is not set
+# CONFIG_RGBLED is not set
+# CONFIG_PCA9635PW is not set
+# CONFIG_NCP5623C is not set
+# CONFIG_WS2812 is not set
+# CONFIG_ARCH_HAVE_SDIO is not set
+# CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE is not set
+# CONFIG_ARCH_HAVE_SDIO_PREFLIGHT is not set
+# CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT is not set
+# CONFIG_MMCSD is not set
+# CONFIG_MODEM is not set
+CONFIG_MTD=y
+CONFIG_MTD_PARTITION=y
+CONFIG_MTD_SECT512=y
+CONFIG_MTD_SECT512_ERASED_STATE=0xff
+# CONFIG_MTD_SECT512_READONLY is not set
+# CONFIG_MTD_PARTITION_NAMES is not set
+# CONFIG_MTD_BYTE_WRITE is not set
+# CONFIG_MTD_PROGMEM is not set
+# CONFIG_MTD_CONFIG is not set
+
+#
+# MTD Device Drivers
+#
+# CONFIG_MTD_NAND is not set
+# CONFIG_RAMMTD is not set
+# CONFIG_FILEMTD is not set
+# CONFIG_MTD_AT24XX is not set
+# CONFIG_MTD_AT25 is not set
+# CONFIG_MTD_AT45DB is not set
+# CONFIG_MTD_IS25XP is not set
+# CONFIG_MTD_M25P is not set
+# CONFIG_MTD_MX25L is not set
+# CONFIG_MTD_MX35 is not set
+# CONFIG_MTD_S25FL1 is not set
+# CONFIG_MTD_N25QXXX is not set
+# CONFIG_MTD_W25QXXXJV is not set
+# CONFIG_MTD_MX25RXX is not set
+# CONFIG_MTD_SMART is not set
+# CONFIG_MTD_RAMTRON is not set
+# CONFIG_MTD_SST25 is not set
+# CONFIG_MTD_SST25XX is not set
+# CONFIG_MTD_SST26 is not set
+# CONFIG_MTD_SST39FV is not set
+# CONFIG_MTD_W25 is not set
+# CONFIG_MTD_GD25 is not set
+# CONFIG_MTD_GD5F is not set
+# CONFIG_EEPROM is not set
+# CONFIG_PIPES is not set
+# CONFIG_PM is not set
+# CONFIG_DRIVERS_POWERLED is not set
+# CONFIG_DRIVERS_SMPS is not set
+# CONFIG_DRIVERS_MOTOR is not set
+# CONFIG_POWER is not set
+# CONFIG_SENSORS is not set
+CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_REMOVABLE is not set
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_16550_UART is not set
+# CONFIG_OTHER_UART_SERIALDRIVER is not set
+CONFIG_MCU_SERIAL=y
+# CONFIG_STANDARD_SERIAL is not set
+# CONFIG_SERIAL_IFLOWCONTROL is not set
+# CONFIG_SERIAL_RS485CONTROL is not set
+# CONFIG_SERIAL_OFLOWCONTROL is not set
+# CONFIG_SERIAL_TXDMA is not set
+# CONFIG_SERIAL_RXDMA is not set
+# CONFIG_SERIAL_TIOCSERGSTRUCT is not set
+# CONFIG_SERIAL_TERMIOS is not set
+CONFIG_UART0_SERIAL_CONSOLE=y
+# CONFIG_UART1_SERIAL_CONSOLE is not set
+# CONFIG_OTHER_SERIAL_CONSOLE is not set
+# CONFIG_NO_SERIAL_CONSOLE is not set
+# CONFIG_UART_SERIALDRIVER is not set
+CONFIG_UART0_SERIALDRIVER=y
+CONFIG_UART1_SERIALDRIVER=y
+# CONFIG_UART2_SERIALDRIVER is not set
+# CONFIG_UART3_SERIALDRIVER is not set
+# CONFIG_UART4_SERIALDRIVER is not set
+# CONFIG_UART5_SERIALDRIVER is not set
+# CONFIG_UART6_SERIALDRIVER is not set
+# CONFIG_UART7_SERIALDRIVER is not set
+# CONFIG_UART8_SERIALDRIVER is not set
+
+#
+# UART0 Configuration
+#
+CONFIG_UART0_RXBUFSIZE=128
+CONFIG_UART0_TXBUFSIZE=128
+CONFIG_UART0_BAUD=2000000
+CONFIG_UART0_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART0_2STOP=0
+# CONFIG_UART0_IFLOWCONTROL is not set
+# CONFIG_UART0_OFLOWCONTROL is not set
+# CONFIG_UART0_RXDMA is not set
+# CONFIG_UART0_TXDMA is not set
+
+#
+# UART1 Configuration
+#
+CONFIG_UART1_RXBUFSIZE=256
+CONFIG_UART1_TXBUFSIZE=256
+CONFIG_UART1_BAUD=115200
+CONFIG_UART1_BITS=8
+CONFIG_UART1_PARITY=0
+CONFIG_UART1_2STOP=0
+# CONFIG_UART1_IFLOWCONTROL is not set
+# CONFIG_UART1_OFLOWCONTROL is not set
+# CONFIG_UART1_RXDMA is not set
+# CONFIG_UART1_TXDMA is not set
+# CONFIG_LPUART_SERIALDRIVER is not set
+# CONFIG_LPUART0_SERIALDRIVER is not set
+# CONFIG_LPUART1_SERIALDRIVER is not set
+# CONFIG_LPUART2_SERIALDRIVER is not set
+# CONFIG_LPUART3_SERIALDRIVER is not set
+# CONFIG_LPUART4_SERIALDRIVER is not set
+# CONFIG_LPUART5_SERIALDRIVER is not set
+# CONFIG_LPUART6_SERIALDRIVER is not set
+# CONFIG_LPUART7_SERIALDRIVER is not set
+# CONFIG_LPUART8_SERIALDRIVER is not set
+# CONFIG_USART0_SERIALDRIVER is not set
+# CONFIG_USART1_SERIALDRIVER is not set
+# CONFIG_USART2_SERIALDRIVER is not set
+# CONFIG_USART3_SERIALDRIVER is not set
+# CONFIG_USART4_SERIALDRIVER is not set
+# CONFIG_USART5_SERIALDRIVER is not set
+# CONFIG_USART6_SERIALDRIVER is not set
+# CONFIG_USART7_SERIALDRIVER is not set
+# CONFIG_USART8_SERIALDRIVER is not set
+# CONFIG_USART9_SERIALDRIVER is not set
+# CONFIG_SCI0_SERIALDRIVER is not set
+# CONFIG_SCI1_SERIALDRIVER is not set
+# CONFIG_SCI2_SERIALDRIVER is not set
+# CONFIG_SCI3_SERIALDRIVER is not set
+# CONFIG_SCI4_SERIALDRIVER is not set
+# CONFIG_SCI5_SERIALDRIVER is not set
+# CONFIG_SCI6_SERIALDRIVER is not set
+# CONFIG_SCI7_SERIALDRIVER is not set
+# CONFIG_SCI8_SERIALDRIVER is not set
+# CONFIG_SCI9_SERIALDRIVER is not set
+# CONFIG_SCI10_SERIALDRIVER is not set
+# CONFIG_SCI11_SERIALDRIVER is not set
+# CONFIG_SCI12_SERIALDRIVER is not set
+# CONFIG_PSEUDOTERM is not set
+# CONFIG_USBDEV is not set
+# CONFIG_USBHOST_HAVE_ASYNCH is not set
+# CONFIG_USBHOST is not set
+# CONFIG_USBMISC is not set
+# CONFIG_HAVE_USBTRACE is not set
+# CONFIG_DRIVERS_WIRELESS is not set
+# CONFIG_DRIVERS_CONTACTLESS is not set
+# CONFIG_1WIRE is not set
+
+#
+# System Logging
+#
+# CONFIG_ARCH_SYSLOG is not set
+# CONFIG_SYSLOG_WRITE is not set
+# CONFIG_RAMLOG is not set
+# CONFIG_SYSLOG_INTBUFFER is not set
+# CONFIG_SYSLOG_TIMESTAMP is not set
+# CONFIG_SYSLOG_PREFIX is not set
+# CONFIG_SYSLOG_CHAR is not set
+# CONFIG_SYSLOG_CONSOLE is not set
+CONFIG_SYSLOG_DEFAULT=y
+# CONFIG_SYSLOG_FILE is not set
+# CONFIG_CONSOLE_SYSLOG is not set
+# CONFIG_SYSLOG_CHARDEV is not set
+# CONFIG_DRIVERS_RF is not set
+# CONFIG_DRIVERS_RC is not set
+
+#
+# Networking Support
+#
+# CONFIG_ARCH_HAVE_NET is not set
+# CONFIG_ARCH_HAVE_PHY is not set
+# CONFIG_ARCH_PHY_INTERRUPT is not set
+# CONFIG_ARCH_PHY_POLLED is not set
+# CONFIG_ARCH_HAVE_NETDEV_STATISTICS is not set
+# CONFIG_NET_WRITE_BUFFERS is not set
+# CONFIG_NET_READAHEAD is not set
+# CONFIG_NET_MCASTGROUP is not set
+# CONFIG_NET is not set
+
+#
+# Crypto API
+#
+# CONFIG_CRYPTO is not set
+
+#
+# File Systems
+#
+
+#
+# File system configuration
+#
+# CONFIG_DISABLE_MOUNTPOINT is not set
+# CONFIG_FS_AUTOMOUNTER is not set
+CONFIG_FS_NEPOLL_DESCRIPTORS=8
+CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y
+# CONFIG_EVENT_FD is not set
+# CONFIG_FS_NAMED_SEMAPHORES is not set
+# CONFIG_FS_RAMMAP is not set
+
+#
+# Partition Table
+#
+CONFIG_PTABLE_PARTITION=y
+# CONFIG_FS_FAT is not set
+# CONFIG_NFS is not set
+# CONFIG_FS_NXFFS is not set
+# CONFIG_FS_ROMFS is not set
+# CONFIG_FS_CROMFS is not set
+# CONFIG_FS_TMPFS is not set
+# CONFIG_FS_SMARTFS is not set
+# CONFIG_FS_BINFS is not set
+CONFIG_FS_PROCFS=y
+# CONFIG_FS_PROCFS_REGISTER is not set
+
+#
+# Exclude individual procfs entries
+#
+# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set
+CONFIG_FS_PROCFS_EXCLUDE_ENVIRON=y
+# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set
+# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set
+# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set
+# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set
+# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set
+# CONFIG_FS_PROCFS_EXCLUDE_CPULOAD is not set
+# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set
+# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set
+# CONFIG_FS_PROCFS_EXCLUDE_PARTITIONS is not set
+# CONFIG_FS_SPIFFS is not set
+CONFIG_FS_LITTLEFS=y
+# CONFIG_FS_UNIONFS is not set
+# CONFIG_FS_HOSTFS is not set
+
+#
+# Graphics Support
+#
+# CONFIG_NX is not set
+# CONFIG_NXFONTS is not set
+
+#
+# Font Cache Pixel Depths
+#
+# CONFIG_NXFONTS_DISABLE_1BPP is not set
+# CONFIG_NXFONTS_DISABLE_2BPP is not set
+# CONFIG_NXFONTS_DISABLE_4BPP is not set
+# CONFIG_NXFONTS_DISABLE_8BPP is not set
+# CONFIG_NXFONTS_DISABLE_16BPP is not set
+# CONFIG_NXFONTS_DISABLE_24BPP is not set
+# CONFIG_NXFONTS_DISABLE_32BPP is not set
+CONFIG_NXFONTS_PACKEDMSFIRST=y
+# CONFIG_NXGLIB is not set
+
+#
+# Memory Management
+#
+# CONFIG_MM_SMALL is not set
+CONFIG_MM_REGIONS=1
+# CONFIG_ARCH_HAVE_HEAP2 is not set
+# CONFIG_GRAN is not set
+# CONFIG_MM_FILL_ALLOCATIONS is not set
+# CONFIG_MM_CIRCBUF is not set
+
+#
+# Common I/O Buffer Support
+#
+# CONFIG_MM_IOB is not set
+
+#
+# Audio Support
+#
+# CONFIG_AUDIO is not set
+
+#
+# Video Support
+#
+
+#
+# Video subsystem
+#
+# CONFIG_VIDEO is not set
+
+#
+# Wireless Support
+#
+# CONFIG_WIRELESS is not set
+
+#
+# Binary Loader
+#
+CONFIG_BINFMT_DISABLE=y
+# CONFIG_SYMTAB_ORDEREDBYNAME is not set
+
+#
+# Library Routines
+#
+
+#
+# Standard C Library Options
+#
+
+#
+# Standard C I/O
+#
+CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_NUNGET_CHARS=2
+# CONFIG_LIBC_PRINT_LEGACY is not set
+# CONFIG_LIBC_FLOATINGPOINT is not set
+# CONFIG_LIBC_LONG_LONG is not set
+# CONFIG_LIBC_SCANSET is not set
+# CONFIG_EOL_IS_CR is not set
+# CONFIG_EOL_IS_LF is not set
+# CONFIG_EOL_IS_BOTH_CRLF is not set
+CONFIG_EOL_IS_EITHER_CRLF=y
+# CONFIG_AUDIO_SRC is not set
+# CONFIG_LIBM is not set
+
+#
+# Architecture-Specific Support
+#
+CONFIG_ARCH_LOWPUTC=y
+# CONFIG_ARCH_ROMGETC is not set
+# CONFIG_LIBC_ARCH_MEMCPY is not set
+# CONFIG_LIBC_ARCH_MEMCMP is not set
+# CONFIG_LIBC_ARCH_MEMMOVE is not set
+# CONFIG_LIBC_ARCH_MEMSET is not set
+# CONFIG_LIBC_ARCH_STRCHR is not set
+# CONFIG_LIBC_ARCH_STRCMP is not set
+# CONFIG_LIBC_ARCH_STRCPY is not set
+# CONFIG_LIBC_ARCH_STRLCPY is not set
+# CONFIG_LIBC_ARCH_STRNCPY is not set
+# CONFIG_LIBC_ARCH_STRLEN is not set
+# CONFIG_LIBC_ARCH_STRNLEN is not set
+# CONFIG_LIBC_ARCH_ELF is not set
+
+#
+# stdlib Options
+#
+CONFIG_LIB_RAND_ORDER=1
+CONFIG_LIBC_TMPDIR="/tmp"
+CONFIG_LIBC_MAX_TMPFILE=32
+
+#
+# Program Execution Options
+#
+CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=8192
+CONFIG_LIB_HOSTNAME=""
+
+#
+# errno Decode Support
+#
+CONFIG_LIBC_STRERROR=y
+# CONFIG_LIBC_STRERROR_SHORT is not set
+CONFIG_LIBC_PERROR_STDOUT=y
+
+#
+# memcpy/memset Options
+#
+# CONFIG_MEMCPY_VIK is not set
+# CONFIG_MEMSET_OPTSPEED is not set
+
+#
+# pthread support
+#
+# CONFIG_LIBC_DLFCN is not set
+# CONFIG_LIBC_MODLIB is not set
+# CONFIG_LIBC_GROUP_FILE is not set
+# CONFIG_LIBC_PASSWD_FILE is not set
+# CONFIG_LIBC_WCHAR is not set
+# CONFIG_LIBC_LOCALE is not set
+# CONFIG_LIBC_LZF is not set
+
+#
+# Time/Time Zone Support
+#
+
+#
+# Thread Local Storage (TLS)
+#
+# CONFIG_TLS_ALIGNED is not set
+CONFIG_TLS_NELEM=4
+
+#
+# Network-Related Options
+#
+# CONFIG_LIBC_IPv4_ADDRCONV is not set
+# CONFIG_LIBC_IPv6_ADDRCONV is not set
+# CONFIG_LIBC_NETDB is not set
+
+#
+# NETDB Support
+#
+# CONFIG_LIBC_GAISTRERROR is not set
+CONFIG_NETDB_BUFSIZE=256
+CONFIG_NETDB_MAX_IPADDR=1
+# CONFIG_NETDB_HOSTFILE is not set
+CONFIG_LIB_SENDFILE_BUFSIZE=512
+
+#
+# Non-standard Library Support
+#
+# CONFIG_LIB_CRC64_FAST is not set
+# CONFIG_LIB_KBDCODEC is not set
+# CONFIG_LIB_SLCDCODEC is not set
+# CONFIG_LIB_HEX2BIN is not set
+CONFIG_BUILTIN=y
+
+#
+# Basic CXX Support
+#
+# CONFIG_C99_BOOL8 is not set
+# CONFIG_HAVE_CXX is not set
+# CONFIG_LIBDSP is not set
+
+#
+# Open Asymmetric Multi Processing
+#
+# CONFIG_OPENAMP is not set
+
+#
+# Application Configuration
+#
+
+#
+# CAN Utilities
+#
+
+#
+# Examples
+#
+# CONFIG_EXAMPLES_ABNTCODI is not set
+# CONFIG_EXAMPLES_ADXL372_TEST is not set
+# CONFIG_EXAMPLES_APA102 is not set
+# CONFIG_EXAMPLES_AUDIO_SOUND is not set
+# CONFIG_EXAMPLES_BATTERY is not set
+# CONFIG_EXAMPLES_SIXAXIS is not set
+# CONFIG_EXAMPLES_CALIB_UDELAY is not set
+# CONFIG_EXAMPLES_CAMERA is not set
+# CONFIG_EXAMPLES_CCTYPE is not set
+# CONFIG_EXAMPLES_CHARGER is not set
+# CONFIG_EXAMPLES_CHAT is not set
+# CONFIG_EXAMPLES_CHRONO is not set
+# CONFIG_EXAMPLES_CONFIGDATA is not set
+# CONFIG_EXAMPLES_DHCPD is not set
+# CONFIG_EXAMPLES_DHTXX is not set
+# CONFIG_EXAMPLES_DSPTEST is not set
+# CONFIG_EXAMPLES_ESP32_HIMEM is not set
+# CONFIG_EXAMPLES_FTPC is not set
+# CONFIG_EXAMPLES_FTPD is not set
+# CONFIG_EXAMPLES_FXOS8700CQ is not set
+CONFIG_EXAMPLES_GPIO=y
+CONFIG_EXAMPLES_GPIO_PROGNAME="gpio"
+CONFIG_EXAMPLES_GPIO_PRIORITY=100
+CONFIG_EXAMPLES_GPIO_STACKSIZE=2048
+# CONFIG_EXAMPLES_GPS is not set
+# CONFIG_EXAMPLES_HDC1008 is not set
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_EXAMPLES_HELLO_PROGNAME="hello"
+CONFIG_EXAMPLES_HELLO_PRIORITY=100
+CONFIG_EXAMPLES_HELLO_STACKSIZE=8192
+# CONFIG_EXAMPLES_HIDKBD is not set
+# CONFIG_EXAMPLES_IGMP is not set
+# CONFIG_EXAMPLES_INA219 is not set
+# CONFIG_EXAMPLES_INA226 is not set
+# CONFIG_EXAMPLES_LSM330SPI_TEST is not set
+# CONFIG_EXAMPLES_LVGLDEMO is not set
+# CONFIG_EXAMPLES_MAX31855 is not set
+# CONFIG_EXAMPLES_MEDIA is not set
+# CONFIG_EXAMPLES_MLX90614 is not set
+# CONFIG_EXAMPLES_MODBUS is not set
+# CONFIG_EXAMPLES_MODBUSMASTER is not set
+# CONFIG_EXAMPLES_MOUNT is not set
+# CONFIG_EXAMPLES_MTDPART is not set
+# CONFIG_EXAMPLES_NULL is not set
+# CONFIG_EXAMPLES_NXDEMO is not set
+# CONFIG_EXAMPLES_OBD2 is not set
+CONFIG_EXAMPLES_ONESHOT=y
+CONFIG_EXAMPLES_ONESHOT_DEVNAME="/dev/oneshot"
+CONFIG_EXAMPLES_ONESHOT_DELAY=100000
+CONFIG_EXAMPLES_ONESHOT_SIGNO=13
+CONFIG_EXAMPLES_ONESHOT_STACKSIZE=2048
+CONFIG_EXAMPLES_ONESHOT_PRIORITY=100
+CONFIG_EXAMPLES_ONESHOT_PROGNAME="oneshot"
+# CONFIG_EXAMPLES_PCA9635 is not set
+# CONFIG_EXAMPLES_PDCURSES is not set
+# CONFIG_EXAMPLES_POSIXSPAWN is not set
+# CONFIG_EXAMPLES_POWERLED is not set
+# CONFIG_EXAMPLES_POWERMONITOR is not set
+# CONFIG_EXAMPLES_PPPD is not set
+# CONFIG_EXAMPLES_PWM is not set
+# CONFIG_EXAMPLES_RFID_READUID is not set
+# CONFIG_EXAMPLES_RGBLED is not set
+CONFIG_EXAMPLES_SERIALBLASTER=y
+CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048
+CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50
+CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2"
+CONFIG_EXAMPLES_SERIALRX=y
+CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048
+CONFIG_EXAMPLES_SERIALRX_PRIORITY=50
+# CONFIG_EXAMPLES_SERIALRX_BUFFERED is not set
+CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520
+CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0"
+CONFIG_EXAMPLES_SERIALRX_PRINTHYPHEN=y
+# CONFIG_EXAMPLES_SERIALRX_PRINTHEX is not set
+# CONFIG_EXAMPLES_SERIALRX_PRINTSTR is not set
+CONFIG_EXAMPLES_SERLOOP=y
+# CONFIG_EXAMPLES_SLCD is not set
+# CONFIG_EXAMPLES_SMPS is not set
+# CONFIG_EXAMPLES_STAT is not set
+# CONFIG_EXAMPLES_TCPECHO is not set
+# CONFIG_EXAMPLES_TIFF is not set
+CONFIG_EXAMPLES_TIMER=y
+CONFIG_EXAMPLES_TIMER_DEVNAME="/dev/timer0"
+CONFIG_EXAMPLES_TIMER_INTERVAL=1000000
+CONFIG_EXAMPLES_TIMER_DELAY=100000
+CONFIG_EXAMPLES_TIMER_NSAMPLES=20
+CONFIG_EXAMPLES_TIMER_SIGNO=17
+CONFIG_EXAMPLES_TIMER_STACKSIZE=2048
+CONFIG_EXAMPLES_TIMER_PRIORITY=100
+CONFIG_EXAMPLES_TIMER_PROGNAME="timer"
+# CONFIG_EXAMPLES_TOUCHSCREEN is not set
+# CONFIG_EXAMPLES_UID is not set
+# CONFIG_EXAMPLES_USBSERIAL is not set
+# CONFIG_EXAMPLES_USERFS is not set
+# CONFIG_EXAMPLES_WATCHDOG is not set
+# CONFIG_EXAMPLES_WEBSERVER is not set
+# CONFIG_EXAMPLES_XBC_TEST is not set
+
+#
+# File System Utilities
+#
+# CONFIG_FSUTILS_FLASH_ERASEALL is not set
+# CONFIG_FSUTILS_INIFILE is not set
+# CONFIG_FSUTILS_INIH is not set
+# CONFIG_FSUTILS_PASSWD is not set
+
+#
+# GPS Utilities
+#
+# CONFIG_GPSUTILS_MINMEA_LIB is not set
+
+#
+# Graphics Support
+#
+# CONFIG_GRAPHICS_FT80X is not set
+# CONFIG_GRAPHICS_LVGL is not set
+
+#
+# NxWidgets
+#
+
+#
+# NxWM
+#
+# CONFIG_GRAPHICS_PDCURSES is not set
+# CONFIG_TIFF is not set
+
+#
+# Industrial Applications
+#
+# CONFIG_INDUSTRY_ABNT_CODI_LIB is not set
+
+#
+# Interpreters
+#
+# CONFIG_INTERPRETERS_BAS is not set
+# CONFIG_INTERPRETERS_DUKTAPE is not set
+# CONFIG_INTERPRETERS_FICL is not set
+# CONFIG_INTERPRETERS_MINIBASIC is not set
+# CONFIG_INTERPRETERS_QUICKJS is not set
+# CONFIG_INTERPRETERS_WAMR is not set
+# CONFIG_INTERPRETERS_WASM3 is not set
+
+#
+# FreeModBus
+#
+# CONFIG_MODBUS is not set
+
+#
+# Network Utilities
+#
+# CONFIG_NETUTILS_CHAT is not set
+# CONFIG_NETUTILS_CJSON is not set
+# CONFIG_NETUTILS_CODECS is not set
+# CONFIG_NETUTILS_ESP8266 is not set
+# CONFIG_NETUTILS_FTPC is not set
+
+#
+# NSH Library
+#
+CONFIG_NSH_LIBRARY=y
+# CONFIG_NSH_MOTD is not set
+
+#
+# Command Line Configuration
+#
+CONFIG_NSH_PROMPT_STRING="nsh> "
+CONFIG_NSH_READLINE=y
+# CONFIG_NSH_CLE is not set
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_DISABLE_SEMICOLON=y
+# CONFIG_NSH_QUOTE is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_NSH_MAXARGUMENTS=7
+# CONFIG_NSH_ARGCAT is not set
+CONFIG_NSH_NESTDEPTH=3
+# CONFIG_NSH_DISABLEBG is not set
+CONFIG_NSH_BUILTIN_APPS=y
+
+#
+# Disable Individual commands
+#
+CONFIG_NSH_DISABLE_BASENAME=y
+# CONFIG_NSH_DISABLE_CAT is not set
+CONFIG_NSH_DISABLE_CD=y
+CONFIG_NSH_DISABLE_CP=y
+CONFIG_NSH_DISABLE_CMP=y
+CONFIG_NSH_DISABLE_DATE=y
+CONFIG_NSH_DISABLE_DD=y
+CONFIG_NSH_DISABLE_DF=y
+CONFIG_NSH_DISABLE_DIRNAME=y
+# CONFIG_NSH_DISABLE_ECHO is not set
+# CONFIG_NSH_DISABLE_ENV is not set
+CONFIG_NSH_DISABLE_EXEC=y
+CONFIG_NSH_DISABLE_EXIT=y
+# CONFIG_NSH_DISABLE_EXPORT is not set
+# CONFIG_NSH_DISABLE_FREE is not set
+CONFIG_NSH_DISABLE_GET=y
+# CONFIG_NSH_DISABLE_HELP is not set
+CONFIG_NSH_DISABLE_HEXDUMP=y
+# CONFIG_NSH_DISABLE_IFCONFIG is not set
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+# CONFIG_NSH_DISABLE_KILL is not set
+CONFIG_NSH_DISABLE_LOSETUP=y
+# CONFIG_NSH_DISABLE_LOSMART is not set
+# CONFIG_NSH_DISABLE_LS is not set
+# CONFIG_NSH_DISABLE_MB is not set
+CONFIG_NSH_DISABLE_MKDIR=y
+CONFIG_NSH_DISABLE_MKRD=y
+# CONFIG_NSH_DISABLE_MH is not set
+# CONFIG_NSH_DISABLE_MOUNT is not set
+# CONFIG_NSH_DISABLE_MV is not set
+# CONFIG_NSH_DISABLE_MW is not set
+CONFIG_NSH_DISABLE_PRINTF=y
+# CONFIG_NSH_DISABLE_PS is not set
+# CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set
+CONFIG_NSH_DISABLE_PUT=y
+# CONFIG_NSH_DISABLE_PWD is not set
+CONFIG_NSH_DISABLE_RM=y
+CONFIG_NSH_DISABLE_RMDIR=y
+# CONFIG_NSH_DISABLE_SET is not set
+# CONFIG_NSH_DISABLE_SOURCE is not set
+# CONFIG_NSH_DISABLE_SLEEP is not set
+CONFIG_NSH_DISABLE_TIME=y
+# CONFIG_NSH_DISABLE_TEST is not set
+# CONFIG_NSH_DISABLE_TELNETD is not set
+CONFIG_NSH_DISABLE_TRUNCATE=y
+CONFIG_NSH_DISABLE_UMOUNT=y
+# CONFIG_NSH_DISABLE_UNAME is not set
+# CONFIG_NSH_DISABLE_UNSET is not set
+# CONFIG_NSH_DISABLE_USLEEP is not set
+CONFIG_NSH_DISABLE_WGET=y
+CONFIG_NSH_DISABLE_XD=y
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Configure Command Options
+#
+# CONFIG_NSH_VARS is not set
+CONFIG_NSH_CODECS_BUFSIZE=128
+CONFIG_NSH_PROC_MOUNTPOINT="/proc"
+CONFIG_NSH_FILEIOSIZE=64
+CONFIG_NSH_STRERROR=y
+
+#
+# Scripting Support
+#
+CONFIG_NSH_DISABLESCRIPT=y
+
+#
+# Console Configuration
+#
+CONFIG_NSH_CONSOLE=y
+# CONFIG_NSH_ALTCONDEV is not set
+CONFIG_NSH_ARCHINIT=y
+# CONFIG_NSH_LOGIN is not set
+# CONFIG_NSH_CONSOLE_LOGIN is not set
+
+#
+# Platform-specific Support
+#
+# CONFIG_PLATFORM_CONFIGDATA is not set
+
+#
+# System Libraries and NSH Add-Ons
+#
+# CONFIG_SYSTEM_ADBD is not set
+# CONFIG_SYSTEM_CLE is not set
+# CONFIG_SYSTEM_CUTERM is not set
+# CONFIG_SYSTEM_EMBEDLOG is not set
+# CONFIG_SYSTEM_FLASH_ERASEALL is not set
+# CONFIG_SYSTEM_HEX2BIN is not set
+# CONFIG_SYSTEM_HEXED is not set
+
+#
+# libuv async i/o Library
+#
+# CONFIG_LIBUV is not set
+CONFIG_SYSTEM_NSH=y
+CONFIG_SYSTEM_NSH_PRIORITY=100
+CONFIG_SYSTEM_NSH_STACKSIZE=2048
+CONFIG_SYSTEM_NSH_PROGNAME="nsh"
+# CONFIG_SYSTEM_POPEN is not set
+# CONFIG_SYSTEM_RAMTEST is not set
+CONFIG_READLINE_HAVE_EXTMATCH=y
+CONFIG_SYSTEM_READLINE=y
+CONFIG_READLINE_ECHO=y
+# CONFIG_READLINE_TABCOMPLETION is not set
+# CONFIG_READLINE_CMD_HISTORY is not set
+# CONFIG_SYSTEM_SETLOGMASK is not set
+# CONFIG_SYSTEM_STACKMONITOR is not set
+# CONFIG_SYSTEM_SYSTEM is not set
+# CONFIG_SYSTEM_TEE is not set
+# CONFIG_SYSTEM_TERMCURSES is not set
+# CONFIG_SYSTEM_UBLOXMODEM is not set
+# CONFIG_SYSTEM_VI is not set
+# CONFIG_SYSTEM_ZMODEM is not set
+
+#
+# Testing
+#
+# CONFIG_TESTING_FATUTF8 is not set
+# CONFIG_TESTING_FSTEST is not set
+CONFIG_TESTING_GETPRIME=y
+CONFIG_TESTING_GETPRIME_PROGNAME="getprime"
+CONFIG_TESTING_GETPRIME_PRIORITY=50
+CONFIG_TESTING_GETPRIME_STACKSIZE=2048
+# CONFIG_TESTING_IRTEST is not set
+# CONFIG_TESTING_MM is not set
+# CONFIG_TESTING_NXFFS is not set
+# CONFIG_TESTING_OSTEST is not set
+# CONFIG_TESTING_SCANFTEST is not set
+# CONFIG_TESTING_SENSORTEST is not set
+# CONFIG_TESTING_SMART is not set
+# CONFIG_TESTING_SMART_TEST is not set
+# CONFIG_TESTING_UNITY is not set
+
+#
+# Wireless Libraries and NSH Add-Ons
+#
+
+#
+# Bluetooth applications
+#
+# CONFIG_BTSAK is not set
+
+#
+# IEEE 802.15.4 applications
+#
+# CONFIG_IEEE802154_I8SAK is not set
+# CONFIG_IEEE802154_LIBMAC is not set
+# CONFIG_IEEE802154_LIBUTILS is not set
diff --git a/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig b/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig
new file mode 100644
index 0000000000..98bcacc8a8
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/configs/nsh/defconfig
@@ -0,0 +1,75 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_DISABLEBG is not set
+# CONFIG_NSH_DISABLE_LOSMART is not set
+# CONFIG_NSH_DISABLE_UNAME is not set
+# CONFIG_STANDARD_SERIAL is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="bl602evb"
+CONFIG_ARCH_BOARD_BL602EVB=y
+CONFIG_ARCH_CHIP="bl602"
+CONFIG_ARCH_CHIP_BL602=y
+CONFIG_ARCH_INTERRUPTSTACK=8192
+CONFIG_ARCH_FPU=y
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BINFMT_DISABLE=y
+CONFIG_BOARD_LOOPSPERMSEC=10000
+CONFIG_BUILTIN=y
+CONFIG_DEBUG_FULLOPT=y
+CONFIG_DEBUG_SYMBOLS=y
+CONFIG_DEFAULT_SMALL=y
+CONFIG_DEV_ZERO=y
+CONFIG_DISABLE_MQUEUE=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_EXAMPLES_HELLO_STACKSIZE=8192
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=8192
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_MAX_TASKS=8
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_NFILE_DESCRIPTORS=6
+CONFIG_NFILE_STREAMS=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_DISABLE_CD=y
+CONFIG_NSH_DISABLE_CP=y
+CONFIG_NSH_DISABLE_IFUPDOWN=y
+CONFIG_NSH_DISABLE_MKDIR=y
+CONFIG_NSH_DISABLE_RM=y
+CONFIG_NSH_DISABLE_RMDIR=y
+CONFIG_NSH_DISABLE_UMOUNT=y
+CONFIG_NSH_FILEIOSIZE=64
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_PTHREAD_STACK_DEFAULT=8192
+CONFIG_RAM_SIZE=134217728
+CONFIG_RAM_START=0xc0800000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_RV32IM_CUSTOM_IRQ_SUPPORT=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_STACK_COLORATION=y
+CONFIG_START_DAY=20
+CONFIG_START_MONTH=3
+CONFIG_START_YEAR=2020
+CONFIG_STDIO_DISABLE_BUFFERING=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TASK_NAME_SIZE=12
+CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=8192
+CONFIG_TESTING_GETPRIME=y
+CONFIG_UART0_RXBUFSIZE=128
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_UART0_TXBUFSIZE=128
+CONFIG_USERMAIN_STACKSIZE=8192
+CONFIG_USER_ENTRYPOINT="nsh_main"
+CONFIG_WDOG_INTRESERVE=0
+CONFIG_DEBUG_FEATURES=y
diff --git a/boards/risc-v/bl602/bl602evb/include/board.h b/boards/risc-v/bl602/bl602evb/include/board.h
new file mode 100644
index 0000000000..b6f551a648
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/include/board.h
@@ -0,0 +1,68 @@
+/****************************************************************************
+ * boards/risc-v/litex/arty_a7/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
+#define __BOARDS_RISCV_BL602_BL602EVB_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: litex_boardinitialize
+ ****************************************************************************/
+
+void litex_boardinitialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_RISC-V_BL602_EVB_INCLUDE_BOARD_H */
diff --git a/boards/risc-v/bl602/bl602evb/scripts/Make.defs b/boards/risc-v/bl602/bl602evb/scripts/Make.defs
new file mode 100644
index 0000000000..829f6d92b5
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/scripts/Make.defs
@@ -0,0 +1,89 @@
+############################################################################
+# boards/risc-v/bl602/bl602evb/scripts/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+include $(TOPDIR)/arch/risc-v/src/rv32im/Toolchain.defs
+
+ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src
+ARCH_INCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)include
+
+LDSCRIPT = ld.script
+
+CINCPATH := ${shell $(INCDIR) -s "$(CC)" $(TOPDIR)$(DELIM)include}
+CXXINCPATH := ${shell $(INCDIR) -s "$(CC)" $(TOPDIR)$(DELIM)include$(DELIM)cxx}
+
+ARCHINCLUDES += $(CINCPATH)
+ARCHXXINCLUDES += $(CINCPATH) $(CXXINCPATH)
+
+ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
+ ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}"
+else
+ ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+STRIP = $(CROSSDEV)strip --strip-unneeded
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+ ARCHOPTIMIZATION = -g
+ ASARCHCPUFLAGS += -Wa,-g
+endif
+
+MAXOPTIMIZATION = -Os
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+ ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCPUFLAGS = -march=rv32imfc -mabi=ilp32f -mno-relax
+ARCHCFLAGS = -fno-builtin -ffunction-sections -fdata-sections
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+ARCHDEFINES += -DARCH_RISCV
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+AFLAGS += $(CFLAGS) -D__ASSEMBLY__ $(ASARCHCPUFLAGS)
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+LDFLAGS += --gc-sections -melf32lriscv
+
+HOSTCC = gcc
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
diff --git a/boards/risc-v/bl602/bl602evb/scripts/ld.script b/boards/risc-v/bl602/bl602evb/scripts/ld.script
new file mode 100644
index 0000000000..7608882699
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/scripts/ld.script
@@ -0,0 +1,279 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( bl602_start )
+
+__EM_SIZE = DEFINED(ble_controller_init) ? 8K : 0K;
+
+MEMORY
+{
+ rom (rxai!w) : ORIGIN = 0x21015000, LENGTH = 44K
+ flash (rxai!w) : ORIGIN = 0x23000000, LENGTH = 4M
+ ram_tcm (wxa) : ORIGIN = 0x4200C000, LENGTH = (16K + 16K + 48K + 64K + 64K + 8K - __EM_SIZE) /*put itcm with dtam and also OCRAM*/
+ ram_wifi (wxa) : ORIGIN = 0x42042000 - __EM_SIZE, LENGTH = (8K + 104K - 64K - 8K) /*leave 8K left for BLE*/
+}
+
+SECTIONS
+{
+ __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+ BOOT2_PT_ADDR = 0x42049C00;
+ BOOT2_FLASHCFG_ADDR = 0x42049c18;
+
+ .init :
+ {
+ KEEP (*(SORT_NONE(.init)))
+ } > flash
+
+ .text :
+ {
+ *(.text.unlikely .text.unlikely.*)
+ *(.text.startup .text.startup.*)
+ *(.text .text.*)
+ *(.gnu.linkonce.t.*)
+ } > flash
+
+ .rodata :
+ {
+ *(.rdata)
+ *(.rodata .rodata.*)
+ *(.sdata2.*)
+
+ /* static cli cmds */
+ . = ALIGN(4);
+ _bl_static_cli_cmds_start = .;
+ KEEP(*(.static_cli_cmds))
+ *(.static_cli_cmds)
+ _bl_static_cli_cmds_end = .;
+
+ /* static fw attribute entry */
+ . = ALIGN(4);
+ _bl_static_fw_cfg_entry_start = .;
+ KEEP(*(.wifi.cfg.entry))
+ _bl_static_fw_cfg_entry_end = .;
+
+ /* static blog code1 */
+ . = ALIGN(4);
+ _bl_static_blogcomponent_code_start = .;
+ KEEP(SORT(*)(.static_blogcomponent_code*))
+ *(.static_blogcomponent_code*)
+ _bl_static_blogcomponent_code_end = .;
+
+ /* static blog code2 */
+ . = ALIGN(4);
+ _bl_static_blogfile_code_start = .;
+ KEEP(SORT(*)(.static_blogfile_code*))
+ *(.static_blogfile_code*)
+ _bl_static_blogfile_code_end = .;
+
+ /* static blog code3 */
+ . = ALIGN(4);
+ _bl_static_blogpri_code_start = .;
+ KEEP(SORT(*)(.static_blogpri_code*))
+ *(.static_blogpri_code*)
+ _bl_static_blogpri_code_end = .;
+
+ *(.gnu.linkonce.r.*)
+
+ /*Framework table section, use ALIGN here to avoid fill section*/
+ . = ALIGN(4);
+ _rom_framework_audio_device_start = .;
+ KEEP(*(.framework.audio_device))
+ _rom_framework_audio_device_end = .;
+ } > flash
+
+ /*put wifibss in the first place*/
+ .wifibss (NOLOAD) :
+ {
+ PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
+ PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
+ *ipc_shared.o(COMMON)
+ *sdu_shared.o(COMMON)
+ *hal_desc.o(COMMON)
+ *txl_buffer_shared.o(COMMON)
+ *txl_frame_shared.o(COMMON)
+ *scan_shared.o(COMMON)
+ *scanu_shared.o(COMMON)
+ *mfp_bip.o(COMMON)
+ *me_mic.o(COMMON)
+ *bl_sta_mgmt_others.o(COMMON)
+ *bl_pmk_mgmt.o(COMMON)
+ *bl_pmk_mgmt_internal.o(COMMON)
+ *libwifi_drv.a:bl_utils.o(COMMON)
+ *libwifi_drv.a:bl_utils.o(.bss*)
+ *(.wifi_ram*)
+ . = ALIGN(16);
+ } > ram_wifi
+
+ PROVIDE( _heap_wifi_start = . );
+ PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
+
+ .romdata :
+ {
+ /*always put freetos under global_pointer with the following order. No change!*/
+ PROVIDE( __global_pointer_head$ = . );
+ PROVIDE( __global_pointer$ = . + 0x7F0 );
+ . = . + 0x498;
+ } > ram_tcm AT > flash
+
+ .data :
+ {
+ PROVIDE( _data_load = LOADADDR(.data) );
+ PROVIDE( _data_run = ADDR(.data) );
+ PROVIDE( _data_run_end = ADDR(.data) + SIZEOF(.data));
+
+ *(.tcm_code)
+ *(.tcm_const)
+ *(.sclock_rlt_code)
+ *(.sclock_rlt_const)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+
+ *(.sdata .sdata.*)
+ *(.gnu.linkonce.s.*)
+
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+
+ . = ALIGN(8);
+ *(._k_queue.static.*)
+ *(._k_sem.static.*)
+ *(._k_mutex.static.*)
+ _net_buf_pool_list = .;
+ KEEP(*(SORT_BY_NAME("._net_buf_pool.static.*")))
+ _bt_gatt_service_static_list_start = .;
+ KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
+ _bt_gatt_service_static_list_end = .;
+ _bt_l2cap_fixed_chan_list_start = .;
+ KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
+ _bt_l2cap_fixed_chan_list_end = .;
+ } > ram_tcm AT > flash
+
+ .boot2 (NOLOAD) :
+ {
+ PROVIDE ( __boot2_pt_addr_start = . );
+ *(.bss.boot2_partition_table)
+ PROVIDE ( __boot2_pt_addr_end = . );
+
+ PROVIDE ( __boot2_flash_cfg_start = . );
+ *(.bss.boot2_flashCfg)
+ PROVIDE ( __boot2_flash_cfg_end = . );
+
+ } > ram_tcm
+
+ .bss (NOLOAD) :
+ {
+ PROVIDE( __bss_start = ADDR(.bss) );
+ PROVIDE( __bss_end = ADDR(.bss) + SIZEOF(.bss) );
+
+ PROVIDE( _sbss = __bss_start );
+ PROVIDE( _ebss = __bss_end );
+
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ } > ram_tcm
+
+ PROVIDE( _heap_start = . );
+ PROVIDE( _heap_size = ADDR(.stack) - _heap_start );
+
+
+ .stack ORIGIN(ram_tcm) + LENGTH(ram_tcm) - __stack_size (NOLOAD) :
+ {
+ . = . + __stack_size;
+ PROVIDE( _sp_main = . );
+ __freertos_irq_stack_top = .;
+ } >ram_tcm
+
+
+ /*SYMOBOL used in code*/
+ PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
+ PROVIDE( _ld_bl_static_cli_cmds_end = _bl_static_cli_cmds_end );
+
+ /*CFG FW used in code*/
+ PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
+ PROVIDE( _ld_bl_static_cfg_entry_end = _bl_static_fw_cfg_entry_end );
+
+ /* blog */
+ PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
+ PROVIDE( _ld_bl_static_blogcomponent_code_end = _bl_static_blogcomponent_code_end );
+ PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
+ PROVIDE( _ld_bl_static_blogfile_code_end = _bl_static_blogfile_code_end );
+ PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
+ PROVIDE( _ld_bl_static_blogpri_code_end = _bl_static_blogpri_code_end );
+
+ PROVIDE( _ld_ram_size0 = LENGTH(flash) );
+ PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
+ PROVIDE( _ld_ram_size1 = LENGTH(ram_tcm) );
+ PROVIDE( _ld_ram_addr1 = ORIGIN(ram_tcm) );
+ PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
+ PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
+
+
+ /*BOOT2 sections*/
+ PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );
+ PROVIDE ( __boot2_flash_cfg_src = BOOT2_FLASHCFG_ADDR );
+
+ PROVIDE(xTaskGetTickCount = 0x0000000021017694);
+ PROVIDE(xTaskGetTickCountFromISR = 0x00000000210176aa);
+ PROVIDE(pvPortMalloc = 0x0000000021019662);
+ PROVIDE(vPortFree = 0x000000002101973a);
+ PROVIDE(vTaskNotifyGiveFromISR = 0x00000000210188e8);
+ PROVIDE(vTaskSwitchContext = 0x0000000021017a04);
+ PROVIDE(ulTaskNotifyTake = 0x0000000021018548);
+ PROVIDE(vTaskExitCritical = 0x00000000210183f4);
+ PROVIDE(vTaskEnterCritical = 0x00000000210183e4);
+ PROVIDE(xTaskGetCurrentTaskHandle = 0x0000000021018152);
+ PROVIDE(xQueueSemaphoreTake = 0x0000000021015ce8);
+ PROVIDE(xQueueGenericSend = 0x0000000021015834);
+ PROVIDE(xQueueGenericSendFromISR = 0x0000000021015a4c);
+ PROVIDE(xTaskCreateStatic = 0x00000000210170a2);
+ PROVIDE(xTaskCreate = 0x000000002101713a);
+ PROVIDE(xQueueCreateMutex = 0x0000000021015a1c);
+ PROVIDE(xQueueCreateMutexStatic = 0x0000000021015994);
+ PROVIDE(vQueueDelete = 0x00000000210161d8);
+ PROVIDE(xQueueGenericCreateStatic = 0x00000000210156c2);
+ PROVIDE(xQueueGenericCreate = 0x0000000021015744);
+ PROVIDE(xQueueReceive = 0x0000000021015b8a);
+ PROVIDE(uxQueueMessagesWaiting = 0x0000000021016168);
+ PROVIDE(vTaskDelay = 0x00000000210179c6);
+ PROVIDE(vTaskDelayUntil = 0x0000000021017952);
+ PROVIDE(xPortGetFreeHeapSize = 0x00000000210197ce);
+ PROVIDE(vTaskList = 0x0000000021018408);
+ PROVIDE(xTimerGenericCommand = 0x0000000021018bec);
+ PROVIDE(xTimerCreateTimerTask = 0x0000000021018a9e);
+ PROVIDE(xTimerCreate = 0x0000000021018af6);
+ PROVIDE(xTimerCreateStatic = 0x0000000021018b66);
+ PROVIDE(xQueueCreateCountingSemaphoreStatic = 0x00000000210157c2);
+ PROVIDE(xQueueCreateCountingSemaphore = 0x0000000021015800);
+ PROVIDE(pTrapNetCounter = __global_pointer_head$);
+ PROVIDE(TrapNetCounter = __global_pointer_head$ + 0x58);
+ PROVIDE(vEventGroupDelete = 0x00000000210153be);
+ PROVIDE(xEventGroupWaitBits = 0x0000000021015086);
+ PROVIDE(xEventGroupCreateStatic = 0x0000000021015000);
+ PROVIDE(xEventGroupSetBits = 0x00000000210151e0);
+ PROVIDE(xStreamBufferGenericCreateStatic = 0x00000000210165c0);
+ PROVIDE(xStreamBufferReceive = 0x00000000210169ae);
+ PROVIDE(xStreamBufferSend = 0x00000000210167a8);
+ PROVIDE(pvTimerGetTimerID = 0x0000000021018fd4);
+ PROVIDE(xTaskGenericNotify = 0x00000000210186be);
+ PROVIDE(xTaskGenericNotifyFromISR = 0x00000000210187de);
+ PROVIDE(xQueueGiveMutexRecursive = 0x00000000210159c8);
+ PROVIDE(xQueueTakeMutexRecursive = 0x0000000021015e70);
+ PROVIDE(xTaskGetTickCount2 = 0x000000002101769a);
+ PROVIDE(xQueueGiveFromISR = 0x0000000021015b0e);
+ PROVIDE(vTaskDelete = 0x00000000210171b6);
+ PROVIDE(uxTaskGetStackHighWaterMark = 0x0000000021018110);
+ PROVIDE(pcTaskGetName = 0x00000000210176b6);
+ PROVIDE(vTaskStartScheduler = 0x0000000021017610);
+ PROVIDE(vPortDefineHeapRegions = 0x00000000210197da);
+ PROVIDE(__LD_CONFIG_EM_SEL = __EM_SIZE);
+
+ PROVIDE( _ld_symbol_rom_framework_audio_device_start = _rom_framework_audio_device_start);
+ PROVIDE( _ld_symbol_rom_framework_audio_device_end = _rom_framework_audio_device_end);
+
+}
diff --git a/boards/risc-v/bl602/bl602evb/src/Makefile b/boards/risc-v/bl602/bl602evb/src/Makefile
new file mode 100644
index 0000000000..8fdb2cc62b
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/src/Makefile
@@ -0,0 +1,29 @@
+############################################################################
+# boards/risc-v/bl602/evb/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include $(TOPDIR)/Make.defs
+
+CSRCS = bl602_bringup.c bl602_boot.c
+
+ifeq ($(CONFIG_LIB_BOARDCTL),y)
+CSRCS += bl602_appinit.c
+endif
+
+include $(TOPDIR)/boards/Board.mk
diff --git a/boards/risc-v/bl602/bl602evb/src/bl602_appinit.c b/boards/risc-v/bl602/bl602evb/src/bl602_appinit.c
new file mode 100644
index 0000000000..cc6a4eb146
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/src/bl602_appinit.c
@@ -0,0 +1,69 @@
+/****************************************************************************
+ * boards/risc-v/bl602/evb/src/litex_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <syslog.h>
+#include <errno.h>
+
+#include <nuttx/board.h>
+
+#include "chip.h"
+#include "bl602evb.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform architecture specific initialization
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no
+ * meaning to NuttX; the meaning of the argument is a contract
+ * between the board-specific initialization logic and the
+ * matching application logic. The value could be such things as a
+ * mode enumeration value, a set of DIP switch switch settings, a
+ * pointer to configuration data read from a file or serial FLASH,
+ * or whatever you would like to do with it. Every implementation
+ * should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+ bl602_bringup();
+
+ return 0;
+}
diff --git a/boards/risc-v/bl602/bl602evb/src/bl602_boot.c b/boards/risc-v/bl602/bl602evb/src/bl602_boot.c
new file mode 100644
index 0000000000..75132765f5
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/src/bl602_boot.c
@@ -0,0 +1,64 @@
+/****************************************************************************
+ * boards/risc-v/bl602/evb/src/litex_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "hardware/bl602_hbn.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_boardinitialize
+ *
+ * Description:
+ * All LITEX architectures must provide the following entry point.
+ * This entry point is called early in the initialization -- after all
+ * memory has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
+
+void bl602_boardinitialize(void)
+{
+ uint32_t tmp_val;
+
+ tmp_val = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+ tmp_val = BL_SET_REG_BITS_VAL(tmp_val, HBN_REG_AON_PAD_IE_SMT, 1);
+ BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp_val);
+}
diff --git a/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c b/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c
new file mode 100644
index 0000000000..2f151f24e2
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/src/bl602_bringup.c
@@ -0,0 +1,113 @@
+/****************************************************************************
+ * boards/risc-v/bl602/evb/src/litex_bringup.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/timers/oneshot.h>
+
+#include <sys/mount.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <syslog.h>
+#include <errno.h>
+
+#include <nuttx/board.h>
+#include <nuttx/input/buttons.h>
+#include <bl602_tim_lowerhalf.h>
+#include <bl602_oneshot_lowerhalf.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: bl602_bringup
+ ****************************************************************************/
+
+int bl602_bringup(void)
+{
+#if defined(CONFIG_TIMER) && defined(CONFIG_ONESHOT) && \
+ defined(CONFIG_BL602_TIMER1)
+ struct oneshot_lowerhalf_s *os = NULL;
+#endif
+ int ret = OK;
+
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
+
+ ret = mount(NULL, "/proc", "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslog(
+ LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", "/proc", ret);
+ return ret;
+ }
+#endif
+
+#if defined(CONFIG_TIMER)
+#if defined(CONFIG_BL602_TIMER0)
+ ret = bl602_timer_initialize("/dev/timer0", 0);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "Failed to initialize /dev/timer0 Driver: %d\n", ret);
+ return ret;
+ }
+#endif
+
+#if defined(CONFIG_BL602_TIMER1) && !defined(CONFIG_ONESHOT)
+ ret = bl602_timer_initialize("/dev/timer1", 1);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "Failed to initialize /dev/timer1 Driver: %d\n", ret);
+ return ret;
+ }
+#elif defined(CONFIG_BL602_TIMER1) && defined(CONFIG_ONESHOT)
+ os = oneshot_initialize(1, 1);
+ if (os == NULL)
+ {
+ syslog(LOG_ERR, "ERROR: oneshot_initialize failed\n");
+ }
+ else
+ {
+#ifdef CONFIG_CPULOAD_ONESHOT
+ /* Configure the oneshot timer to support CPU load measurement */
+
+ nxsched_oneshot_extclk(os);
+
+#else
+ ret = oneshot_register("/dev/oneshot", os);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR,
+ "ERROR: Failed to register oneshot at /dev/oneshot: %d\n",
+ ret);
+ }
+#endif
+ }
+#endif
+#endif
+
+ return ret;
+}
diff --git a/boards/risc-v/bl602/bl602evb/src/bl602evb.h b/boards/risc-v/bl602/bl602evb/src/bl602evb.h
new file mode 100644
index 0000000000..5d3d3919ee
--- /dev/null
+++ b/boards/risc-v/bl602/bl602evb/src/bl602evb.h
@@ -0,0 +1,32 @@
+/****************************************************************************
+ * boards/risc-v/bl602/bl602evb/src/bl602evb.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __BOARDS_RISCV_BL602_BL602EVB_SRC_BL602EVB_H
+#define __BOARDS_RISCV_BL602_BL602EVB_SRC_BL602EVB_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+int bl602_bringup(void);
+
+#endif /* __BOARDS_RISCV_BL602_EVB_SRC_ARTY_A7_H */