nrf52 improvements
Author: Alan Carvalho de Assis <acassis@gmail.com>
Run nxstyle on .c and .h files and fix it
Author: raiden00pl <raiden00pl@gmail.com>
arch/arm/src/nrf52: use the same naming convention for register defs
arch/arm/src/nrf52/hardware/nrf52_ficr.h: remove invalid defs
arch/arm/src/nrf52/hardware: add TIMER register defs
This commit is contained in:
Mateusz Szafoni
Alan Carvalho de Assis
parent
02f619a8be
commit
58c3ee65e7
@ -1,4 +1,4 @@
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/***************************************************************************************************
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/*****************************************************************************
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* arch/arm/src/nrf52/hardware/nrf52_ficr.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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@ -31,23 +31,23 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_FICR_H
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#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_FICR_H
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/***************************************************************************************************
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/****************************************************************************
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* Included Files
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***************************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/***************************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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***************************************************************************************************/
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****************************************************************************/
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/* FICR Register Offsets ****************************************************************************/
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/* FICR Register Offsets ****************************************************/
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/* Registers for the FICR */
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@ -149,15 +149,6 @@
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/* FICR Register Bitfield Definitions **************************************************************/
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#define NRF52_FICR_READY_READY (1 << 0) /* FICR is ready */
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#define NRF52_FICR_CONFIG_WEN (1 << 0) /* Enable write program memory */
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#define NRF52_FICR_ICACHECNF_CACHEEN (1 << 0) /* Cache enable */
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#define NRF52_FICR_ICACHECNF_CACHEPROFEN (1 << 8) /* Cache profiling enable */
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/* ENABLE Register */
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/* INTENSET Register */
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/* TODO: */
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#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_FICR_H */
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@ -95,12 +95,12 @@
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/* Register bit definitions *********************************************************/
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#define NRF52_GPIO_CNF_DIR (1 << 0) /* Bit 0: Pin direction */
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#define NRF52_GPIO_CNF_INPUT (1 << 1) /* Bit 1: Input buffer disconnect */
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#define NRF52_GPIO_CNF_PULL_SHIFT (2)
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#define NRF52_GPIO_CNF_PULL_MASK (0x3 << NRF52_GPIO_CNF_PULL_SHIFT)
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# define NRF52_GPIO_CNF_PULL_DISABLED (0 << NRF52_GPIO_CNF_PULL_SHIFT)
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# define NRF52_GPIO_CNF_PULL_DOWN (1 << NRF52_GPIO_CNF_PULL_SHIFT)
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# define NRF52_GPIO_CNF_PULL_UP (3 << NRF52_GPIO_CNF_PULL_SHIFT)
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#define GPIO_CNF_DIR (1 << 0) /* Bit 0: Pin direction */
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#define GPIO_CNF_INPUT (1 << 1) /* Bit 1: Input buffer disconnect */
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#define GPIO_CNF_PULL_SHIFT (2)
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#define GPIO_CNF_PULL_MASK (0x3 << GPIO_CNF_PULL_SHIFT)
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# define GPIO_CNF_PULL_DISABLED (0 << GPIO_CNF_PULL_SHIFT)
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# define GPIO_CNF_PULL_DOWN (1 << GPIO_CNF_PULL_SHIFT)
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# define GPIO_CNF_PULL_UP (3 << GPIO_CNF_PULL_SHIFT)
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#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIO_H */
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@ -48,34 +48,38 @@
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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/* Register Offsets for RNG *********************************************************/
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#define NRF52_RNG_T_START_OFFSET 0x000 /* RNG Task Start */
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#define NRF52_RNG_T_STOP_OFFSET 0x004 /* RNG Task Stop */
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#define NRF52_RNG_EVENT_RDY_OFFSET 0x100 /* RNG Eevent ValRDY */
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#define NRF52_RNG_SHORT_OFFSET 0x200 /* RNG Short Register */
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#define NRF52_RNG_INT_SET_OFFSET 0x304 /* RNG INT SET Register */
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#define NRF52_RNG_INT_CLR_OFFSET 0x308 /* RNG INT CLR Register */
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#define NRF52_RNG_CONFIG_OFFSET 0x504 /* RNG CONFIG Register */
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#define NRF52_RNG_VALUE_OFFSET 0x508 /* RNG Value Register */
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#define NRF52_RNG_TASKS_START_OFFSET 0x0000 /* RNG Task Start */
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#define NRF52_RNG_TASKS_STOP_OFFSET 0x0004 /* RNG Task Stop */
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#define NRF52_RNG_EVENTS_RDY_OFFSET 0x0100 /* RNG Eevent ValRDY */
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#define NRF52_RNG_SHORTS_OFFSET 0x0200 /* RNG Short Register */
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#define NRF52_RNG_INTSET_OFFSET 0x0304 /* RNG INT SET Register */
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#define NRF52_RNG_INTCLR_OFFSET 0x0308 /* RNG INT CLR Register */
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#define NRF52_RNG_CONFIG_OFFSET 0x0504 /* RNG CONFIG Register */
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#define NRF52_RNG_VALUE_OFFSET 0x0508 /* RNG Value Register */
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/* Register Addresses ***************************************************************/
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/* Register Addresses for RNG *******************************************************/
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#define NRF52_RNG_T_START (NRF52_RNG_BASE + NRF52_RNG_T_START_OFFSET)
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#define NRF52_RNG_T_STOP (NRF52_RNG_BASE + NRF52_RNG_T_STOP_OFFSET)
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#define NRF52_RNG_EVENT_RDY (NRF52_RNG_BASE + NRF52_RNG_EVENT_RDY_OFFSET)
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#define NRF52_RNG_TASKS_START (NRF52_RNG_BASE + NRF52_RNG_TASKS_START_OFFSET)
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#define NRF52_RNG_TASKS_STOP (NRF52_RNG_BASE + NRF52_RNG_TASKS_STOP_OFFSET)
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#define NRF52_RNG_EVENTS_RDY (NRF52_RNG_BASE + NRF52_RNG_EVENTS_RDY_OFFSET)
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#define NRF52_RNG_SHORT (NRF52_RNG_BASE + NRF52_RNG_SHORT_OFFSET)
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#define NRF52_RNG_INT_SET (NRF52_RNG_BASE + NRF52_RNG_INT_SET_OFFSET)
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#define NRF52_RNG_INT_CLR (NRF52_RNG_BASE + NRF52_RNG_INT_CLR_OFFSET)
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#define NRF52_RNG_SHORTS (NRF52_RNG_BASE + NRF52_RNG_SHORTS_OFFSET)
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#define NRF52_RNG_INTSET (NRF52_RNG_BASE + NRF52_RNG_INTSET_OFFSET)
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#define NRF52_RNG_INTCLR (NRF52_RNG_BASE + NRF52_RNG_INTCLR_OFFSET)
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#define NRF52_RNG_CONFIG (NRF52_RNG_BASE + NRF52_RNG_CONFIG_OFFSET)
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#define NRF52_RNG_VALUE (NRF52_RNG_BASE + NRF52_RNG_VALUE_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* IntEnSet / IntEnClr Register Bit */
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/* INTSET/INTCLR Register */
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#define NRF52_RNG_INT_EVENT_RDY (1<<0)
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#define RNG_INT_RDY (1 << 0) /* Bit 0: VALRDY event */
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/* CONFIG Register */
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#define RNG_CONFIG_DERCEN (1 << 0) /* Bit 0: Bias correction */
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#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_STM32_RNG_H */
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@ -36,7 +36,7 @@
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#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SAADC_H
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#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SAADC_H
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/****************************************************************************
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/***************************************************************************
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* Included Files
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***************************************************************************/
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@ -49,33 +49,33 @@
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/* Register offsets for SAADC **********************************************/
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#define NRF52_SAADC_TASKS_START 0x0000 /* Start the SAADCM */
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#define NRF52_SAADC_TASKS_SAMPLE 0x0004 /* Takes one SAADC sample */
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#define NRF52_SAADC_TASKS_STOP 0x0008 /* Stop the SAADC */
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#define NRF52_SAADC_TASKS_CALEOFFSET 0x000c /* Starts offset auto-calibration */
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#define NRF52_SAADC_EVENTS_STARTED 0x0100 /* The SAADC has started */
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#define NRF52_SAADC_EVENTS_END 0x0104 /* The SAADC has filled up the result buffer */
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#define NRF52_SAADC_EVENTS_DONE 0x0108 /* A conversio ntask has been completed */
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#define NRF52_SAADC_EVENTS_RESULTDONE 0x010c /* Result ready for transfer to RAM */
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#define NRF52_SAADC_EVENTS_CALDONE 0x0110 /* Calibration is complete */
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#define NRF52_SAADC_EVENTS_STOPPED 0x0110 /* The SAADC has stopped */
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#define NRF52_SAADC_EVENTS_CHLIMH(x) (0x118 + (x + 0x8)) /* Limit high event for channel x */
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#define NRF52_SAADC_EVENTS_CHLIML(x) (0x11c + (x + 0x8)) /* Limit low event for channel x */
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#define NRF52_SAADC_INTEN 0x0300 /* Enable or disable interrupt */
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#define NRF52_SAADC_INTENSET 0x0304 /* Enable interrupt */
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#define NRF52_SAADC_INTENCLR 0x0308 /* Disable interrupt */
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#define NRF52_SAADC_STATUS 0x0400 /* Status */
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#define NRF52_SAADC_ENABLE 0x0500 /* Enable or disable SAADC */
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#define NRF52_SAADC_CHPSELP(x) (0x510 + (x + 0x10)) /* Input positive pin for CH[x] */
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#define NRF52_SAADC_CHPSELN(x) (0x514 + (x + 0x10)) /* Input negative pin for CH[x] */
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#define NRF52_SAADC_CHCONFIG(x) (0x518 + (x + 0x10)) /* Input configuration for CH[x] */
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#define NRF52_SAADC_CHLIMIT(x) (0x51c + (x + 0x10)) /* High/low limits for event monitoring of a CH[x] */
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#define NRF52_SAADC_RESOLUTION 0x05f0 /* Resolution configuration */
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#define NRF52_SAADC_OVERSAMPLE 0x05f4 /* Oversampling configuration */
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#define NRF52_SAADC_SAMPLERATE 0x05f8 /* Controls normal or continous sample rate */
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#define NRF52_SAADC_PTR 0x062c /* Data pointer */
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#define NRF52_SAADC_MAXCNT 0x0630 /* Maximum number of 16-bit samples */
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#define NRF52_SAADC_AMOUNT 0x0634 /* Number of 16-bit samples written to buffer */
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#define NRF52_SAADC_TASKS_START_OFFSET 0x0000 /* Start the SAADCM */
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#define NRF52_SAADC_TASKS_SAMPLE_OFFSET 0x0004 /* Takes one SAADC sample */
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#define NRF52_SAADC_TASKS_STOP_OFFSET 0x0008 /* Stop the SAADC */
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#define NRF52_SAADC_TASKS_CALOFFSET_OFFSET 0x000c /* Starts offset auto-calibration */
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#define NRF52_SAADC_EVENTS_STARTED_OFFSET 0x0100 /* The SAADC has started */
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#define NRF52_SAADC_EVENTS_END_OFFSET 0x0104 /* The SAADC has filled up the result buffer */
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#define NRF52_SAADC_EVENTS_DONE_OFFSET 0x0108 /* A conversio ntask has been completed */
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#define NRF52_SAADC_EVENTS_RESDONE_OFFSET 0x010c /* Result ready for transfer to RAM */
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#define NRF52_SAADC_EVENTS_CALDONE_OFFSET 0x0110 /* Calibration is complete */
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#define NRF52_SAADC_EVENTS_STOPPED_OFFSET 0x0110 /* The SAADC has stopped */
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#define NRF52_SAADC_EVENTS_CHLIMH_OFFSET(x) (0x118 + (x + 0x8)) /* Limit high event for channel x */
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#define NRF52_SAADC_EVENTS_CHLIML_OFFSET(x) (0x11c + (x + 0x8)) /* Limit low event for channel x */
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#define NRF52_SAADC_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */
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#define NRF52_SAADC_INTENSET_OFFSET 0x0304 /* Enable interrupt */
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#define NRF52_SAADC_INTENCLR_OFFSET 0x0308 /* Disable interrupt */
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#define NRF52_SAADC_STATUS_OFFSET 0x0400 /* Status */
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#define NRF52_SAADC_ENABLE_OFFSET 0x0500 /* Enable or disable SAADC */
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#define NRF52_SAADC_CHPSELP_OFFSET(x) (0x510 + (x + 0x10)) /* Input positive pin for CH[x] */
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#define NRF52_SAADC_CHPSELN_OFFSET(x) (0x514 + (x + 0x10)) /* Input negative pin for CH[x] */
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#define NRF52_SAADC_CHCONFIG_OFFSET(x) (0x518 + (x + 0x10)) /* Input configuration for CH[x] */
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#define NRF52_SAADC_CHLIMIT_OFFSET(x) (0x51c + (x + 0x10)) /* High/low limits for event monitoring of a CH[x] */
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#define NRF52_SAADC_RESOLUTION_OFFSET 0x05f0 /* Resolution configuration */
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#define NRF52_SAADC_OVERSAMPLE_OFFSET 0x05f4 /* Oversampling configuration */
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#define NRF52_SAADC_SAMPLERATE_OFFSET 0x05f8 /* Controls normal or continous sample rate */
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#define NRF52_SAADC_PTR_OFFSET 0x062c /* Data pointer */
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#define NRF52_SAADC_MAXCNT_OFFSET 0x0630 /* Maximum number of 16-bit samples */
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#define NRF52_SAADC_AMOUNT_OFFSET 0x0634 /* Number of 16-bit samples written to buffer */
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/* Register Bitfield Definitions for SAADC *********************************/
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@ -84,7 +84,7 @@
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#define SAADC_INT_STARTED (1 << 0) /* Bit 0: Interrupt for event STARTED */
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#define SAADC_INT_END (1 << 1) /* Bit 1: Interrupt for event END */
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#define SAADC_INT_DONE (1 << 2) /* Bit 2: Interrupt for event DONE */
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#define SAADC_INT_RESULTDONE (1 << 3) /* Bit 3: Interrupt for event RESULTDONE */
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#define SAADC_INT_RESDONE (1 << 3) /* Bit 3: Interrupt for event RESULTDONE */
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#define SAADC_INT_CALDONE (1 << 4) /* Bit 4: Interrupt for event CALIBRATEDONE */
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#define SAADC_INT_STOPPED (1 << 5) /* Bit 5: Interrupt for event STOPPED */
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#define SAADC_INT_CHXLIMH(x) (1 << (x + 0x6)) /* Bit (x+6): Interrupt for event CHxLIMITH */
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99
arch/arm/src/nrf52/hardware/nrf52_tim.h
Normal file
99
arch/arm/src/nrf52/hardware/nrf52_tim.h
Normal file
@ -0,0 +1,99 @@
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/**************************************************************************
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* arch/arm/src/nrf52/hardware/nrf52_tim.h
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*
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* Copyright (C) 2020 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TIM_H
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#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TIM_H
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/***************************************************************************
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* Included Files
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***************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/***************************************************************************
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* Pre-processor Definitions
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***************************************************************************/
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/* Register offsets for TIM ************************************************/
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#define NRF52_TIM_TASKS_START_OFFSET 0x0000 /* Start Timer */
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#define NRF52_TIM_TASKS_STOP_OFFSET 0x0004 /* Stop Timer */
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#define NRF52_TIM_TASKS_COUNT_OFFSET 0x0008 /* Increment Timer*/
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#define NRF52_TIM_TASKS_CLEAR_OFFSET 0x000c /* Clear time */
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#define NRF52_TIM_TASKS_SHUTDOWN_OFFSET 0x0010 /* Shutdown Timer */
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#define NRF52_TIM_TASKS_CAPTURE_OFFSET(x) (0x0040 + ((x) * 0x04)) /* Capture Timer value to CC[x] */
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#define NRF52_TIM_EVENTS_COMPARE_OFFSET(x) (0x0140 + ((x) * 0x04)) /* Compare event on CC[x] */
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#define NRF52_TIM_SHORTS_OFFSET 0x0200 /* Shortcuts between local events and tasks */
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#define NRF52_TIM_INTENSET_OFFSET 0x0304 /* Enable interrupt */
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#define NRF52_TIM_MODE_OFFSET 0x0504 /* Timer mode selection */
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#define NRF52_TIM_BITMODE_OFFSET 0x0508 /* Configure the number of bits used by the Timer */
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#define NRF52_TIM_PRESCALER_OFFSET 0x0510 /* Timer prescaler register */
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#define NRF52_TIM_CC_OFFSET(x) (0x0540 + ((x) * 0x04)) /* Capture/Compare register x */
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/* Register offsets for TIM ************************************************/
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/* SHORTS Register */
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#define TIM_SHORTS_COMPARE_CLEAR(x) (1 << (x)) /* Bits 0-5: */
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#define TIM_SHORTS_COMPARE_STOP(x) (1 << (x + 0x8)) /* Bits 8-13 */
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/* INTENSET/INTENCLR Register */
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#define TIM_INT_COMPARE(x) (1 << (x + 0x16)) /* Bits 16-21 */
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/* MODE Register */
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#define TIM_MODE_SHIFT (0) /* Bits 0-1: Timer mode */
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#define TIM_MODE_MASK (0x3 << TIM_MODE_SHIFT)
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# define TIM_MODE_TIMER (0x0 << TIM_MODE_SHIFT) /* 0: Timer mode */
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# define TIM_MODE_COUNTER (0x1 << TIM_MODE_SHIFT) /* 1: Counter mode */
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# define TIM_MODE_LPCONUTER (0x2 << TIM_MODE_SHIFT) /* 2: Low Power Counter mode */
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/* BITMODE Register */
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#define TIM_BITMODE_SHIFT (0) /* Bits 0-1: Timer bit width */
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#define TIM_BITMODE_MASK (0x3 << TIM_BITMODE_SHIFT)
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# define TIM_BITMODE_16B (0x0 << TIM_BITMODE_SHIFT) /* 0: 16 bit */
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# define TIM_BITMODE_8B (0x1 << TIM_BITMODE_SHIFT) /* 1: 8 bit */
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# define TIM_BITMODE_24B (0x2 << TIM_BITMODE_SHIFT) /* 2: 24 bit */
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# define TIM_BITMODE_32B (0x3 << TIM_BITMODE_SHIFT) /* 3: 32 bit */
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/* PRESCALER Register */
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#define TIM_PRESCALER_SHIFT (0) /* Bits 0-3: Prescaler value */
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#define TIM_PRESCALER_MASK (0xf << TIM_PRESCALER_SHIFT)
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#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TIM_H */
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@ -89,15 +89,27 @@
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#define NRF52_WDT_RR6 (NRF52_WDT_BASE + NRF52_WDT_RR6_OFFSET)
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#define NRF52_WDT_RR7 (NRF52_WDT_BASE + NRF52_WDT_RR7_OFFSET)
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/* UART Register Bitfield Definitions **************************************************************/
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/* WDT Register Bitfield Definitions ***************************************************************/
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/* ENABLE Register */
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/* INTENSET/INTENCLR Register */
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#define NRF52_UART_ENABLE_DISABLE (0)
|
||||
#define NRF52_UART_ENABLE_ENABLE (4)
|
||||
#define WDT_INT_TIMEOUT (1 << 0) /* Bit 0: TIMEOUT */
|
||||
|
||||
/* INTENSET Register */
|
||||
/* REQSTATUS[x] Register */
|
||||
|
||||
#define NRF52_UART_INTENSET_RXDRDY (1 << 2)
|
||||
#define WDT_REQSTATUS_RR(x) (1 << (x)) /* Bits 0-7: Request status for RR[i] register */
|
||||
|
||||
/* RREN[x] Register */
|
||||
|
||||
#define WDT_RREN_RR(x) (1 << (x)) /* Bits 0-7: Enable or disable RR[i] register */
|
||||
|
||||
/* CONFIG Register */
|
||||
|
||||
#define WDT_CONFIG_SLEEP (1 << 0) /* Bit 0: */
|
||||
#define WDT_CONFIG_HALT (1 << 0) /* Bit 3: */
|
||||
|
||||
/* RR[x] Register */
|
||||
|
||||
#define WDT_RR_VALUE (0x6E524635UL) /* Fixed value, don't modify it */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_WDT_H */
|
||||
|
||||
@ -144,17 +144,17 @@ static inline void nrf52_gpio_mode(nrf52_pinset_t cfgset,
|
||||
mode = cfgset & GPIO_MODE_MASK;
|
||||
|
||||
regval = getreg32(offset);
|
||||
regval &= NRF52_GPIO_CNF_PULL_MASK;
|
||||
regval &= GPIO_CNF_PULL_MASK;
|
||||
|
||||
if (mode == GPIO_PULLUP)
|
||||
{
|
||||
regval &= NRF52_GPIO_CNF_PULL_MASK;
|
||||
regval |= NRF52_GPIO_CNF_PULL_UP;
|
||||
regval &= GPIO_CNF_PULL_MASK;
|
||||
regval |= GPIO_CNF_PULL_UP;
|
||||
}
|
||||
else if (mode == GPIO_PULLDOWN)
|
||||
{
|
||||
regval &= NRF52_GPIO_CNF_PULL_MASK;
|
||||
regval |= NRF52_GPIO_CNF_PULL_DOWN;
|
||||
regval &= GPIO_CNF_PULL_MASK;
|
||||
regval |= GPIO_CNF_PULL_DOWN;
|
||||
}
|
||||
|
||||
putreg32(regval, offset);
|
||||
@ -243,7 +243,7 @@ int nrf52_gpio_unconfig(nrf52_pinset_t cfgset)
|
||||
|
||||
/* Configure as input and disconnect input buffer */
|
||||
|
||||
putreg32(NRF52_GPIO_CNF_INPUT, offset);
|
||||
putreg32(GPIO_CNF_INPUT, offset);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -91,8 +91,8 @@ static struct rng_dev_s g_rngdev;
|
||||
|
||||
static const struct file_operations g_rngops =
|
||||
{
|
||||
.open = nrf52_rng_open, /* open */
|
||||
.read = nrf52_rng_read, /* read */
|
||||
.open = nrf52_rng_open, /* open */
|
||||
.read = nrf52_rng_read, /* read */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
@ -104,11 +104,11 @@ static void nrf52_rng_start(void)
|
||||
irqstate_t flag;
|
||||
flag = enter_critical_section();
|
||||
|
||||
nrf52_event_clear(NRF52_RNG_EVENT_RDY);
|
||||
nrf52_event_clear(NRF52_RNG_EVENTS_RDY);
|
||||
|
||||
putreg32(1, NRF52_RNG_CONFIG);
|
||||
nrf52_interrupt_enable(NRF52_RNG_INT_SET, NRF52_RNG_INT_EVENT_RDY);
|
||||
nrf52_task_trigger(NRF52_RNG_T_START);
|
||||
nrf52_interrupt_enable(NRF52_RNG_INTSET, RNG_INT_RDY);
|
||||
nrf52_task_trigger(NRF52_RNG_TASKS_START);
|
||||
|
||||
up_enable_irq(NRF52_IRQ_RNG);
|
||||
|
||||
@ -122,10 +122,10 @@ static void nrf52_rng_stop(void)
|
||||
|
||||
up_disable_irq(NRF52_IRQ_RNG);
|
||||
|
||||
nrf52_task_trigger(NRF52_RNG_T_STOP);
|
||||
nrf52_interrupt_disable(NRF52_RNG_INT_CLR, NRF52_RNG_INT_EVENT_RDY);
|
||||
nrf52_task_trigger(NRF52_RNG_TASKS_STOP);
|
||||
nrf52_interrupt_disable(NRF52_RNG_INTCLR, RNG_INT_RDY);
|
||||
|
||||
nrf52_event_clear(NRF52_RNG_EVENT_RDY);
|
||||
nrf52_event_clear(NRF52_RNG_EVENTS_RDY);
|
||||
|
||||
leave_critical_section(flag);
|
||||
}
|
||||
@ -169,9 +169,9 @@ static int nrf52_rng_irqhandler(int irq, FAR void *context, FAR void *arg)
|
||||
FAR struct rng_dev_s *priv = (struct rng_dev_s *) &g_rngdev;
|
||||
uint8_t *addr;
|
||||
|
||||
if (getreg32(NRF52_RNG_EVENT_RDY) == NRF52_RNG_INT_EVENT_RDY)
|
||||
if (getreg32(NRF52_RNG_EVENTS_RDY) == RNG_INT_RDY)
|
||||
{
|
||||
nrf52_event_clear(NRF52_RNG_EVENT_RDY);
|
||||
nrf52_event_clear(NRF52_RNG_EVENTS_RDY);
|
||||
if (priv->rd_count < priv->buflen)
|
||||
{
|
||||
addr = priv->rd_buf + priv->rd_count++;
|
||||
|
||||
@ -192,7 +192,7 @@ static void nrf52_wdt_int_enable(uint32_t int_mask)
|
||||
|
||||
static void nrf52_wdt_task_trigger(void)
|
||||
{
|
||||
putreg32(NRF_WDT_TASK_SET, NRF52_WDT_TASKS_START);
|
||||
putreg32(1, NRF52_WDT_TASKS_START);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -213,7 +213,7 @@ static void nrf52_wdt_reload_request_set(int rr_register)
|
||||
{
|
||||
/* Each register is 32-bit (4 bytes), then multiply by 4 to get offset */
|
||||
|
||||
putreg32(NRF_WDT_RR_VALUE, NRF52_WDT_RR0 + (4 * rr_register));
|
||||
putreg32(WDT_RR_VALUE, NRF52_WDT_RR0 + (4 * rr_register));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -261,8 +261,8 @@ static void nrf52_wdt_reload_value_set(uint32_t reload_value)
|
||||
* Start the watchdog timer, resetting the time to the current timeout,
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
* lower - A pointer the publicly visible representation of the
|
||||
* "lower-half" driver state structure.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
@ -285,7 +285,7 @@ static int nrf52_start(FAR struct watchdog_lowerhalf_s *lower)
|
||||
flags = enter_critical_section();
|
||||
priv->lastreset = clock_systimer();
|
||||
priv->started = true;
|
||||
nrf52_wdt_int_enable(NRF_WDT_INT_TIMEOUT_MASK);
|
||||
nrf52_wdt_int_enable(WDT_INT_TIMEOUT);
|
||||
nrf52_wdt_task_trigger();
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
@ -300,8 +300,8 @@ static int nrf52_start(FAR struct watchdog_lowerhalf_s *lower)
|
||||
* Stop the watchdog timer
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
* lower - A pointer the publicly visible representation of the
|
||||
* "lower-half" driver state structure.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
@ -325,8 +325,8 @@ static int nrf52_stop(FAR struct watchdog_lowerhalf_s *lower)
|
||||
* the watchdog timer or "petting the dog".
|
||||
*
|
||||
* Input Parameters:
|
||||
* lower - A pointer the publicly visible representation of the "lower-half"
|
||||
* driver state structure.
|
||||
* lower - A pointer the publicly visible representation of the
|
||||
* "lower-half" driver state structure.
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
@ -460,7 +460,8 @@ static int nrf52_settimeout(FAR struct watchdog_lowerhalf_s *lower,
|
||||
|
||||
up_enable_irq(NRF52_IRQ_WDT);
|
||||
|
||||
wdinfo(" mode=%d priority=%d\n", WDT_CONFIG_MODE, WDT_CONFIG_IRQ_PRIORITY);
|
||||
wdinfo(" mode=%d priority=%d\n", WDT_CONFIG_MODE,
|
||||
WDT_CONFIG_IRQ_PRIORITY);
|
||||
|
||||
return OK;
|
||||
}
|
||||
@ -503,8 +504,8 @@ int nrf52_wdt_initialize(FAR const char *devpath, int16_t mode_sleep,
|
||||
|
||||
priv->ops = &g_wdtops;
|
||||
priv->started = false;
|
||||
priv->mode = (mode_halt << WDT_CONFIG_HALT_POS) |
|
||||
(mode_sleep << WDT_CONFIG_SLEEP_POS);
|
||||
priv->mode = (mode_halt << WDT_CONFIG_HALT) |
|
||||
(mode_sleep << WDT_CONFIG_SLEEP);
|
||||
|
||||
#if 0
|
||||
/* Request LSECLK firstly */
|
||||
|
||||
@ -44,29 +44,10 @@
|
||||
|
||||
#ifdef CONFIG_WATCHDOG
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define NRF_WDT_RR_VALUE 0x6E524635UL /* Fixed value, don't modify it */
|
||||
#define NRF_WDT_TASK_SET 1
|
||||
#define WDT_CONFIG_HALT_POS 3
|
||||
#define WDT_CONFIG_SLEEP_POS 0
|
||||
#define NRF_WDT_INT_TIMEOUT_MASK 1
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
enum wdt_behaviour_e
|
||||
{
|
||||
WDG_PAUSE = 0,
|
||||
@ -77,6 +58,15 @@ enum wdt_behaviour_e
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_wdt_initialize
|
||||
*
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user