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stm32 timers: Make some register operations more readable.

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This commit is contained in:
Anthony Merlino 2021-04-11 15:37:17 -04:00 committed by David Sidrane
parent 0cc0c3d503
commit 58c92be39c
18 changed files with 61 additions and 37 deletions
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2
arch/arm/src/stm32/hardware/stm32_tim_v1v2.h
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@ -826,6 +826,7 @@
# define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
# define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
#endif
#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */
@ -1222,6 +1223,7 @@
* no CC4N output, so it does not make sense!
*/
#endif
#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */

2
arch/arm/src/stm32/hardware/stm32_tim_v3.h
View File

@ -769,6 +769,7 @@
#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 Output Polarity */
#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 Output Enable */
#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 Output Polarity */
#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* ATIM Counter (CNT) */
@ -1236,6 +1237,7 @@
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 Output Enable */
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 Output Polarity */
#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 Complementary Output Polarity */
#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* GTIM Counter (CNT) */

6
arch/arm/src/stm32/stm32_capture.c
View File

@ -963,9 +963,9 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev,
/* Shift all CCER bits to corresponding channel */
mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP);
mask <<= (channel << 2);
regval <<= (channel << 2);
ccer_en_bit <<= (channel << 2);
mask <<= GTIM_CCER_CCXBASE(channel);
regval <<= GTIM_CCER_CCXBASE(channel);
ccer_en_bit <<= GTIM_CCER_CCXBASE(channel);
stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, mask, regval);

5
arch/arm/src/stm32/stm32_tickless.c
View File

@ -237,7 +237,8 @@ static int stm32_tickless_setchannel(uint8_t channel)
/* Assume that channel is disabled and polarity is active high */
ccer_val &= ~(3 << (channel << 2));
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
GTIM_CCER_CCXBASE(channel));
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
@ -264,7 +265,7 @@ static int stm32_tickless_setchannel(uint8_t channel)
/* Set polarity */
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
/* Define its position (shift) and get register offset */

7
arch/arm/src/stm32/stm32_tim.c
View File

@ -985,7 +985,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
/* Assume that channel is disabled and polarity is active high */
ccer_val &= ~(3 << (channel << 2));
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
GTIM_CCER_CCXBASE(channel));
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
@ -1014,7 +1015,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
case STM32_TIM_CH_OUTPWM:
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) +
ATIM_CCMR1_OC1PE;
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
break;
default:
@ -1025,7 +1026,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
if (mode & STM32_TIM_CH_POLARITY_NEG)
{
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
}
/* Define its position (shift) and get register offset */

2
arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
View File

@ -611,6 +611,7 @@
#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */
@ -1030,6 +1031,7 @@
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM3 only) */
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM3 only) */
#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity (TIM3 only) */
#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */

7
arch/arm/src/stm32f0l0g0/stm32_tim.c
View File

@ -969,7 +969,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
/* Assume that channel is disabled and polarity is active high */
ccer_val &= ~(3 << (channel << 2));
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
GTIM_CCER_CCXBASE(channel));
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
@ -991,7 +992,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
case STM32_TIM_CH_OUTPWM:
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) +
ATIM_CCMR1_OC1PE;
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
break;
default:
@ -1002,7 +1003,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
if (mode & STM32_TIM_CH_POLARITY_NEG)
{
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
}
/* Define its position (shift) and get register offset */

2
arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h
View File

@ -694,6 +694,7 @@
#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */
@ -1073,6 +1074,7 @@
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */

2
arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h
View File

@ -696,6 +696,7 @@
#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */
@ -1075,6 +1076,7 @@
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */

2
arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h
View File

@ -702,6 +702,7 @@
#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */
@ -1093,6 +1094,7 @@
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */

6
arch/arm/src/stm32f7/stm32_capture.c
View File

@ -969,9 +969,9 @@ static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev,
/* Shift all CCER bits to corresponding channel */
mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP);
mask <<= (channel << 2);
regval <<= (channel << 2);
ccer_en_bit <<= (channel << 2);
mask <<= GTIM_CCER_CCXBASE(channel);
regval <<= GTIM_CCER_CCXBASE(channel);
ccer_en_bit <<= GTIM_CCER_CCXBASE(channel);
stm32_modifyreg16(priv, STM32_GTIM_CCER_OFFSET, mask, regval);

23
arch/arm/src/stm32f7/stm32_tickless.c
View File

@ -113,13 +113,13 @@
#endif
#if CONFIG_STM32F7_TICKLESS_CHANNEL == 1
#define DIER_CAPT_IE ATIM_DIER_CC1IE
#define DIER_CAPT_IE GTIM_DIER_CC1IE
#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 2
#define DIER_CAPT_IE ATIM_DIER_CC2IE
#define DIER_CAPT_IE GTIM_DIER_CC2IE
#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 3
#define DIER_CAPT_IE ATIM_DIER_CC3IE
#define DIER_CAPT_IE GTIM_DIER_CC3IE
#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 4
#define DIER_CAPT_IE ATIM_DIER_CC4IE
#define DIER_CAPT_IE GTIM_DIER_CC4IE
#endif
/****************************************************************************
@ -248,7 +248,8 @@ static int stm32_tickless_setchannel(uint8_t channel)
/* Assume that channel is disabled and polarity is active high */
ccer_val &= ~(3 << (channel << 2));
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
GTIM_CCER_CCXBASE(channel));
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
@ -264,11 +265,11 @@ static int stm32_tickless_setchannel(uint8_t channel)
* disabled.
*/
ccmr_val = (ATIM_CCMR_MODE_FRZN << ATIM_CCMR1_OC1M_SHIFT);
ccmr_val = (GTIM_CCMR_MODE_FRZN << GTIM_CCMR1_OC1M_SHIFT);
/* Set polarity */
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
/* Define its position (shift) and get register offset */
@ -351,7 +352,7 @@ static void stm32_timing_handler(void)
{
g_tickless.overflow++;
STM32_TIM_ACKINT(g_tickless.tch, ATIM_SR_UIF);
STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF);
}
/****************************************************************************
@ -373,7 +374,7 @@ static int stm32_tickless_handler(int irq, void *context, void *arg)
{
int interrupt_flags = stm32_tickless_getint();
if (interrupt_flags & ATIM_SR_UIF)
if (interrupt_flags & GTIM_SR_UIF)
{
stm32_timing_handler();
}
@ -684,7 +685,7 @@ int up_timer_gettime(FAR struct timespec *ts)
overflow = g_tickless.overflow;
counter = STM32_TIM_GETCOUNTER(g_tickless.tch);
pending = STM32_TIM_CHECKINT(g_tickless.tch, ATIM_SR_UIF);
pending = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF);
verify = STM32_TIM_GETCOUNTER(g_tickless.tch);
/* If an interrupt was pending before we re-enabled interrupts,
@ -693,7 +694,7 @@ int up_timer_gettime(FAR struct timespec *ts)
if (pending)
{
STM32_TIM_ACKINT(g_tickless.tch, ATIM_SR_UIF);
STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF);
/* Increment the overflow count and use the value of the
* guaranteed to be AFTER the overflow occurred.

9
arch/arm/src/stm32f7/stm32_tim.c
View File

@ -750,7 +750,8 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
/* Assume that channel is disabled and polarity is active high */
ccer_val &= ~(3 << (channel << 2));
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
GTIM_CCER_CCXBASE(channel));
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
@ -772,13 +773,13 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
case STM32_TIM_CH_OUTPWM:
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) +
ATIM_CCMR1_OC1PE;
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
break;
case STM32_TIM_CH_OUTTOGGLE:
ccmr_val = (ATIM_CCMR_MODE_OCREFTOG << ATIM_CCMR1_OC1M_SHIFT) +
ATIM_CCMR1_OC1PE;
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
break;
default:
@ -789,7 +790,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev,
if (mode & STM32_TIM_CH_POLARITY_NEG)
{
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
}
/* Define its position (shift) and get register offset */

2
arch/arm/src/stm32l4/hardware/stm32l4_tim.h
View File

@ -674,6 +674,7 @@
#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */
@ -1049,6 +1050,7 @@
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */

5
arch/arm/src/stm32l4/stm32l4_adc.c
View File

@ -959,12 +959,13 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
/* Assume that channel is disabled and polarity is active high */
ccer_val = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET);
ccer_val &= ~(3 << (channel << 2));
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
GTIM_CCER_CCXBASE(channel));
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) |
(ATIM_CCMR_CCS_CCOUT << ATIM_CCMR1_CC1S_SHIFT) |
ATIM_CCMR1_OC1PE;
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
if (channel & 1)
{

7
arch/arm/src/stm32l4/stm32l4_tim.c
View File

@ -1157,7 +1157,8 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev,
/* Assume that channel is disabled and polarity is active high */
ccer_val = stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET);
ccer_val &= ~(3 << (channel << 2));
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
GTIM_CCER_CCXBASE(channel));
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
@ -1186,7 +1187,7 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev,
case STM32L4_TIM_CH_OUTPWM:
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) +
ATIM_CCMR1_OC1PE;
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
break;
default:
@ -1197,7 +1198,7 @@ static int stm32l4_tim_setchannel(FAR struct stm32l4_tim_dev_s *dev,
if (mode & STM32L4_TIM_CH_POLARITY_NEG)
{
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
}
/* Define its position (shift) and get register offset */

2
arch/arm/src/stm32l5/hardware/stm32l5_tim.h
View File

@ -625,6 +625,7 @@
#define ATIM_CCER_CC5P (1 << 17) /* Bit 17: Capture/Compare 5 output Polarity */
#define ATIM_CCER_CC6E (1 << 20) /* Bit 20: Capture/Compare 6 output enable */
#define ATIM_CCER_CC6P (1 << 21) /* Bit 21: Capture/Compare 6 output Polarity */
#define ATIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */
@ -970,6 +971,7 @@
#define GTIM_CCER_CC4E (1 << 12) /* Bit 12: Capture/Compare 4 output enable (TIM2-5 only) */
#define GTIM_CCER_CC4P (1 << 13) /* Bit 13: Capture/Compare 4 output Polarity (TIM2-5 only) */
#define GTIM_CCER_CC4NP (1 << 15) /* Bit 15: Capture/Compare 4 output Polarity */
#define GTIM_CCER_CCXBASE(ch) (ch << 2) /* Each channel uses 4-bits */
/* 16-bit counter register */

7
arch/arm/src/stm32l5/stm32l5_tim.c
View File

@ -943,7 +943,8 @@ static int stm32l5_tim_setchannel(FAR struct stm32l5_tim_dev_s *dev,
/* Assume that channel is disabled and polarity is active high */
ccer_val = stm32l5_getreg16(dev, STM32L5_GTIM_CCER_OFFSET);
ccer_val &= ~(3 << (channel << 2));
ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) <<
GTIM_CCER_CCXBASE(channel));
/* This function is not supported on basic timers. To enable or
* disable it, simply set its clock to valid frequency or zero.
@ -972,7 +973,7 @@ static int stm32l5_tim_setchannel(FAR struct stm32l5_tim_dev_s *dev,
case STM32L5_TIM_CH_OUTPWM:
ccmr_val = (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) +
ATIM_CCMR1_OC1PE;
ccer_val |= ATIM_CCER_CC1E << (channel << 2);
ccer_val |= ATIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel);
break;
default:
@ -983,7 +984,7 @@ static int stm32l5_tim_setchannel(FAR struct stm32l5_tim_dev_s *dev,
if (mode & STM32L5_TIM_CH_POLARITY_NEG)
{
ccer_val |= ATIM_CCER_CC1P << (channel << 2);
ccer_val |= ATIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel);
}
/* Define its position (shift) and get register offset */