sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

nxstyle: Fix existing long line to match code style

Browse Source 
Signed-off-by: Brennan Ashton <bashton@brennanashton.com>
This commit is contained in:
Brennan Ashton 2020-08-30 13:19:41 -07:00 committed by Matias N
parent 4cb193d530
commit 58e43adf08
4 changed files with 127 additions and 110 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

135
arch/arm/src/kinetis/kinetis_lowputc.c
View File

@ -310,15 +310,17 @@ void arm_lowputc(char ch)
* redesigning all of the FIFO status logic.
*/
while ((getreg8(CONSOLE_BASE+KINETIS_UART_S1_OFFSET) & UART_S1_TDRE) == 0);
while (
(getreg8(CONSOLE_BASE + KINETIS_UART_S1_OFFSET) & UART_S1_TDRE) == 0);
# endif
/* Then write the character to the UART data register */
putreg8((uint8_t)ch, CONSOLE_BASE+KINETIS_UART_D_OFFSET);
putreg8((uint8_t)ch, CONSOLE_BASE + KINETIS_UART_D_OFFSET);
#elif defined(HAVE_LPUART_CONSOLE)
while ((getreg32(CONSOLE_BASE + KINETIS_LPUART_STAT_OFFSET) & LPUART_STAT_TDRE) == 0);
while ((getreg32(CONSOLE_BASE + KINETIS_LPUART_STAT_OFFSET) &
LPUART_STAT_TDRE) == 0);
/* Then send the character */
@ -350,20 +352,20 @@ void kinetis_lowsetup(void)
# if defined(CONFIG_KINETIS_UART0) || defined(CONFIG_KINETIS_UART1) || \
defined(CONFIG_KINETIS_UART2) || defined(CONFIG_KINETIS_UART3)
regval = getreg32(KINETIS_SIM_SCGC4);
regval = getreg32(KINETIS_SIM_SCGC4);
# ifdef CONFIG_KINETIS_UART0
regval |= SIM_SCGC4_UART0;
regval |= SIM_SCGC4_UART0;
# endif
# ifdef CONFIG_KINETIS_UART1
regval |= SIM_SCGC4_UART1;
regval |= SIM_SCGC4_UART1;
# endif
# ifdef CONFIG_KINETIS_UART2
regval |= SIM_SCGC4_UART2;
regval |= SIM_SCGC4_UART2;
# endif
# ifdef CONFIG_KINETIS_UART3
regval |= SIM_SCGC4_UART3;
regval |= SIM_SCGC4_UART3;
# endif
putreg32(regval, KINETIS_SIM_SCGC4);
putreg32(regval, KINETIS_SIM_SCGC4);
# endif
@ -371,14 +373,14 @@ void kinetis_lowsetup(void)
# if defined(CONFIG_KINETIS_UART4) || defined(CONFIG_KINETIS_UART5)
regval = getreg32(KINETIS_SIM_SCGC1);
regval = getreg32(KINETIS_SIM_SCGC1);
# ifdef CONFIG_KINETIS_UART4
regval |= SIM_SCGC1_UART4;
regval |= SIM_SCGC1_UART4;
# endif
# ifdef CONFIG_KINETIS_UART5
regval |= SIM_SCGC1_UART5;
regval |= SIM_SCGC1_UART5;
# endif
putreg32(regval, KINETIS_SIM_SCGC1);
putreg32(regval, KINETIS_SIM_SCGC1);
# endif
@ -486,7 +488,7 @@ void kinetis_lowsetup(void)
# warning REVISIT
#endif
/* Configure UART pins for the all enabled UARTs */
/* Configure UART pins for the all enabled UARTs */
#ifdef CONFIG_KINETIS_LPUART0
kinetis_pinconfig(PIN_LPUART0_TX);
@ -567,9 +569,9 @@ void kinetis_uartreset(uintptr_t uart_base)
/* Just disable the transmitter and receiver */
regval = getreg8(uart_base+KINETIS_UART_C2_OFFSET);
regval = getreg8(uart_base + KINETIS_UART_C2_OFFSET);
regval &= ~(UART_C2_RE | UART_C2_TE);
putreg8(regval, uart_base+KINETIS_UART_C2_OFFSET);
putreg8(regval, uart_base + KINETIS_UART_C2_OFFSET);
}
#endif
@ -588,9 +590,9 @@ void kinetis_lpuartreset(uintptr_t uart_base)
/* Just disable the transmitter and receiver */
regval = getreg32(uart_base+KINETIS_LPUART_CTRL_OFFSET);
regval = getreg32(uart_base + KINETIS_LPUART_CTRL_OFFSET);
regval &= ~(LPUART_CTRL_RE | LPUART_CTRL_TE);
putreg32(regval, uart_base+KINETIS_LPUART_CTRL_OFFSET);
putreg32(regval, uart_base + KINETIS_LPUART_CTRL_OFFSET);
}
#endif
@ -618,9 +620,9 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
/* Disable the transmitter and receiver throughout the reconfiguration */
regval = getreg8(uart_base+KINETIS_UART_C2_OFFSET);
regval = getreg8(uart_base + KINETIS_UART_C2_OFFSET);
regval &= ~(UART_C2_RE | UART_C2_TE);
putreg8(regval, uart_base+KINETIS_UART_C2_OFFSET);
putreg8(regval, uart_base + KINETIS_UART_C2_OFFSET);
/* Configure number of bits, stop bits and parity */
@ -664,7 +666,7 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
DEBUGASSERT(nbits == 8);
}
putreg8(regval, uart_base+KINETIS_UART_C1_OFFSET);
putreg8(regval, uart_base + KINETIS_UART_C1_OFFSET);
/* Calculate baud settings (truncating) */
@ -675,18 +677,19 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
* UARTx_BDH register.
*/
regval = getreg8(uart_base+KINETIS_UART_BDH_OFFSET);
regval = getreg8(uart_base + KINETIS_UART_BDH_OFFSET);
regval &= ~(UART_BDH_SBR_MASK | UART_BDH_SBNS);
if (stop2)
{
regval |= UART_BDH_SBNS;
}
tmp = sbr >> 8;
regval |= (((uint8_t)tmp) << UART_BDH_SBR_SHIFT) & UART_BDH_SBR_MASK;
putreg8(regval, uart_base+KINETIS_UART_BDH_OFFSET);
putreg8(regval, uart_base + KINETIS_UART_BDH_OFFSET);
regval = sbr & 0xff;
putreg8(regval, uart_base+KINETIS_UART_BDL_OFFSET);
putreg8(regval, uart_base + KINETIS_UART_BDL_OFFSET);
/* Calculate a fractional divider to get closer to the requested baud.
* The fractional divider, BRFA, is a 5 bit fractional value that is
@ -703,9 +706,9 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
/* Set the BRFA field (retaining other bits in the UARTx_C4 register) */
regval = getreg8(uart_base+KINETIS_UART_C4_OFFSET) & ~UART_C4_BRFA_MASK;
regval = getreg8(uart_base + KINETIS_UART_C4_OFFSET) & ~UART_C4_BRFA_MASK;
regval |= ((uint8_t)brfa << UART_C4_BRFA_SHIFT) & UART_C4_BRFA_MASK;
putreg8(regval, uart_base+KINETIS_UART_C4_OFFSET);
putreg8(regval, uart_base + KINETIS_UART_C4_OFFSET);
/* Set the FIFO watermarks.
*
@ -720,25 +723,28 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
*/
#ifdef CONFIG_KINETIS_UARTFIFOS
depth = g_sizemap[(regval & UART_PFIFO_RXFIFOSIZE_MASK) >> UART_PFIFO_RXFIFOSIZE_SHIFT];
depth = g_sizemap[(regval & UART_PFIFO_RXFIFOSIZE_MASK) >>
UART_PFIFO_RXFIFOSIZE_SHIFT];
if (depth > 1)
{
depth = (3 * depth) >> 2;
}
putreg8(depth , uart_base+KINETIS_UART_RWFIFO_OFFSET);
putreg8(depth , uart_base + KINETIS_UART_RWFIFO_OFFSET);
depth = g_sizemap[(regval & UART_PFIFO_TXFIFOSIZE_MASK) >> UART_PFIFO_TXFIFOSIZE_SHIFT];
depth = g_sizemap[(regval & UART_PFIFO_TXFIFOSIZE_MASK) >>
UART_PFIFO_TXFIFOSIZE_SHIFT];
if (depth > 3)
{
depth = (depth >> 2);
}
putreg8(depth, uart_base+KINETIS_UART_TWFIFO_OFFSET);
putreg8(depth, uart_base + KINETIS_UART_TWFIFO_OFFSET);
/* Enable RX and TX FIFOs */
putreg8(UART_PFIFO_RXFE | UART_PFIFO_TXFE, uart_base+KINETIS_UART_PFIFO_OFFSET);
putreg8(UART_PFIFO_RXFE | UART_PFIFO_TXFE,
uart_base + KINETIS_UART_PFIFO_OFFSET);
#else
/* Otherwise, disable the FIFOs. Then the FIFOs are disable, the effective
* FIFO depth is 1. So set the watermarks as follows:
@ -751,14 +757,14 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
* Set the watermarks to one/zero and disable the FIFOs
*/
putreg8(1, uart_base+KINETIS_UART_RWFIFO_OFFSET);
putreg8(0, uart_base+KINETIS_UART_TWFIFO_OFFSET);
putreg8(0, uart_base+KINETIS_UART_PFIFO_OFFSET);
putreg8(1, uart_base + KINETIS_UART_RWFIFO_OFFSET);
putreg8(0, uart_base + KINETIS_UART_TWFIFO_OFFSET);
putreg8(0, uart_base + KINETIS_UART_PFIFO_OFFSET);
#endif
/* Hardware flow control */
regval = getreg8(uart_base+KINETIS_UART_MODEM_OFFSET);
regval = getreg8(uart_base + KINETIS_UART_MODEM_OFFSET);
regval &= ~(UART_MODEM_TXCTSE | UART_MODEM_RXRTSE);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
@ -775,13 +781,13 @@ void kinetis_uartconfigure(uintptr_t uart_base, uint32_t baud,
}
#endif
putreg8(regval, uart_base+KINETIS_UART_MODEM_OFFSET);
putreg8(regval, uart_base + KINETIS_UART_MODEM_OFFSET);
/* Now we can (re-)enable the transmitter and receiver */
regval = getreg8(uart_base+KINETIS_UART_C2_OFFSET);
regval = getreg8(uart_base + KINETIS_UART_C2_OFFSET);
regval |= (UART_C2_RE | UART_C2_TE);
putreg8(regval, uart_base+KINETIS_UART_C2_OFFSET);
putreg8(regval, uart_base + KINETIS_UART_C2_OFFSET);
}
#endif
@ -839,45 +845,45 @@ void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud,
for (osr = 32; osr >= 4; osr--)
{
sbr = clock / (baud * osr);
sbr = clock / (baud * osr);
/* Ensure the minimum SBR */
/* Ensure the minimum SBR */
if (sbr == 0)
{
sbr++;
}
if (sbr == 0)
{
sbr++;
}
/* Calculate the actual baud rate */
/* Calculate the actual baud rate */
current_baud = clock / (sbr * osr);
current_baud = clock / (sbr * osr);
/* look at the deviation of current baud to requested */
/* look at the deviation of current baud to requested */
baud_error = current_baud - baud;
if (baud_error <= min_baud_error)
{
min_baud_error = baud_error;
actual_baud = current_baud;
sbrreg = sbr;
osrreg = osr;
}
baud_error = current_baud - baud;
if (baud_error <= min_baud_error)
{
min_baud_error = baud_error;
actual_baud = current_baud;
sbrreg = sbr;
osrreg = osr;
}
}
UNUSED(actual_baud);
DEBUGASSERT(actual_baud-baud < (baud /100) * 2);
DEBUGASSERT(actual_baud - baud < (baud / 100) * 2);
DEBUGASSERT(sbrreg != 0 && sbrreg < 8192);
DEBUGASSERT(osrreg != 0);
/* Disable the transmitter and receiver throughout the reconfiguration */
regval = getreg32(uart_base+KINETIS_LPUART_CTRL_OFFSET);
regval = getreg32(uart_base + KINETIS_LPUART_CTRL_OFFSET);
regval &= ~(LPUART_CTRL_RE | LPUART_CTRL_TE);
putreg32(regval, uart_base+KINETIS_LPUART_CTRL_OFFSET);
putreg32(regval, uart_base + KINETIS_LPUART_CTRL_OFFSET);
/* Reset the BAUD register */
regval = getreg32(uart_base+KINETIS_LPUART_BAUD_OFFSET);
regval = getreg32(uart_base + KINETIS_LPUART_BAUD_OFFSET);
regval &= ~(LPUART_BAUD_INIT);
/* Set the Baud rate, nbits and stop bits */
@ -906,7 +912,7 @@ void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud,
regval |= LPUART_BAUD_BOTHEDGE;
}
putreg32(regval, uart_base+KINETIS_LPUART_BAUD_OFFSET);
putreg32(regval, uart_base + KINETIS_LPUART_BAUD_OFFSET);
/* Configure number of bits and parity */
@ -949,7 +955,7 @@ void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud,
/* Hardware flow control */
regval = getreg32(uart_base+KINETIS_LPUART_MODIR_OFFSET);
regval = getreg32(uart_base + KINETIS_LPUART_MODIR_OFFSET);
regval &= ~(UART_MODEM_TXCTSE | UART_MODEM_RXRTSE);
#ifdef CONFIG_SERIAL_IFLOWCONTROL
@ -957,18 +963,21 @@ void kinetis_lpuartconfigure(uintptr_t uart_base, uint32_t baud,
{
regval |= LPUART_MODIR_RXRTSE;
}
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
if (oflow)
{
regval |= LPUART_MODIR_TXCTSE;
}
#endif
putreg32(regval, uart_base+KINETIS_LPUART_MODIR_OFFSET);
putreg32(regval, uart_base + KINETIS_LPUART_MODIR_OFFSET);
/* Now we can (re-)enable the transmitter and receiver */
regval |= (LPUART_CTRL_RE | LPUART_CTRL_TE);
putreg32(regval, uart_base+KINETIS_LPUART_CTRL_OFFSET);
putreg32(regval, uart_base + KINETIS_LPUART_CTRL_OFFSET);
}
#endif

24
arch/arm/src/lpc17xx_40xx/hardware/lpc17_40_i2s.h
View File

@ -100,6 +100,7 @@
#define I2S_DAO_WSHALFPER_MASK (0x01ff << I2S_DAO_WSHALFPER_SHIFT)
#define I2S_DAO_MUTE (1 << 15) /* Bit 15: Send only zeros on channel */
/* Bits 16-31: Reserved */
/* Digital Audio Input Register */
#define I2S_DAI_WDWID_SHIFT (0) /* Bits 0-1: Selects the number of bytes in data */
@ -114,8 +115,10 @@
#define I2S_DAI_WSHALFPER_SHIFT (6) /* Bits 6-14: Word select half period minus 1 */
#define I2S_DAI_WSHALFPER_MASK (0x01ff << I2S_DAI_WSHALFPER_SHIFT)
/* Bits 15-31: Reserved */
/* Transmit FIFO: 8 - 32-bit transmit FIFO */
/* Receive FIFO: 8 - 32-bit receive FIFO */
/* Transmit FIFO: 8 - 32-bit transmit FIFO
* Receive FIFO: 8 - 32-bit receive FIFO
*/
/* Status Feedback Register */
@ -129,6 +132,7 @@
#define I2S_STATE_TXLEVEL_SHIFT (16) /* Bits 16-19: Current level of the Transmit FIFO */
#define I2S_STATE_TXLEVEL_MASK (15 << I2S_STATE_TXLEVEL_SHIFT)
/* Bits 20-31: Reserved */
/* DMA Configuration Register 1 and 2 */
#define I2S_DMA_RXDMAEN (1 << 0) /* Bit 0: Enable DMA1 for I2S receive */
@ -140,6 +144,7 @@
#define I2S_DMA_TXDEPTH_SHIFT (16) /* Bits 16-19: FIFO level that triggers a TX request on DMA1 */
#define I2S_DMA_TXDEPTH_MASK (15 << I2S_DMA_TXDEPTH_SHIFT)
/* Bits 20-31: Reserved */
/* Interrupt Request Control Register */
#define I2S_IRQ_RXEN (1 << 0) /* Bit 0: Enable I2S receive interrupt */
@ -151,6 +156,7 @@
#define I2S_IRQ_TXDEPTH_SHIFT (16) /* Bits 16-19: Set FIFO level for irq request */
#define I2S_IRQ_TXDEPTH_MASK (15 << I2S_IRQ_TXDEPTH_SHIFT)
/* Bits 20-31: Reserved */
/* Transmit and Receive MCLK divider */
#define I2S_RATE_YDIV_SHIFT (0) /* Bits 0-7: I2S transmit MCLK rate denominator */
@ -164,6 +170,7 @@
#define I2S_BITRATE_SHIFT (0) /* Bits 0-5: I2S transmit bit rate */
#define I2S_BITRATE_MASK (0x3f << I2S_BITRATE_SHIFT)
/* Bits 6-31: Reserved */
/* Transmit and Receive mode control */
#define I2S_MODE_CLKSEL_SHIFT (0) /* Bits 0-1: Clock source for bit clock divider */
@ -171,20 +178,9 @@
# define I2S_MODE_CLKSEL_FRACDIV (0 << I2S_MODE_CLKSEL_SHIFT) /* TX/RX fractional rate divider */
# define I2S_MODE_CLKSEL_RXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* RX_CLCK for TX_MCLK source */
# define I2S_MODE_CLKSEL_TXMCLK (2 << I2S_MODE_CLKSEL_SHIFT) /* TX_CLCK for RX_MCLK source */
#define I2S_MODE_4PIN (1 << 2) /* Bit 2: Transmit/Receive 4-pin mode selection */
#define I2S_MODE_MCENA (1 << 3) /* Bit 3: Enable for the TX/RX_MCLK output */
/* Bits 4-31: Reserved */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC17XX_40XX_HARDWARE_LPC17_40_I2S_H */

68
arch/arm/src/lpc43xx/lpc43_serial.c
View File

@ -433,7 +433,8 @@ static inline uint32_t up_serialin(struct up_dev_s *priv, int offset)
* Name: up_serialout
****************************************************************************/
static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value)
static inline void up_serialout(struct up_dev_s *priv, int offset,
uint32_t value)
{
putreg32(value, priv->uartbase + offset);
}
@ -507,11 +508,13 @@ static int up_setup(struct uart_dev_s *dev)
/* Clear fifos */
up_serialout(priv, LPC43_UART_FCR_OFFSET, (UART_FCR_RXRST | UART_FCR_TXRST));
up_serialout(priv, LPC43_UART_FCR_OFFSET,
(UART_FCR_RXRST | UART_FCR_TXRST));
/* Set trigger */
up_serialout(priv, LPC43_UART_FCR_OFFSET, (UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8));
up_serialout(priv, LPC43_UART_FCR_OFFSET,
(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_8));
/* Set up the IER */
@ -563,7 +566,8 @@ static int up_setup(struct uart_dev_s *dev)
#ifdef CONFIG_UART1_FLOWCONTROL
if (priv->id == 1)
{
up_serialout(priv, LPC43_UART_MCR_OFFSET, (UART_MCR_RTSEN | UART_MCR_CTSEN));
up_serialout(priv, LPC43_UART_MCR_OFFSET,
(UART_MCR_RTSEN | UART_MCR_CTSEN));
}
#endif
@ -642,14 +646,15 @@ static void up_shutdown(struct uart_dev_s *dev)
* Name: up_attach
*
* Description:
* Configure the UART to operation in interrupt driven mode. This method is
* called when the serial port is opened. Normally, this is just after the
* the setup() method is called, however, the serial console may operate in
* a non-interrupt driven mode during the boot phase.
* Configure the UART to operation in interrupt driven mode. This method
* is called when the serial port is opened. Normally, this is just
* after the the setup() method is called, however, the serial console may
* operate in a non-interrupt driven mode during the boot phase.
*
* RX and TX interrupts are not enabled when by the attach method (unless the
* hardware supports multiple levels of interrupt enabling). The RX and TX
* interrupts are not enabled until the txint() and rxint() methods are called.
* RX and TX interrupts are not enabled when by the attach method (unless
* the hardware supports multiple levels of interrupt enabling). The RX
* and TX interrupts are not enabled until the txint() and rxint() methods
* are called.
*
****************************************************************************/
@ -678,8 +683,8 @@ static int up_attach(struct uart_dev_s *dev)
*
* Description:
* Detach UART interrupts. This method is called when the serial port is
* closed normally just before the shutdown method is called. The exception is
* the serial console which is never shutdown.
* closed normally just before the shutdown method is called. The
* exception is the serial console which is never shutdown.
*
****************************************************************************/
@ -804,10 +809,10 @@ static int up_interrupt(int irq, void *context, void *arg)
*
* RS-485/EIA-485 Normal Multidrop Mode (NMM) -- NOT supported
*
* In this mode, an address is detected when a received byte causes the
* USART to set the parity error and generate an interrupt. When the
* parity error interrupt will be generated and the processor can decide
* whether or not to disable the receiver.
* In this mode, an address is detected when a received byte causes
* the USART to set the parity error and generate an interrupt. When
* the parity error interrupt will be generated and the processor can
* decide whether or not to disable the receiver.
*
* RS-485/EIA-485 Auto Address Detection (AAD) mode -- NOT supported
*
@ -818,21 +823,23 @@ static int up_interrupt(int irq, void *context, void *arg)
* will be automatically enabled.
*
* When an address byte which does not match the RS485ADRMATCH value
* is received, the receiver will be automatically disabled in hardware.
* is received, the receiver will be automatically disabled in
* hardware.
*
* RS-485/EIA-485 Auto Direction Control -- Supported
*
* Allow the transmitter to automatically control the state of the DIR
* pin as a direction control output signal. The DIR pin will be asserted
* (driven LOW) when the CPU writes data into the TXFIFO. The pin will be
* de-asserted (driven HIGH) once the last bit of data has been transmitted.
* pin as a direction control output signal. The DIR pin will be
* asserted (driven LOW) when the CPU writes data into the TXFIFO. The
* pin will be de-asserted (driven HIGH) once the last bit of data has
* been transmitted.
*
* RS485/EIA-485 driver delay time -- Supported
*
* The driver delay time is the delay between the last stop bit leaving
* the TXFIFO and the de-assertion of the DIR pin. This delay time can be
* programmed in the 8-bit RS485DLY register. The delay time is in periods
* of the baud clock.
* the TXFIFO and the de-assertion of the DIR pin. This delay time can
* be programmed in the 8-bit RS485DLY register. The delay time is in
* periods of the baud clock.
*
* RS485/EIA-485 output inversion -- Supported
*
@ -991,8 +998,9 @@ static inline int up_get_rs485_mode(struct up_dev_s *priv,
}
/* We only have control of the delay after send. Time must be
* returned in milliseconds; this must be converted from the baud clock.
* (The baud clock should be 16 times the currently selected BAUD.)
* returned in milliseconds; this must be converted from the baud
* clock. (The baud clock should be 16 times the currently
* selected BAUD.)
*
* msec = 1000 * dly / baud
*/
@ -1100,15 +1108,15 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef HAVE_RS485
case TIOCSRS485: /* Set RS485 mode, arg: pointer to struct serial_rs485 */
{
ret = up_set_rs485_mode(priv,
(const struct serial_rs485 *)((uintptr_t)arg));
ret = up_set_rs485_mode(
priv, (const struct serial_rs485 *)((uintptr_t)arg));
}
break;
case TIOCGRS485: /* Get RS485 mode, arg: pointer to struct serial_rs485 */
{
ret = up_get_rs485_mode(priv,
(struct serial_rs485 *)((uintptr_t)arg));
ret = up_get_rs485_mode(
priv, (struct serial_rs485 *)((uintptr_t)arg));
}
break;
#endif

10
boards/arm/sama5/sama5d2-xult/include/board_498mhz.h
View File

@ -106,7 +106,7 @@
#define BOARD_PLLA_FREQUENCY (996000000) /* PLLACK: 83 * 12Mhz / 1 */
#define BOARD_PCK_FREQUENCY (498000000) /* CPU: PLLACK / 2 / 1 */
#define BOARD_MCK_FREQUENCY (166000000) /* MCK: PLLACK / 1 / 1 / 3 */
#define BOARD_ADCCLK_FREQUENCY (83000000) /* ADCCLK: MCK / ((7+1)*2) */
#define BOARD_ADCCLK_FREQUENCY (83000000) /* ADCCLK: MCK / ((7+1)*2) */
/* Clocking to certain peripherals may be MCK/2.
*
@ -161,11 +161,15 @@
* Where CLKDIV has a range of 0-255.
*/
/* MCK = 132MHz, CLKDIV = 164, MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz */
/* MCK = 132MHz, CLKDIV = 164,
* MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz
*/
#define HSMCI_INIT_CLKDIV (164 << HSMCI_MR_CLKDIV_SHIFT)
/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD, MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz */
/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD,
* MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz
*/
#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)