Merged in raiden00/nuttx (pull request #279)
STM32F33: Move DMA logic to a separate files + add ADC support Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Mateusz Szafoni
Gregory Nutt
commit
5907ec8cf9
366
arch/arm/src/stm32/chip/stm32f33xxx_dma.h
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366
arch/arm/src/stm32/chip/stm32f33xxx_dma.h
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@ -0,0 +1,366 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f33xxx_dma.h
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*
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* Copyright (C) 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* 12 Channels Total: 7 DMA1 Channels(1-7) and 5 DMA2 channels (1-5) */
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#define DMA1 0
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#define DMA2 1
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#define DMA3 2
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#define DMA4 3
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#define DMA5 4
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#define DMA6 5
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#define DMA7 6
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/* Register Offsets *****************************************************************/
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#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
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#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
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#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
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#define STM32_DMACHAN1_OFFSET 0x0000
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#define STM32_DMACHAN2_OFFSET 0x0014
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#define STM32_DMACHAN3_OFFSET 0x0028
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#define STM32_DMACHAN4_OFFSET 0x003c
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#define STM32_DMACHAN5_OFFSET 0x0050
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#define STM32_DMACHAN6_OFFSET 0x0064
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#define STM32_DMACHAN7_OFFSET 0x0078
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#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */
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#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */
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#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */
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#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel 1 memory address register */
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#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n))
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#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */
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#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */
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#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */
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#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */
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#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */
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#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */
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#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */
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#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */
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#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */
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#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */
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#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */
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#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */
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#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */
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#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */
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#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */
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#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */
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#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */
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#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */
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#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */
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#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */
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#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */
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#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */
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#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */
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#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */
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#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */
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#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */
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#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */
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#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */
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/* Register Addresses ***************************************************************/
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#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET)
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#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET)
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#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n))
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#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET)
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#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET)
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#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET)
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#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET)
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#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET)
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#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET)
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#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET)
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#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n))
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#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET)
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#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET)
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#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET)
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#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET)
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#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET)
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#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET)
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#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET)
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#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n))
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#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET)
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#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET)
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#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET)
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#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET)
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#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET)
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#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET)
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#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET)
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#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n))
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#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET)
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#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET)
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#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET)
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#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET)
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#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET)
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#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET)
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#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET)
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#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET)
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#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET)
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#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n))
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#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET)
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#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET)
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#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET)
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#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET)
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#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET)
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#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n))
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#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET)
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#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET)
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#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET)
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#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET)
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#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET)
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#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n))
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#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET)
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#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET)
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#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET)
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#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET)
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#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET)
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#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n))
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#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET)
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#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET)
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#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET)
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#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET)
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#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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#define DMA_CHAN_SHIFT(n) ((n) << 2)
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#define DMA_CHAN_MASK 0x0f
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#define DMA_CHAN_GIF_BIT (1 << 0) /* Bit 0: Channel Global interrupt flag */
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#define DMA_CHAN_TCIF_BIT (1 << 1) /* Bit 1: Channel Transfer Complete flag */
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#define DMA_CHAN_HTIF_BIT (1 << 2) /* Bit 2: Channel Half Transfer flag */
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#define DMA_CHAN_TEIF_BIT (1 << 3) /* Bit 3: Channel Transfer Error flag */
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/* DMA interrupt status register */
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#define DMA_ISR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
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#define DMA_ISR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_ISR_CHAN_SHIFT(n))
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#define DMA_ISR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt status */
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#define DMA_ISR_CHAN1_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN1_SHIFT)
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#define DMA_ISR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt status */
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#define DMA_ISR_CHAN2_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN2_SHIFT)
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#define DMA_ISR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt status */
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#define DMA_ISR_CHAN3_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN3_SHIFT)
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#define DMA_ISR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt status */
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#define DMA_ISR_CHAN4_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN4_SHIFT)
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#define DMA_ISR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt status */
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#define DMA_ISR_CHAN5_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN5_SHIFT)
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#define DMA_ISR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt status */
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#define DMA_ISR_CHAN6_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN6_SHIFT)
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#define DMA_ISR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt status */
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#define DMA_ISR_CHAN7_MASK (DMA_CHAN_MASK << DMA_ISR_CHAN7_SHIFT)
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#define DMA_ISR_GIF(n) (DMA_CHAN_GIF_BIT << DMA_ISR_CHAN_SHIFT(n))
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#define DMA_ISR_TCIF(n) (DMA_CHAN_TCIF_BIT << DMA_ISR_CHAN_SHIFT(n))
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#define DMA_ISR_HTIF(n) (DMA_CHAN_HTIF_BIT << DMA_ISR_CHAN_SHIFT(n))
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#define DMA_ISR_TEIF(n) (DMA_CHAN_TEIF_BIT << DMA_ISR_CHAN_SHIFT(n))
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/* DMA interrupt flag clear register */
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#define DMA_IFCR_CHAN_SHIFT(n) DMA_CHAN_SHIFT(n)
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#define DMA_IFCR_CHAN_MASK(n) (DMA_CHAN_MASK << DMA_IFCR_CHAN_SHIFT(n))
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#define DMA_IFCR_CHAN1_SHIFT (0) /* Bits 3-0: DMA Channel 1 interrupt flag clear */
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#define DMA_IFCR_CHAN1_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN1_SHIFT)
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#define DMA_IFCR_CHAN2_SHIFT (4) /* Bits 7-4: DMA Channel 2 interrupt flag clear */
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#define DMA_IFCR_CHAN2_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN2_SHIFT)
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#define DMA_IFCR_CHAN3_SHIFT (8) /* Bits 11-8: DMA Channel 3 interrupt flag clear */
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#define DMA_IFCR_CHAN3_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN3_SHIFT)
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#define DMA_IFCR_CHAN4_SHIFT (12) /* Bits 15-12: DMA Channel 4 interrupt flag clear */
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#define DMA_IFCR_CHAN4_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN4_SHIFT)
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#define DMA_IFCR_CHAN5_SHIFT (16) /* Bits 19-16: DMA Channel 5 interrupt flag clear */
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#define DMA_IFCR_CHAN5_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN5_SHIFT)
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#define DMA_IFCR_CHAN6_SHIFT (20) /* Bits 23-20: DMA Channel 6 interrupt flag clear */
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#define DMA_IFCR_CHAN6_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN6_SHIFT)
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#define DMA_IFCR_CHAN7_SHIFT (24) /* Bits 27-24: DMA Channel 7 interrupt flag clear */
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#define DMA_IFCR_CHAN7_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN7_SHIFT)
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#define DMA_IFCR_ALLCHANNELS (0x0fffffff)
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#define DMA_IFCR_CGIF(n) (DMA_CHAN_GIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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#define DMA_IFCR_CTCIF(n) (DMA_CHAN_TCIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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#define DMA_IFCR_CHTIF(n) (DMA_CHAN_HTIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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#define DMA_IFCR_CTEIF(n) (DMA_CHAN_TEIF_BIT << DMA_IFCR_CHAN_SHIFT(n))
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/* DMA channel configuration register */
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#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
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#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
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#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
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#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
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#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
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#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
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#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
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#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
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#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
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#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
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# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
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# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
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# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
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#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
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#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
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# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
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# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
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# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
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#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
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#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
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# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
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# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
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# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
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# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
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#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
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#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
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/* DMA channel number of data register */
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#define DMA_CNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
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#define DMA_CNDTR_NDT_MASK (0xffff << DMA_CNDTR_NDT_SHIFT)
|
||||
|
||||
/* DMA Channel mapping. Each DMA channel has a mapping to several possible
|
||||
* sources/sinks of data. The requests from peripherals assigned to a channel
|
||||
* are simply OR'ed together before entering the DMA block. This means that only
|
||||
* one request on a given channel can be enabled at once.
|
||||
*
|
||||
* Alternative DMA channel selections are provided with a numeric suffix like _1,
|
||||
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
|
||||
* Additional definitions are required in the board.h file.
|
||||
*/
|
||||
|
||||
#define STM32_DMA1_CHAN1 (0)
|
||||
#define STM32_DMA1_CHAN2 (1)
|
||||
#define STM32_DMA1_CHAN3 (2)
|
||||
#define STM32_DMA1_CHAN4 (3)
|
||||
#define STM32_DMA1_CHAN5 (4)
|
||||
#define STM32_DMA1_CHAN6 (5)
|
||||
#define STM32_DMA1_CHAN7 (6)
|
||||
|
||||
#define STM32_DMA2_CHAN1 (7)
|
||||
#define STM32_DMA2_CHAN2 (8)
|
||||
#define STM32_DMA2_CHAN3 (9)
|
||||
#define STM32_DMA2_CHAN4 (10)
|
||||
#define STM32_DMA2_CHAN5 (11)
|
||||
|
||||
#define DMACHAN_ADC1 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM17_CH1_1 STM32_DMA1_CHAN1
|
||||
#define DMACHAN_TIM17_UP_1 STM32_DMA1_CHAN1
|
||||
|
||||
#define DMACHAN_ADC2_1 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_SPI1_RX_1 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_USART3_TX STM32_DMA1_CHAN2
|
||||
#define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
|
||||
#define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
|
||||
#define DMACHAN_HRTIM1_M STM32_DMA1_CHAN2
|
||||
|
||||
#define DMACHAN_SPI1_TX_1 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_USART3_RX STM32_DMA1_CHAN3
|
||||
#define DMACHAN_I2C1_RX_2 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
|
||||
#define DMACHAN_TIM6_UP STM32_DMA1_CHAN3
|
||||
#define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_DAC16_CH1_1 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_DAC16_UP_1 STM32_DMA1_CHAN3
|
||||
#define DMACHAN_HRTIM1_A STM32_DMA1_CHAN3
|
||||
|
||||
#define DMACHAN_ADC2_2 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_SPI1_RX_2 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_USART1_TX STM32_DMA1_CHAN4
|
||||
#define DMACHAN_I2C1_TX_3 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
|
||||
#define DMACHAN_TIM7_UP STM32_DMA1_CHAN4
|
||||
#define DMACHAN_DAC2_CH2 STM32_DMA1_CHAN4
|
||||
#define DMACHAN_HRTIM1_B STM32_DMA1_CHAN4
|
||||
|
||||
#define DMACHAN_SPI1_TX_2 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_USART1_RX STM32_DMA1_CHAN5
|
||||
#define DMACHAN_I2C1_RX_3 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM15_UP STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5
|
||||
#define DMACHAN_TIM15_COM STM32_DMA1_CHAN5
|
||||
#define DMACHAN_HRTIM1_C STM32_DMA1_CHAN5
|
||||
|
||||
#define DMACHAN_SPI1_RX_3 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_USART2_RX STM32_DMA1_CHAN6
|
||||
#define DMACHAN_I2C1_TX_1 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM16_CH1_2 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_TIM16_UP_2 STM32_DMA1_CHAN6
|
||||
#define DMACHAN_HRTIM1_D STM32_DMA1_CHAN6
|
||||
|
||||
#define DMACHAN_SPI1_TX_3 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_USART2_TX STM32_DMA1_CHAN7
|
||||
#define DMACHAN_I2C1_RX_1 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7
|
||||
#define DMACHAN_HRTIM1_E STM32_DMA1_CHAN7
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_DMA_H */
|
||||
@ -6,6 +6,7 @@
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Diego Sanchez <dsanchez@nx-engineering.com>
|
||||
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
|
||||
* Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -77,11 +78,12 @@
|
||||
#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \
|
||||
defined(CONFIG_STM32_ADC3) || defined(CONFIG_STM32_ADC4)
|
||||
|
||||
/* This implementation is for the STM32 F1, F2, F4 and STM32L15XX only */
|
||||
/* This implementation is for the STM32 F1, F2, F3, F4 and STM32L15XX only */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
|
||||
/* At the moment there is no proper implementation for timers external
|
||||
* trigger in STM32L15XX May be added latter
|
||||
@ -91,6 +93,14 @@
|
||||
# warning "There is no proper implementation for TIMER TRIGGERS at the moment"
|
||||
#endif
|
||||
|
||||
/* At the moment there is no proper implementation for HRTIMER external
|
||||
* trigger in STM32F33XX
|
||||
*/
|
||||
|
||||
#if defined(ADC_HAVE_HRTIMER) && defined(CONFIG_STM32_STM32F33XX)
|
||||
# warning "There is no proper implementation for HRTIMER TRIGGERS at the moment"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
@ -108,6 +118,10 @@
|
||||
# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST
|
||||
# define RCC_RSTR_ADC3RST RCC_AHBRSTR_ADC34RST
|
||||
# define RCC_RSTR_ADC4RST RCC_AHBRSTR_ADC34RST
|
||||
#elif defined(CONFIG_STM32_STM32F33XX)
|
||||
# define STM32_RCC_RSTR STM32_RCC_AHBRSTR
|
||||
# define RCC_RSTR_ADC1RST RCC_AHBRSTR_ADC12RST
|
||||
# define RCC_RSTR_ADC2RST RCC_AHBRSTR_ADC12RST
|
||||
#elif defined(CONFIG_STM32_STM32F37XX)
|
||||
# define STM32_RCC_RSTR STM32_RCC_APB2RSTR
|
||||
# define RCC_RSTR_ADC1RST RCC_APB2RSTR_ADCRST
|
||||
@ -124,7 +138,7 @@
|
||||
|
||||
/* ADC interrupts ***********************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F30XX
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
# define STM32_ADC_DMAREG_OFFSET STM32_ADC_CFGR_OFFSET
|
||||
# define ADC_DMAREG_DMA ADC_CFGR_DMAEN
|
||||
# define STM32_ADC_EXTREG_OFFSET STM32_ADC_CFGR_OFFSET
|
||||
@ -226,7 +240,7 @@
|
||||
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP7_SHIFT) | \
|
||||
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP8_SHIFT) | \
|
||||
(ADC_SMPR_DEFAULT << ADC_SMPR2_SMP9_SHIFT))
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
# if defined(ADC_HAVE_DMA) || (ADC_MAX_SAMPLES == 1)
|
||||
# define ADC_SMPR_DEFAULT ADC_SMPR_61p5
|
||||
# else /* Slow down sampling frequency */
|
||||
@ -338,8 +352,8 @@ struct stm32_dev_s
|
||||
/* ADC Register access */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
|
||||
uint32_t setbits);
|
||||
#endif
|
||||
@ -606,8 +620,8 @@ static struct adc_dev_s g_adcdev4 =
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) ||defined(CONFIG_STM32_STM32F40XX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
static void stm32_modifyreg32(unsigned int addr, uint32_t clrbits,
|
||||
uint32_t setbits)
|
||||
{
|
||||
@ -1242,7 +1256,7 @@ static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
|
||||
|
||||
adc_enable(priv, true);
|
||||
}
|
||||
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||
#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable)
|
||||
{
|
||||
uint32_t regval;
|
||||
@ -1520,7 +1534,7 @@ static void adc_select_ch_bank(FAR struct stm32_dev_s *priv,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F30XX
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
static void adc_enable(FAR struct stm32_dev_s *priv, bool enable)
|
||||
{
|
||||
uint32_t regval;
|
||||
@ -1699,8 +1713,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, FAR void *arg)
|
||||
* Name: adc_bind
|
||||
*
|
||||
* Description:
|
||||
* Bind the upper-half driver callbacks to the lower-half implementation. This
|
||||
* must be called early in order to receive ADC event notifications.
|
||||
* Bind the upper-half driver callbacks to the lower-half implementation.
|
||||
* This must be called early in order to receive ADC event notifications.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
@ -1718,8 +1732,8 @@ static int adc_bind(FAR struct adc_dev_s *dev,
|
||||
* Name: adc_reset
|
||||
*
|
||||
* Description:
|
||||
* Reset the ADC device. Called early to initialize the hardware. This
|
||||
* is called, before adc_setup() and on error conditions.
|
||||
* Reset the ADC device. Called early to initialize the hardware.
|
||||
* This is called, before adc_setup() and on error conditions.
|
||||
*
|
||||
* Input Parameters:
|
||||
*
|
||||
@ -1751,7 +1765,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F30XX
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
|
||||
/* Turn off the ADC so we can write the RCC bits */
|
||||
|
||||
@ -1767,7 +1781,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
|
||||
adc_rccreset(priv, false);
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F30XX
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
|
||||
/* Set voltage regular enable to intermediate state */
|
||||
|
||||
@ -1822,7 +1836,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F30XX
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
|
||||
/* Enable the analog watchdog */
|
||||
|
||||
@ -1870,7 +1884,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
|
||||
adc_modifyreg(priv, STM32_ADC_IER_OFFSET, clrbits, setbits);
|
||||
|
||||
#else /* ifdef CONFIG_STM32_STM32F30XX */
|
||||
#else /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM33XX */
|
||||
|
||||
/* Enable the analog watchdog */
|
||||
|
||||
@ -1968,7 +1982,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
|
||||
/* ADC CCR configuration */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
clrbits = ADC_CCR_DUAL_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DMACFG |
|
||||
ADC_CCR_MDMA_MASK | ADC_CCR_CKMODE_MASK | ADC_CCR_VREFEN |
|
||||
ADC_CCR_TSEN | ADC_CCR_VBATEN;
|
||||
@ -1979,10 +1993,12 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
{
|
||||
stm32_modifyreg32(STM32_ADC12_CCR, clrbits, setbits);
|
||||
}
|
||||
#ifndef CONFIG_STM32_STM32F33XX
|
||||
else
|
||||
{
|
||||
stm32_modifyreg32(STM32_ADC34_CCR, clrbits, setbits);
|
||||
}
|
||||
#endif
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F40XX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
@ -2050,7 +2066,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F30XX
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
ainfo("ISR: 0x%08x CR: 0x%08x CFGR: 0x%08x\n",
|
||||
adc_getreg(priv, STM32_ADC_ISR_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_CR_OFFSET),
|
||||
@ -2067,7 +2083,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
|
||||
adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET));
|
||||
#elif defined(CONFIG_STM32_STM32L15XX)
|
||||
ainfo("SQR4: 0x%08x SQR5: 0x%08x\n",
|
||||
@ -2075,15 +2091,17 @@ static void adc_reset(FAR struct adc_dev_s *dev)
|
||||
adc_getreg(priv, STM32_ADC_SQR5_OFFSET));
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F30XX)
|
||||
#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
|
||||
if (priv->base == STM32_ADC1_BASE || priv->base == STM32_ADC2_BASE)
|
||||
{
|
||||
ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC12_CCR));
|
||||
}
|
||||
#ifndef CONFIG_STM32_STM32F33XX
|
||||
else
|
||||
{
|
||||
ainfo("CCR: 0x%08x\n", getreg32(STM32_ADC34_CCR));
|
||||
}
|
||||
#endif
|
||||
#elif defined(CONFIG_STM32_STM32F20XX) || \
|
||||
defined(CONFIG_STM32_STM32F40XX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
@ -3085,8 +3103,9 @@ struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX ||
|
||||
* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F47XX ||
|
||||
* CONFIG_STM32_STM32F40XX || CONFIG_STM32_STM32L15XX
|
||||
* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX ||
|
||||
* CONFIG_STM32_STM32F47XX || CONFIG_STM32_STM32F40XX ||
|
||||
* CONFIG_STM32_STM32L15XX
|
||||
*/
|
||||
#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 ||
|
||||
* CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4
|
||||
|
||||
@ -56,9 +56,10 @@
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "stm32f10xxx_dma.c"
|
||||
#elif defined(CONFIG_STM32_STM32F33XX)
|
||||
# include "stm32f33xxx_dma.c"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "stm32f20xxx_dma.c"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
|
||||
@ -48,9 +48,10 @@
|
||||
/* Include the correct DMA register definitions for this STM32 family */
|
||||
|
||||
#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX)
|
||||
defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
|
||||
# include "chip/stm32f10xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F33XX)
|
||||
# include "chip/stm32f33xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F20XX)
|
||||
# include "chip/stm32f20xxx_dma.h"
|
||||
#elif defined(CONFIG_STM32_STM32F40XX)
|
||||
|
||||
@ -57,7 +57,8 @@
|
||||
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
|
||||
defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32L15XX)
|
||||
defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX) || \
|
||||
defined(CONFIG_STM32_STM32L15XX)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
|
||||
696
arch/arm/src/stm32/stm32f33xxx_dma.c
Normal file
696
arch/arm/src/stm32/stm32f33xxx_dma.c
Normal file
@ -0,0 +1,696 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32f33xxx_dma.c
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <semaphore.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "sched/sched.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_dma.h"
|
||||
#include "stm32.h"
|
||||
|
||||
#if defined(CONFIG_STM32_DMA1) && defined(CONFIG_STM32_STM32F33XX)
|
||||
|
||||
#ifndef CONFIG_ARCH_DMA
|
||||
# warning "STM32 DMA enabled but CONFIG_ARCH_DMA disabled"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define DMA1_NCHANNELS 7
|
||||
#define DMA_NCHANNELS DMA1_NCHANNELS
|
||||
|
||||
#ifndef CONFIG_DMA_PRI
|
||||
# define CONFIG_DMA_PRI NVIC_SYSH_PRIORITY_DEFAULT
|
||||
#endif
|
||||
|
||||
/* Convert the DMA channel base address to the DMA register block address */
|
||||
|
||||
#define DMA_BASE(ch) (ch & 0xfffffc00)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/* This structure descibes one DMA channel */
|
||||
|
||||
struct stm32_dma_s
|
||||
{
|
||||
uint8_t chan; /* DMA channel number (0-6) */
|
||||
uint8_t irq; /* DMA channel IRQ number */
|
||||
sem_t sem; /* Used to wait for DMA channel to become available */
|
||||
uint32_t base; /* DMA register channel base address */
|
||||
dma_callback_t callback; /* Callback invoked when the DMA completes */
|
||||
void *arg; /* Argument passed to callback function */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This array describes the state of each DMA */
|
||||
|
||||
static struct stm32_dma_s g_dma[DMA_NCHANNELS] =
|
||||
{
|
||||
{
|
||||
.chan = 0,
|
||||
.irq = STM32_IRQ_DMA1CH1,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0),
|
||||
},
|
||||
{
|
||||
.chan = 1,
|
||||
.irq = STM32_IRQ_DMA1CH2,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1),
|
||||
},
|
||||
{
|
||||
.chan = 2,
|
||||
.irq = STM32_IRQ_DMA1CH3,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2),
|
||||
},
|
||||
{
|
||||
.chan = 3,
|
||||
.irq = STM32_IRQ_DMA1CH4,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3),
|
||||
},
|
||||
{
|
||||
.chan = 4,
|
||||
.irq = STM32_IRQ_DMA1CH5,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4),
|
||||
},
|
||||
{
|
||||
.chan = 5,
|
||||
.irq = STM32_IRQ_DMA1CH6,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5),
|
||||
},
|
||||
{
|
||||
.chan = 6,
|
||||
.irq = STM32_IRQ_DMA1CH7,
|
||||
.base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6),
|
||||
},
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* DMA register access functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Get non-channel register from DMA1 or DMA2 */
|
||||
|
||||
static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, uint32_t offset)
|
||||
{
|
||||
return getreg32(DMA_BASE(dmach->base) + offset);
|
||||
}
|
||||
|
||||
/* Write to non-channel register in DMA1 or DMA2 */
|
||||
|
||||
static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value)
|
||||
{
|
||||
putreg32(value, DMA_BASE(dmach->base) + offset);
|
||||
}
|
||||
|
||||
/* Get channel register from DMA1 or DMA2 */
|
||||
|
||||
static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, uint32_t offset)
|
||||
{
|
||||
return getreg32(dmach->base + offset);
|
||||
}
|
||||
|
||||
/* Write to channel register in DMA1 or DMA2 */
|
||||
|
||||
static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value)
|
||||
{
|
||||
putreg32(value, dmach->base + offset);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_dmatake() and stm32_dmagive()
|
||||
*
|
||||
* Description:
|
||||
* Used to get exclusive access to a DMA channel.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static void stm32_dmatake(FAR struct stm32_dma_s *dmach)
|
||||
{
|
||||
/* Take the semaphore (perhaps waiting) */
|
||||
|
||||
while (sem_wait(&dmach->sem) != 0)
|
||||
{
|
||||
/* The only case that an error should occur here is if the wait was awakened
|
||||
* by a signal.
|
||||
*/
|
||||
|
||||
ASSERT(errno == EINTR);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void stm32_dmagive(FAR struct stm32_dma_s *dmach)
|
||||
{
|
||||
(void)sem_post(&dmach->sem);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_dmachandisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the DMA channel
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static void stm32_dmachandisable(struct stm32_dma_s *dmach)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Disable all interrupts at the DMA controller */
|
||||
|
||||
regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
regval &= ~DMA_CCR_ALLINTS;
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
||||
regval &= ~DMA_CCR_EN;
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
|
||||
|
||||
/* Clear pending channel interrupts */
|
||||
|
||||
dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmach->chan));
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_dmainterrupt
|
||||
*
|
||||
* Description:
|
||||
* DMA interrupt handler
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static int stm32_dmainterrupt(int irq, void *context, FAR void *arg)
|
||||
{
|
||||
struct stm32_dma_s *dmach;
|
||||
uint32_t isr;
|
||||
int chndx = 0;
|
||||
|
||||
/* Get the channel structure from the interrupt number */
|
||||
|
||||
if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7)
|
||||
{
|
||||
chndx = irq - STM32_IRQ_DMA1CH1;
|
||||
}
|
||||
else
|
||||
{
|
||||
PANIC();
|
||||
}
|
||||
dmach = &g_dma[chndx];
|
||||
|
||||
/* Get the interrupt status (for this channel only) */
|
||||
|
||||
isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan);
|
||||
|
||||
/* Clear the interrupts we are handling */
|
||||
|
||||
dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr);
|
||||
|
||||
/* Invoke the callback */
|
||||
|
||||
if (dmach->callback)
|
||||
{
|
||||
dmach->callback(dmach, isr >> DMA_ISR_CHAN_SHIFT(dmach->chan), dmach->arg);
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmainitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the DMA subsystem
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void weak_function up_dmainitialize(void)
|
||||
{
|
||||
struct stm32_dma_s *dmach;
|
||||
int chndx;
|
||||
|
||||
/* Initialize each DMA channel */
|
||||
|
||||
for (chndx = 0; chndx < DMA_NCHANNELS; chndx++)
|
||||
{
|
||||
dmach = &g_dma[chndx];
|
||||
sem_init(&dmach->sem, 0, 1);
|
||||
|
||||
/* Attach DMA interrupt vectors */
|
||||
|
||||
(void)irq_attach(dmach->irq, stm32_dmainterrupt, NULL);
|
||||
|
||||
/* Disable the DMA channel */
|
||||
|
||||
stm32_dmachandisable(dmach);
|
||||
|
||||
/* Enable the IRQ at the NVIC (still disabled at the DMA controller) */
|
||||
|
||||
up_enable_irq(dmach->irq);
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* Set the interrupt priority */
|
||||
|
||||
up_prioritize_irq(dmach->irq, CONFIG_DMA_PRI);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmachannel
|
||||
*
|
||||
* Description:
|
||||
* Allocate a DMA channel. This function gives the caller mutually
|
||||
* exclusive access to the DMA channel specified by the 'chndx' argument.
|
||||
* DMA channels are shared on the STM32: Devices sharing the same DMA
|
||||
* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
|
||||
* stm32_dma.h.
|
||||
*
|
||||
* If the DMA channel is not available, then stm32_dmachannel() will wait
|
||||
* until the holder of the channel relinquishes the channel by calling
|
||||
* stm32_dmafree(). WARNING: If you have two devices sharing a DMA
|
||||
* channel and the code never releases the channel, the stm32_dmachannel
|
||||
* call for the other will hang forever in this function! Don't let your
|
||||
* design do that!
|
||||
*
|
||||
* Hmm.. I suppose this interface could be extended to make a non-blocking
|
||||
* version. Feel free to do that if that is what you need.
|
||||
*
|
||||
* Input parameter:
|
||||
* chndx - Identifies the stream/channel resource. For the STM32 F1, this
|
||||
* is simply the channel number as provided by the DMACHAN_* definitions
|
||||
* in chip/stm32f10xxx_dma.h.
|
||||
*
|
||||
* Returned Value:
|
||||
* Provided that 'chndx' is valid, this function ALWAYS returns a non-NULL,
|
||||
* void* DMA channel handle. (If 'chndx' is invalid, the function will
|
||||
* assert if debug is enabled or do something ignorant otherwise).
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller does not hold he DMA channel.
|
||||
* - The caller can wait for the DMA channel to be freed if it is no
|
||||
* available.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
DMA_HANDLE stm32_dmachannel(unsigned int chndx)
|
||||
{
|
||||
struct stm32_dma_s *dmach = &g_dma[chndx];
|
||||
|
||||
DEBUGASSERT(chndx < DMA_NCHANNELS);
|
||||
|
||||
/* Get exclusive access to the DMA channel -- OR wait until the channel
|
||||
* is available if it is currently being used by another driver
|
||||
*/
|
||||
|
||||
stm32_dmatake(dmach);
|
||||
|
||||
/* The caller now has exclusive use of the DMA channel */
|
||||
|
||||
return (DMA_HANDLE)dmach;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmafree
|
||||
*
|
||||
* Description:
|
||||
* Release a DMA channel. If another thread is waiting for this DMA channel
|
||||
* in a call to stm32_dmachannel, then this function will re-assign the
|
||||
* DMA channel to that thread and wake it up. NOTE: The 'handle' used
|
||||
* in this argument must NEVER be used again until stm32_dmachannel() is
|
||||
* called again to re-gain access to the channel.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* - The caller holds the DMA channel.
|
||||
* - There is no DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmafree(DMA_HANDLE handle)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
/* Release the channel */
|
||||
|
||||
stm32_dmagive(dmach);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasetup
|
||||
*
|
||||
* Description:
|
||||
* Configure DMA before using
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
size_t ntransfers, uint32_t ccr)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
uint32_t regval;
|
||||
|
||||
/* Then DMA_CNDTRx register can only be modified if the DMA channel is
|
||||
* disabled.
|
||||
*/
|
||||
|
||||
regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
regval &= ~(DMA_CCR_EN);
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
|
||||
|
||||
/* Set the peripheral register address in the DMA_CPARx register. The data
|
||||
* will be moved from/to this address to/from the memory after the
|
||||
* peripheral event.
|
||||
*/
|
||||
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr);
|
||||
|
||||
/* Set the memory address in the DMA_CMARx register. The data will be
|
||||
* written to or read from this memory after the peripheral event.
|
||||
*/
|
||||
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr);
|
||||
|
||||
/* Configure the total number of data to be transferred in the DMA_CNDTRx
|
||||
* register. After each peripheral event, this value will be decremented.
|
||||
*/
|
||||
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers);
|
||||
|
||||
/* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx
|
||||
* register. Configure data transfer direction, circular mode, peripheral & memory
|
||||
* incremented mode, peripheral & memory data size, and interrupt after
|
||||
* half and/or full transfer in the DMA_CCRx register.
|
||||
*/
|
||||
|
||||
regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
|
||||
DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
|
||||
DMA_CCR_DIR);
|
||||
ccr &= (DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK |
|
||||
DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
|
||||
DMA_CCR_DIR);
|
||||
regval |= ccr;
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Start the DMA transfer
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
* - No DMA in progress
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback,
|
||||
void *arg, bool half)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
uint32_t ccr;
|
||||
|
||||
DEBUGASSERT(handle != NULL);
|
||||
|
||||
/* Save the callback info. This will be invoked whent the DMA commpletes */
|
||||
|
||||
dmach->callback = callback;
|
||||
dmach->arg = arg;
|
||||
|
||||
/* Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
|
||||
* As soon as the channel is enabled, it can serve any DMA request from the
|
||||
* peripheral connected on the channel.
|
||||
*/
|
||||
|
||||
ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
ccr |= DMA_CCR_EN;
|
||||
|
||||
/* In normal mode, interrupt at either half or full completion. In circular mode,
|
||||
* always interrupt on buffer wrap, and optionally interrupt at the halfway point.
|
||||
*/
|
||||
|
||||
if ((ccr & DMA_CCR_CIRC) == 0)
|
||||
{
|
||||
/* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
|
||||
* set and an interrupt is generated if the Half-Transfer Interrupt Enable
|
||||
* bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
|
||||
* (TCIF) is set and an interrupt is generated if the Transfer Complete
|
||||
* Interrupt Enable bit (TCIE) is set.
|
||||
*/
|
||||
|
||||
ccr |= (half ? (DMA_CCR_HTIE | DMA_CCR_TEIE) : (DMA_CCR_TCIE | DMA_CCR_TEIE));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In nonstop mode, when the transfer completes it immediately resets
|
||||
* and starts again. The transfer-complete interrupt is thus always
|
||||
* enabled, and the half-complete interrupt can be used in circular
|
||||
* mode to determine when the buffer is half-full, or in double-buffered
|
||||
* mode to determine when one of the two buffers is full.
|
||||
*/
|
||||
|
||||
ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE;
|
||||
}
|
||||
|
||||
dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmastop
|
||||
*
|
||||
* Description:
|
||||
* Cancel the DMA. After stm32_dmastop() is called, the DMA channel is
|
||||
* reset and stm32_dmasetup() must be called before stm32_dmastart() can be
|
||||
* called again
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_dmastop(DMA_HANDLE handle)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
stm32_dmachandisable(dmach);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmaresidual
|
||||
*
|
||||
* Description:
|
||||
* Returns the number of bytes remaining to be transferred
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t stm32_dmaresidual(DMA_HANDLE handle)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
|
||||
return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmacapable
|
||||
*
|
||||
* Description:
|
||||
* Check if the DMA controller can transfer data to/from given memory
|
||||
* address. This depends on the internal connections in the ARM bus matrix
|
||||
* of the processor. Note that this only applies to memory addresses, it
|
||||
* will return false for any peripheral address.
|
||||
*
|
||||
* Returned value:
|
||||
* True, if transfer is possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_DMACAPABLE
|
||||
bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr)
|
||||
{
|
||||
uint32_t transfer_size;
|
||||
uint32_t mend;
|
||||
|
||||
/* Verify that the address conforms to the memory transfer size.
|
||||
* Transfers to/from memory performed by the DMA controller are
|
||||
* required to be aligned to their size.
|
||||
*
|
||||
* See ST RM0090 rev4, section 9.3.11
|
||||
*
|
||||
* Compute mend inline to avoid a possible non-constant integer
|
||||
* multiply.
|
||||
*/
|
||||
|
||||
switch (ccr & DMA_CCR_MSIZE_MASK)
|
||||
{
|
||||
case DMA_CCR_MSIZE_8BITS:
|
||||
transfer_size = 1;
|
||||
mend = maddr + count - 1;
|
||||
break;
|
||||
|
||||
case DMA_CCR_MSIZE_16BITS:
|
||||
transfer_size = 2;
|
||||
mend = maddr + (count << 1) - 1;
|
||||
break;
|
||||
|
||||
case DMA_CCR_MSIZE_32BITS:
|
||||
transfer_size = 4;
|
||||
mend = maddr + (count << 2) - 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
|
||||
if ((maddr & (transfer_size - 1)) != 0)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Verify that the transfer is to a memory region that supports DMA. */
|
||||
|
||||
if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
switch (maddr & STM32_REGION_MASK)
|
||||
{
|
||||
case STM32_SRAM_BASE:
|
||||
case STM32_CODE_BASE:
|
||||
/* All RAM and flash is supported */
|
||||
|
||||
return true;
|
||||
|
||||
default:
|
||||
/* Everything else is unsupported by DMA */
|
||||
|
||||
return false;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasample
|
||||
*
|
||||
* Description:
|
||||
* Sample DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA_INFO
|
||||
void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
irqstate_t flags;
|
||||
|
||||
flags = enter_critical_section();
|
||||
regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET);
|
||||
regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET);
|
||||
regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET);
|
||||
regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET);
|
||||
regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmadump
|
||||
*
|
||||
* Description:
|
||||
* Dump previously sampled DMA register contents
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_DMA_INFO
|
||||
void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
|
||||
const char *msg)
|
||||
{
|
||||
struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle;
|
||||
uint32_t dmabase = DMA_BASE(dmach->base);
|
||||
|
||||
dmainfo("DMA Registers: %s\n", msg);
|
||||
dmainfo(" ISRC[%08x]: %08x\n", dmabase + STM32_DMA_ISR_OFFSET, regs->isr);
|
||||
dmainfo(" CCR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr);
|
||||
dmainfo(" CNDTR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr);
|
||||
dmainfo(" CPAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar);
|
||||
dmainfo(" CMAR[%08x]: %08x\n", dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32_DMA1 && CONFIG_STM32_STM32F33XX */
|
||||
113
configs/nucleo-f334r8/adc/Make.defs
Normal file
113
configs/nucleo-f334r8/adc/Make.defs
Normal file
@ -0,0 +1,113 @@
|
||||
############################################################################
|
||||
# configs/nucleo-f334r8/adc/Make.defs
|
||||
#
|
||||
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include ${TOPDIR}/.config
|
||||
include ${TOPDIR}/tools/Config.mk
|
||||
include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
|
||||
|
||||
LDSCRIPT = ld.script
|
||||
|
||||
ifeq ($(WINTOOL),y)
|
||||
# Windows-native toolchains
|
||||
DIRLINK = $(TOPDIR)/tools/copydir.sh
|
||||
DIRUNLINK = $(TOPDIR)/tools/unlink.sh
|
||||
MKDEP = $(TOPDIR)/tools/mkwindeps.sh
|
||||
ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
|
||||
ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
|
||||
ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
|
||||
else
|
||||
# Linux/Cygwin-native toolchain
|
||||
MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
|
||||
ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
|
||||
ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
|
||||
ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
|
||||
endif
|
||||
|
||||
CC = $(CROSSDEV)gcc
|
||||
CXX = $(CROSSDEV)g++
|
||||
CPP = $(CROSSDEV)gcc -E
|
||||
LD = $(CROSSDEV)ld
|
||||
AR = $(ARCROSSDEV)ar rcs
|
||||
NM = $(ARCROSSDEV)nm
|
||||
OBJCOPY = $(CROSSDEV)objcopy
|
||||
OBJDUMP = $(CROSSDEV)objdump
|
||||
|
||||
ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
|
||||
ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
ARCHOPTIMIZATION = -g
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_DEBUG_NOOPT),y)
|
||||
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
|
||||
endif
|
||||
|
||||
ARCHCFLAGS = -fno-builtin
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
|
||||
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
|
||||
ARCHDEFINES =
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
|
||||
AFLAGS = $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
|
||||
ASMEXT = .S
|
||||
OBJEXT = .o
|
||||
LIBEXT = .a
|
||||
EXEEXT =
|
||||
|
||||
ifneq ($(CROSSDEV),arm-nuttx-elf-)
|
||||
LDFLAGS += -nostartfiles -nodefaultlibs
|
||||
endif
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
LDFLAGS += -g
|
||||
endif
|
||||
|
||||
|
||||
HOSTCC = gcc
|
||||
HOSTINCLUDES = -I.
|
||||
HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
|
||||
HOSTLDFLAGS =
|
||||
|
||||
1239
configs/nucleo-f334r8/adc/defconfig
Normal file
1239
configs/nucleo-f334r8/adc/defconfig
Normal file
File diff suppressed because it is too large
Load Diff
77
configs/nucleo-f334r8/adc/setenv.sh
Normal file
77
configs/nucleo-f334r8/adc/setenv.sh
Normal file
@ -0,0 +1,77 @@
|
||||
#!/bin/bash
|
||||
# configs/nucleo-f224r8/adc/setenv.sh
|
||||
#
|
||||
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
|
||||
if [ "$_" = "$0" ] ; then
|
||||
echo "You must source this script, not run it!" 1>&2
|
||||
exit 1
|
||||
fi
|
||||
|
||||
WD=`pwd`
|
||||
if [ ! -x "setenv.sh" ]; then
|
||||
echo "This script must be executed from the top-level NuttX build directory"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
if [ -z "${PATH_ORIG}" ]; then
|
||||
export PATH_ORIG="${PATH}"
|
||||
fi
|
||||
|
||||
# This is the Cygwin path to the location where I installed the Atmel GCC
|
||||
# toolchain under Windows. You will also have to edit this if you install
|
||||
# this toolchain in any other location
|
||||
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Atmel/Atmel Toolchain/ARM GCC/Native/4.7.3.99/arm-gnu-toolchain/bin"
|
||||
|
||||
# This is the Cygwin path to the location where I installed the CodeSourcery
|
||||
# toolchain under windows. You will also have to edit this if you install
|
||||
# the CodeSourcery toolchain in any other location
|
||||
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin"
|
||||
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
|
||||
# export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
|
||||
|
||||
# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors"
|
||||
# You can this free toolchain here https://launchpad.net/gcc-arm-embedded
|
||||
export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin"
|
||||
|
||||
# This is the path to the location where I installed the devkitARM toolchain
|
||||
# You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/
|
||||
#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/devkitARM/bin"
|
||||
|
||||
# This is the Cygwin path to the location where I build the buildroot
|
||||
# toolchain.
|
||||
# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin"
|
||||
|
||||
# Add the path to the toolchain to the PATH varialble
|
||||
export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}"
|
||||
|
||||
echo "PATH : ${PATH}"
|
||||
@ -243,8 +243,8 @@
|
||||
/* DMA channels *************************************************************/
|
||||
/* ADC */
|
||||
|
||||
#define ADC1_DMA_CHAN DMACHAN_ADC1
|
||||
#define ADC2_DMA_CHAN DMACHAN_ADC2_
|
||||
#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */
|
||||
#define ADC2_DMA_CHAN DMACHAN_ADC2_1 /* DMA1_CH2 */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
|
||||
@ -0,0 +1,253 @@
|
||||
/****************************************************************************
|
||||
* configs/nucleo-f334r8/src/stm32_adc.c
|
||||
*
|
||||
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
|
||||
#include "stm32.h"
|
||||
|
||||
#if defined(CONFIG_ADC) && (defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2))
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* 1 or 2 ADC devices (DEV1, DEV2) */
|
||||
|
||||
#if defined(CONFIG_STM32_ADC1)
|
||||
# define DEV1_PORT 1
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_ADC2)
|
||||
# if defined(DEV1_PORT)
|
||||
# define DEV2_PORT 2
|
||||
# else
|
||||
# define DEV1_PORT 2
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* The number of ADC channels in the conversion list */
|
||||
/* TODO DMA */
|
||||
|
||||
#define ADC1_NCHANNELS 3
|
||||
#define ADC2_NCHANNELS 3
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* DEV 1 */
|
||||
|
||||
#if DEV1_PORT == 1
|
||||
|
||||
#define DEV1_NCHANNELS ADC1_NCHANNELS
|
||||
|
||||
/* Identifying number of each ADC channel (even if NCHANNELS is less ) */
|
||||
|
||||
static const uint8_t g_chanlist1[3] =
|
||||
{
|
||||
1,
|
||||
2,
|
||||
11
|
||||
};
|
||||
|
||||
/* Configurations of pins used by each ADC channel */
|
||||
|
||||
static const uint32_t g_pinlist1[3] =
|
||||
{
|
||||
GPIO_ADC1_IN1, /* PA0/A0 */
|
||||
GPIO_ADC1_IN2, /* PA1/A1 */
|
||||
GPIO_ADC1_IN11, /* PB0/A3 */
|
||||
};
|
||||
|
||||
#elif DEV1_PORT == 2
|
||||
|
||||
#define DEV1_NCHANNELS ADC2_NCHANNELS
|
||||
|
||||
/* Identifying number of each ADC channel */
|
||||
|
||||
static const uint8_t g_chanlist1[3] =
|
||||
{
|
||||
1,
|
||||
6,
|
||||
7
|
||||
};
|
||||
|
||||
/* Configurations of pins used by each ADC channel */
|
||||
|
||||
static const uint32_t g_pinlist1[3] =
|
||||
{
|
||||
GPIO_ADC2_IN1, /* PA4/A2 */
|
||||
GPIO_ADC2_IN7, /* PC1/A4 */
|
||||
GPIO_ADC2_IN6, /* PC0/A5 */
|
||||
};
|
||||
|
||||
#endif /* DEV1_PORT == 1 */
|
||||
|
||||
#ifdef DEV2_PORT
|
||||
|
||||
/* DEV 2 */
|
||||
|
||||
#if DEV2_PORT == 2
|
||||
|
||||
#define DEV2_NCHANNELS ADC2_NCHANNELS
|
||||
|
||||
/* Identifying number of each ADC channel */
|
||||
|
||||
static const uint8_t g_chanlist2[1] =
|
||||
{
|
||||
1,
|
||||
6,
|
||||
7
|
||||
};
|
||||
|
||||
/* Configurations of pins used by each ADC channel */
|
||||
|
||||
static const uint32_t g_pinlist2[3] =
|
||||
{
|
||||
GPIO_ADC2_IN1, /* PA4/A2 */
|
||||
GPIO_ADC2_IN7, /* PC1/A4 */
|
||||
GPIO_ADC2_IN6, /* PC0/A5 */
|
||||
};
|
||||
|
||||
#endif /* DEV2_PORT == 2 */
|
||||
#endif /* DEV2_PORT */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_adc_setup
|
||||
*
|
||||
* Description:
|
||||
* Initialize ADC and register the ADC driver.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int stm32_adc_setup(void)
|
||||
{
|
||||
static bool initialized = false;
|
||||
FAR struct adc_dev_s *adc;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
/* Check if we have already initialized */
|
||||
|
||||
if (!initialized)
|
||||
{
|
||||
/* DEV1 */
|
||||
/* Configure the pins as analog inputs for the selected channels */
|
||||
|
||||
for (i = 0; i < DEV1_NCHANNELS; i++)
|
||||
{
|
||||
stm32_configgpio(g_pinlist1[i]);
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32_adcinitialize(DEV1_PORT, g_chanlist1, DEV1_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC interface 1\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc0" */
|
||||
|
||||
ret = adc_register("/dev/adc0", adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: adc_register /dev/adc0 failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef DEV2_PORT
|
||||
|
||||
/* DEV2 */
|
||||
/* Configure the pins as analog inputs for the selected channels */
|
||||
|
||||
for (i = 0; i < DEV2_NCHANNELS; i++)
|
||||
{
|
||||
stm32_configgpio(g_pinlist2[i]);
|
||||
}
|
||||
|
||||
/* Call stm32_adcinitialize() to get an instance of the ADC interface */
|
||||
|
||||
adc = stm32_adcinitialize(DEV2_PORT, g_chanlist2, DEV2_NCHANNELS);
|
||||
if (adc == NULL)
|
||||
{
|
||||
aerr("ERROR: Failed to get ADC interface 2\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Register the ADC driver at "/dev/adc1" */
|
||||
|
||||
ret = adc_register("/dev/adc1", adc);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: adc_register /dev/adc1 failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
initialized = true;
|
||||
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ADC && (CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2) */
|
||||
@ -45,7 +45,7 @@
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/leds/userled.h>
|
||||
|
||||
#include "nucleo-f303re.h"
|
||||
#include "nucleo-f334r8.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -107,6 +107,26 @@ int board_app_initialize(uintptr_t arg)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ADC
|
||||
/* Initialize ADC and register the ADC driver. */
|
||||
|
||||
ret = stm32_adc_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DAC
|
||||
/* Initialize DAC and register the DAC driver. */
|
||||
|
||||
ret = stm32_dac_setup();
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -78,9 +78,10 @@
|
||||
void stm32_boardinitialize(void)
|
||||
{
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
/* Configure on-board LEDs if LED support has been selected. */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user