From 591147877711d55f166e4c027b7b2283a051ce7a Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 27 Jan 2019 16:17:39 +0000 Subject: [PATCH] Merged in raiden00/nuttx_pe (pull request #823) Improvements in STM32 ADC, PWM and TIM arch/arm/src/stm32/chip/stm32_adc_v2.h: missing T1TRGO2 for JEXTSEL arch/arm/src/stm32/stm32_adc: configure injected channels external trigger when ADC enabled arch/arm/src/stm32/stm32_adc: update injected conversion queue of context after configuration arch/arm/src/stm32/stm32_adc: fix sample time configuration for channels. The array index for channels was missing arch/arm/src/stm32/stm32_adc: support for offset configuration arch/arm/src/stm32/stm32_pwm: fix TRGO/TRGO2 configuration arch/arm/src/stm32/stm32_pwm: support for advanced timers channel 5 and 6 Approved-by: GregoryN --- arch/arm/src/stm32/Kconfig | 166 ++++++++++++++++++++++++- arch/arm/src/stm32/chip/stm32_adc_v2.h | 1 + arch/arm/src/stm32/stm32_adc.c | 109 +++++++++++++--- arch/arm/src/stm32/stm32_adc.h | 7 ++ arch/arm/src/stm32/stm32_pwm.c | 163 +++++++++++++++++++++++- arch/arm/src/stm32/stm32_tim.c | 34 ++--- 6 files changed, 438 insertions(+), 42 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 7d4ab90376..f52b820804 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -3403,6 +3403,54 @@ config STM32_TIM1_CH4OUT endif # STM32_TIM1_CHANNEL4 +config STM32_TIM1_CHANNEL5 + bool "TIM1 Channel 5 (internal)" + default n + depends on STM32_HAVE_IP_TIMERS_V2 + ---help--- + Enables channel 5 (no available externaly) + +if STM32_TIM1_CHANNEL5 + +config STM32_TIM1_CH5MODE + int "TIM1 Channel 5 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH5OUT + bool "TIM1 Channel 5 Output" + default n + ---help--- + Enables channel 5 output. + +endif # STM32_TIM1_CHANNEL5 + +config STM32_TIM1_CHANNEL6 + bool "TIM1 Channel 6 (internal)" + default n + depends on STM32_HAVE_IP_TIMERS_V2 + ---help--- + Enables channel 6 (no available externaly) + +if STM32_TIM1_CHANNEL6 + +config STM32_TIM1_CH6MODE + int "TIM1 Channel 6 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32_TIM1_CH6OUT + bool "TIM1 Channel 6 Output" + default n + ---help--- + Enables channel 6 output. + +endif # STM32_TIM1_CHANNEL6 + endif # STM32_PWM_MULTICHAN if !STM32_PWM_MULTICHAN @@ -4379,6 +4427,54 @@ config STM32_TIM8_CH4OUT endif # STM32_TIM8_CHANNEL4 +config STM32_TIM8_CHANNEL5 + bool "TIM8 Channel 5 (internal)" + default n + depends on STM32_HAVE_IP_TIMERS_V2 + ---help--- + Enables channel 5 (no available externaly) + +if STM32_TIM8_CHANNEL5 + +config STM32_TIM8_CH5MODE + int "TIM8 Channel 5 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH5OUT + bool "TIM8 Channel 5 Output" + default n + ---help--- + Enables channel 5 output. + +endif # STM32_TIM8_CHANNEL5 + +config STM32_TIM8_CHANNEL6 + bool "TIM8 Channel 6 (internal)" + default n + depends on STM32_HAVE_IP_TIMERS_V2 + ---help--- + Enables channel 6 (no available externaly) + +if STM32_TIM8_CHANNEL6 + +config STM32_TIM8_CH6MODE + int "TIM8 Channel 6 Mode" + default 0 + range 0 5 + ---help--- + Specifies the channel mode. + +config STM32_TIM8_CH6OUT + bool "TIM8 Channel 6 Output" + default n + ---help--- + Enables channel 6 output. + +endif # STM32_TIM8_CHANNEL6 + endif # STM32_PWM_MULTICHAN if !STM32_PWM_MULTICHAN @@ -5330,10 +5426,10 @@ config STM32_PWM_MULTICHAN Specifies that the PWM driver supports multiple output channels per timer. -config STM32_TIM_PWM_TRGO - bool "TIM PWM TRGO" +config STM32_PWM_TRGO + bool "TIM PWM TRGO support" default n - depends on STM32_TIM1 + depends on STM32_PWM ---help--- Enable TRGO support for PWM driver @@ -6343,6 +6439,38 @@ config STM32_TIM1_CH4IDLE ---help--- TIM1 Channel 4 output IDLE +config STM32_TIM1_CH5POL + int "TIM1 Channel 5 Output polarity" + default 0 + range 0 1 + depends on STM32_TIM1_CH5OUT + ---help--- + TIM1 Channel 5 output polarity + +config STM32_TIM1_CH5IDLE + int "TIM1 Channel 5 Output IDLE" + default 0 + range 0 1 + depends on STM32_TIM1_CH5OUT + ---help--- + TIM1 Channel 5 output IDLE + +config STM32_TIM1_CH6POL + int "TIM1 Channel 6 Output polarity" + default 0 + range 0 1 + depends on STM32_TIM1_CH6OUT + ---help--- + TIM1 Channel 6 output polarity + +config STM32_TIM1_CH6IDLE + int "TIM1 Channel 6 Output IDLE" + default 0 + range 0 1 + depends on STM32_TIM1_CH6OUT + ---help--- + TIM1 Channel 6 output IDLE + config STM32_TIM2_CH1POL int "TIM2 Channel 1 Output polarity" default 0 @@ -6711,6 +6839,38 @@ config STM32_TIM8_CH4IDLE ---help--- TIM8 Channel 4 output IDLE +config STM32_TIM8_CH5POL + int "TIM8 Channel 5 Output polarity" + default 0 + range 0 1 + depends on STM32_TIM8_CH5OUT + ---help--- + TIM8 Channel 5 output polarity + +config STM32_TIM8_CH5IDLE + int "TIM8 Channel 5 Output IDLE" + default 0 + range 0 1 + depends on STM32_TIM8_CH5OUT + ---help--- + TIM8 Channel 5 output IDLE + +config STM32_TIM8_CH6POL + int "TIM8 Channel 6 Output polarity" + default 0 + range 0 1 + depends on STM32_TIM8_CH6OUT + ---help--- + TIM8 Channel 6 output polarity + +config STM32_TIM8_CH6IDLE + int "TIM8 Channel 6 Output IDLE" + default 0 + range 0 1 + depends on STM32_TIM8_CH6OUT + ---help--- + TIM8 Channel 6 output IDLE + config STM32_TIM9_CH1POL int "TIM9 Channel 1 Output polarity" default 0 diff --git a/arch/arm/src/stm32/chip/stm32_adc_v2.h b/arch/arm/src/stm32/chip/stm32_adc_v2.h index 72dc056d76..2fd75a2c78 100644 --- a/arch/arm/src/stm32/chip/stm32_adc_v2.h +++ b/arch/arm/src/stm32/chip/stm32_adc_v2.h @@ -574,6 +574,7 @@ # define ADC12_JSQR_JEXTSEL_T4TRGO (5 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T20TRGO (6 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T8CC4 (7 << ADC_JSQR_JEXTSEL_SHIFT) +# define ADC12_JSQR_JEXTSEL_T1TRGO2 (8 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T8TRGO (9 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T3CC3 (11 << ADC_JSQR_JEXTSEL_SHIFT) # define ADC12_JSQR_JEXTSEL_T3TRGO (12 << ADC_JSQR_JEXTSEL_SHIFT) diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index 37acc70899..a9565a76a0 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -687,6 +687,8 @@ static void adc_intdis(FAR struct stm32_adc_dev_s *dev, uint32_t source); static uint32_t adc_intget(FAR struct stm32_adc_dev_s *dev); static uint32_t adc_regget(FAR struct stm32_adc_dev_s *dev); static void adc_llops_reg_startconv(FAR struct stm32_adc_dev_s *dev, bool enable); +static int adc_offset_set(FAR struct stm32_adc_dev_s *dev, uint8_t ch, uint8_t i, + uint16_t offset); # ifdef ADC_HAVE_DMA static int adc_regbufregister(FAR struct stm32_adc_dev_s *dev, uint16_t *buffer, uint8_t len); @@ -734,6 +736,7 @@ static const struct stm32_adc_ops_s g_adc_llops = .int_dis = adc_intdis, .val_get = adc_regget, .reg_startconv = adc_llops_reg_startconv, + .offset_set = adc_offset_set, # ifdef ADC_HAVE_DMA .regbuf_reg = adc_regbufregister, # endif @@ -2783,16 +2786,26 @@ static void adc_configure(FAR struct adc_dev_s *dev) adc_extcfg_set(dev, priv->extcfg); #endif -#ifdef ADC_HAVE_JEXTCFG - /* Configure external event for injected group */ - - adc_jextcfg_set(dev, priv->jextcfg); -#endif - /* Enable ADC */ adc_enable(priv, true); +#ifdef ADC_HAVE_JEXTCFG + /* Configure external event for injected group when ADC enabled */ + + adc_jextcfg_set(dev, priv->jextcfg); + +#if defined(HAVE_IP_ADC_V2) + /* For ADC IPv2 there is queue of context for injected conversion. + * JEXTCFG configuration is the second write to JSQR register which means + * configuration is stored on queue. + * We trigger single INJ conversion here to update context. + */ + + adc_inj_startconv(priv, true); +#endif +#endif + /* Dump regs */ adc_dumpregs(priv); @@ -3267,8 +3280,9 @@ static void adc_dumpregs(FAR struct stm32_dev_s *priv) UNUSED(priv); #if defined(HAVE_IP_ADC_V2) - ainfo("ISR: 0x%08x CR: 0x%08x CFGR1: 0x%08x\n", + ainfo("ISR: 0x%08x IER: 0x%08x CR: 0x%08x CFGR1: 0x%08x\n", adc_getreg(priv, STM32_ADC_ISR_OFFSET), + adc_getreg(priv, STM32_ADC_IER_OFFSET), adc_getreg(priv, STM32_ADC_CR_OFFSET), adc_getreg(priv, STM32_ADC_CFGR1_OFFSET)); #else @@ -3278,17 +3292,19 @@ static void adc_dumpregs(FAR struct stm32_dev_s *priv) adc_getreg(priv, STM32_ADC_CR2_OFFSET)); #endif - ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x\n", + ainfo("SQR1: 0x%08x SQR2: 0x%08x SQR3: 0x%08x SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR1_OFFSET), adc_getreg(priv, STM32_ADC_SQR2_OFFSET), - adc_getreg(priv, STM32_ADC_SQR3_OFFSET)); + adc_getreg(priv, STM32_ADC_SQR3_OFFSET), + adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); + + ainfo("SMPR1: 0x%08x SMPR2: 0x%08x\n", + adc_getreg(priv, STM32_ADC_SMPR1_OFFSET), + adc_getreg(priv, STM32_ADC_SMPR2_OFFSET)); #if defined(STM32_ADC_SQR5_OFFSET) - ainfo("SQR4: 0x%08x SQR5: 0x%08x\n", - adc_getreg(priv, STM32_ADC_SQR4_OFFSET) - adc_getreg(priv, STM32_ADC_SQR5_OFFSET)); -#elif defined(STM32_ADC_SQR4_OFFSET) - ainfo("SQR4: 0x%08x\n", adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); + ainfo("SQR5: 0x%08x\n", + adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); #endif #ifdef ADC_HAVE_INJECTED @@ -3629,6 +3645,67 @@ static uint32_t adc_sqrbits(FAR struct stm32_dev_s *priv, int first, int last, return bits; } +/**************************************************************************** + * Name: adc_offset_set + ****************************************************************************/ + +#ifdef HAVE_IP_ADC_V2 +static int adc_offset_set(FAR struct stm32_adc_dev_s *dev, uint8_t ch, + uint8_t i, uint16_t offset) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev; + uint32_t regval = 0; + uint32_t reg = 0; + int ret = OK; + + if (i >= 4) + { + /* There are only four offset registers. */ + + ret = -E2BIG; + goto errout; + } + + reg = STM32_ADC_OFR1_OFFSET + i * 4; + + regval = ADC_OFR_OFFSETY_EN; + adc_putreg(priv, reg, regval); + + regval |= ADC_OFR_OFFSETY_CH(ch) | ADC_OFR_OFFSETY(offset); + adc_putreg(priv, reg, regval); + +errout: + return ret; +} +#else /* HAVE_IP_ADC_V1 */ +static int adc_offset_set(FAR struct stm32_adc_dev_s *dev, uint8_t ch, + uint8_t i, uint16_t offset) +{ + FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev; + uint32_t reg = 0; + int ret = OK; + + /* WARNING: Offset only for injected channels! */ + + UNUSED(ch); + + if (i >= 4) + { + /* There are only four offset registers. */ + + ret = -E2BIG; + goto errout; + } + + reg = STM32_ADC_JOFR1_OFFSET + i * 4; + + adc_putreg(priv, reg, offset); + +errout: + return ret; +} +#endif + /**************************************************************************** * Name: adc_set_ch * @@ -4381,13 +4458,13 @@ void adc_sampletime_set(FAR struct stm32_adc_dev_s *dev, { for (i = 0; i < time_samples->channels_nbr; i++) { - ch_index = time_samples->channel->channel; + ch_index = time_samples->channel[i].channel; if (ch_index >= ADC_CHANNELS_NUMBER) { break; } - priv->sample_rate[ch_index] = time_samples->channel->sample_time; + priv->sample_rate[ch_index] = time_samples->channel[i].sample_time; } } } diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/stm32/stm32_adc.h index 59c000f3f3..94e6690dc7 100644 --- a/arch/arm/src/stm32/stm32_adc.h +++ b/arch/arm/src/stm32/stm32_adc.h @@ -1921,6 +1921,8 @@ (adc)->llops->regbuf_reg(adc, buffer, len) #define ADC_REG_STARTCONV(adc, state) \ (adc)->llops->reg_startconv(adc, state) +#define ADC_OFFSET_SET(adc, ch, i, o) \ + (adc)->llops->offset_set(adc, ch, i, o) #define ADC_INJ_STARTCONV(adc, state) \ (adc)->llops->inj_startconv(adc, state) #define ADC_INJDATA_GET(adc, chan) \ @@ -2053,6 +2055,11 @@ struct stm32_adc_ops_s void (*reg_startconv)(FAR struct stm32_adc_dev_s *dev, bool state); + /* Set offset for channel */ + + int (*offset_set)(FAR struct stm32_adc_dev_s *dev, uint8_t ch, uint8_t i, + uint16_t offset); + #ifdef ADC_HAVE_INJECTED /* Get current ADC injected data register */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index fd5ac116cf..c8ab9a8e95 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -652,6 +652,36 @@ static struct stm32_pwmchan_s g_pwm1channels[] = .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } +#endif + }, +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL5 + { + .channel = 5, + .mode = CONFIG_STM32_TIM1_CH5MODE +#ifdef CONFIG_STM32_TIM1_CH5OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, + .pincfg = 0, /* No available externaly */ + } +#endif + } +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL6 + { + .channel = 6, + .mode = CONFIG_STM32_TIM1_CH6MODE +#ifdef CONFIG_STM32_TIM1_CH6OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, + .pincfg = 0, /* No available externaly */ + } #endif } #endif @@ -1185,6 +1215,36 @@ static struct stm32_pwmchan_s g_pwm8channels[] = #endif }, #endif +#ifdef CONFIG_STM32_TIM8_CHANNEL5 + { + .channel = 5, + .mode = CONFIG_STM32_TIM8_CH5MODE +#ifdef CONFIG_STM32_TIM8_CH5OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, + .pincfg = 0, /* No available externaly */ + } +#endif + } +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL6 + { + .channel = 6, + .mode = CONFIG_STM32_TIM8_CH6MODE +#ifdef CONFIG_STM32_TIM8_CH6OUT + .out1 = + { + .in_use = 1, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, + .pincfg = 0, /* No available externaly */ + } +#endif + } +#endif }; static struct stm32_pwmtimer_s g_pwm8dev = @@ -2016,6 +2076,16 @@ static void pwm_dumpregs(struct stm32_pwmtimer_s *priv, FAR const char *msg) pwminfo(" DCR: %04x DMAR: %04x\n", pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); + +#ifdef HAVE_IP_TIMERS_V2 + if (priv->timtype == TIMTYPE_ADVANCED) + { + pwminfo(" CCMR3: %04x CCR5: %04x CCR6: %04x\n", + pwm_getreg(priv, STM32_ATIM_CCMR3_OFFSET), + pwm_getreg(priv, STM32_ATIM_CCR5_OFFSET), + pwm_getreg(priv, STM32_ATIM_CCR6_OFFSET)); + } +#endif } #endif @@ -2468,9 +2538,22 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, uint32_t ccmr2 = 0; int ret = OK; #ifdef HAVE_IP_TIMERS_V2 + uint32_t ccmr3 = 0; + uint32_t ocmode3 = 0; bool ocmbit = false; #endif +#ifdef HAVE_IP_TIMERS_V2 + /* Only advanced timers have channels 5-6 */ + + if (channel > 4 && priv->timtype != TIMTYPE_ADVANCED) + { + pwmerr("ERROR: No such channel: %u\n", channel); + ret = -EINVAL; + goto errout; + } +#endif + /* Get channel mode * TODO: configurable preload for CCxR */ @@ -2531,6 +2614,12 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, ccmr1 = pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET); ccmr2 = pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET); +#ifdef HAVE_IP_TIMERS_V2 + if (priv->timtype == TIMTYPE_ADVANCED) + { + ccmr3 = pwm_getreg(priv, STM32_ATIM_CCMR3_OFFSET); + } +#endif switch (channel) { @@ -2670,6 +2759,62 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, break; } +#ifdef HAVE_IP_TIMERS_V2 + case 5: /* PWM Mode configuration: Channel 5 */ + { + /* Reset current channel 5 mode configuration */ + + ccmr3 &= ~(ATIM_CCMR3_OC5M_MASK | ATIM_CCMR3_OC5PE); + + /* Enable CCR5 preload */ + + ocmode3 |= (chanmode << ATIM_CCMR3_OC5M_SHIFT); + + /* Enable CCR5 preload */ + + ocmode3 |= ATIM_CCMR3_OC5PE; + + /* Reset current OC bit */ + + ccmr3 &= ~(ATIM_CCMR3_OC5M); + + /* Set an additional OC5M bit */ + + if (ocmbit) + { + ocmode3 |= ATIM_CCMR3_OC5M; + } + break; + } + + case 6: /* PWM Mode configuration: Channel 6 */ + { + /* Reset current channel 6 mode configuration */ + + ccmr3 &= ~(ATIM_CCMR3_OC6M_MASK | ATIM_CCMR3_OC6PE); + + /* Enable CCR6 preload */ + + ocmode3 |= (chanmode << ATIM_CCMR3_OC6M_SHIFT); + + /* Enable CCR6 preload */ + + ocmode3 |= ATIM_CCMR3_OC6PE; + + /* Reset current OC bit */ + + ccmr3 &= ~(ATIM_CCMR3_OC6M); + + /* Set an additional OC6M bit */ + + if (ocmbit) + { + ocmode3 |= ATIM_CCMR3_OC6M; + } + break; + } +#endif + default: { pwmerr("ERROR: No such channel: %u\n", channel); @@ -2683,10 +2828,17 @@ static int pwm_mode_configure(FAR struct stm32_pwmtimer_s *priv, ccmr1 |= ocmode1; ccmr2 |= ocmode2; - /* Write CCMR1 and CCMR2 registers */ + /* Write CCMRx registers */ pwm_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); pwm_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); +#ifdef HAVE_IP_TIMERS_V2 + if (priv->timtype == TIMTYPE_ADVANCED) + { + ccmr3 |= ocmode3; + pwm_putreg(priv, STM32_ATIM_CCMR3_OFFSET, ccmr3); + } +#endif errout: return ret; @@ -2919,12 +3071,12 @@ static int pwm_sync_configure(FAR struct stm32_pwmtimer_s *priv, uint8_t trgo) /* Configure TRGO (4 LSB in trgo) */ - cr2 |= (trgo & ATIM_CR2_MMS_MASK) << ATIM_CR2_MMS_SHIFT; + cr2 |= (((trgo>>0) & 0x0F) << ATIM_CR2_MMS_SHIFT) & ATIM_CR2_MMS_MASK; #ifdef HAVE_IP_TIMERS_V2 /* Configure TRGO2 (4 MSB in trgo)*/ - cr2 |= ((trgo>>4) & ATIM_CR2_MMS2_MASK) << ATIM_CR2_MMS2_SHIFT; + cr2 |= (((trgo>>4) & 0x0F) << ATIM_CR2_MMS2_SHIFT) & ATIM_CR2_MMS2_MASK; #endif /* Write register */ @@ -3178,7 +3330,7 @@ static int pwm_pulsecount_configure(FAR struct pwm_lowerhalf_s *dev) /* Configure TRGO/TRGO2 */ #ifdef HAVE_TRGO - ret = pwm_sync_configure(priv, trgo); + ret = pwm_sync_configure(priv, priv->trgo); if (ret < 0) { goto errout; @@ -3420,7 +3572,7 @@ static int pwm_configure(FAR struct pwm_lowerhalf_s *dev) /* Configure TRGO/TRGO2 */ #ifdef HAVE_TRGO - ret = pwm_sync_configure(priv, trgo); + ret = pwm_sync_configure(priv, priv->trgo); if (ret < 0) { goto errout; @@ -3437,7 +3589,6 @@ static int pwm_configure(FAR struct pwm_lowerhalf_s *dev) if (priv->channels[j].channel != 0) { - /* Update PWM mode */ ret = pwm_mode_configure(priv, priv->channels[j].channel, diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index 003af332aa..bacc0e13e9 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -774,87 +774,87 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) { #ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: - freqin = BOARD_TIM1_FREQUENCY; + freqin = STM32_APB2_TIM1_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: - freqin = BOARD_TIM2_FREQUENCY; + freqin = STM32_APB1_TIM2_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: - freqin = BOARD_TIM3_FREQUENCY; + freqin = STM32_APB1_TIM3_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: - freqin = BOARD_TIM4_FREQUENCY; + freqin = STM32_APB1_TIM4_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: - freqin = BOARD_TIM5_FREQUENCY; + freqin = STM32_APB1_TIM5_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: - freqin = BOARD_TIM6_FREQUENCY; + freqin = STM32_APB1_TIM6_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: - freqin = BOARD_TIM7_FREQUENCY; + freqin = STM32_APB1_TIM7_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: - freqin = BOARD_TIM8_FREQUENCY; + freqin = STM32_APB2_TIM8_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: - freqin = BOARD_TIM9_FREQUENCY; + freqin = STM32_APB2_TIM9_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: - freqin = BOARD_TIM10_FREQUENCY; + freqin = STM32_APB2_TIM10_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: - freqin = BOARD_TIM11_FREQUENCY; + freqin = STM32_APB2_TIM11_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: - freqin = BOARD_TIM12_FREQUENCY; + freqin = STM32_APB1_TIM12_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: - freqin = BOARD_TIM13_FREQUENCY; + freqin = STM32_APB1_TIM13_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: - freqin = BOARD_TIM14_FREQUENCY; + freqin = STM32_APB1_TIM14_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: - freqin = BOARD_TIM15_FREQUENCY; + freqin = STM32_APB2_TIM15_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: - freqin = BOARD_TIM16_FREQUENCY; + freqin = STM32_APB2_TIM16_CLKIN; break; #endif #ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: - freqin = BOARD_TIM17_FREQUENCY; + freqin = STM32_APB2_TIM17_CLKIN; break; #endif