From 593dc946d18cb6dc7657c3ce9479d5c744e1cd91 Mon Sep 17 00:00:00 2001
From: Almir Okato <almir.okato@espressif.com>
Date: Mon, 10 Jun 2024 18:07:35 +0200
Subject: [PATCH] esp32: add simple boot support

The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32 targets and removes the need
for running 'make bootloader' command for it.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
---
 .../platforms/xtensa/esp32/index.rst          |  64 ++-
 arch/xtensa/src/common/espressif/Make.defs    |   1 +
 arch/xtensa/src/common/espressif/esp_loader.c |  53 +-
 arch/xtensa/src/esp32/Bootloader.mk           |  28 +-
 arch/xtensa/src/esp32/Kconfig                 |  34 +-
 arch/xtensa/src/esp32/Kconfig.security        |   6 -
 arch/xtensa/src/esp32/Make.defs               |   9 +-
 arch/xtensa/src/esp32/esp32_start.c           | 194 ++-----
 arch/xtensa/src/esp32/hal.mk                  |  39 +-
 .../xtensa/esp32/common/scripts/esp32_rom.ld  |  33 +-
 .../esp32/common/scripts/flat_memory.ld       |  24 +-
 .../esp32/common/scripts/mcuboot_sections.ld  |  28 +-
 .../common/scripts/simple_boot_sections.ld    | 539 ++++++++++++++++++
 .../esp32/esp32-2432S028/scripts/Make.defs    |   2 +
 .../esp32/esp32-audio-kit/scripts/Make.defs   |   2 +
 .../esp32-devkitc/configs/knsh/defconfig      |   1 -
 .../esp32/esp32-devkitc/scripts/Make.defs     |   2 +
 .../esp32-ethernet-kit/scripts/Make.defs      |   2 +
 .../esp32/esp32-lyrat/scripts/Make.defs       |   2 +
 .../esp32/esp32-pico-kit/scripts/Make.defs    |   2 +
 .../esp32/esp32-sparrow-kit/scripts/Make.defs |   2 +
 .../esp32/esp32-wrover-kit/scripts/Make.defs  |   2 +
 .../lilygo_tbeam_lora_gps/scripts/Make.defs   |   2 +
 .../esp32/ttgo_eink5_v2/scripts/Make.defs     |   2 +
 .../esp32/ttgo_lora_esp32/scripts/Make.defs   |   2 +
 .../ttgo_t_display_esp32/scripts/Make.defs    |   2 +
 tools/esp32/Config.mk                         |  26 +
 27 files changed, 864 insertions(+), 239 deletions(-)
 create mode 100644 boards/xtensa/esp32/common/scripts/simple_boot_sections.ld

diff --git a/Documentation/platforms/xtensa/esp32/index.rst b/Documentation/platforms/xtensa/esp32/index.rst
index 8d9b979582..42bb03189c 100644
--- a/Documentation/platforms/xtensa/esp32/index.rst
+++ b/Documentation/platforms/xtensa/esp32/index.rst
@@ -99,14 +99,48 @@ These steps are given in the setup guide in
 Building and flashing NuttX
 ===========================
 
-Firmware for ESP32 is flashed via the USB/UART interface using the ``esptool.py`` tool.
-It's a two step process where the first converts the ELF file into a ESP32-compatible binary
-and the second flashes it to the board.  These steps are included into the build system and you can
-flash your NuttX firmware simply by running::
+Bootloader and partitions
+-------------------------
 
-    $ make flash ESPTOOL_PORT=<port>
+NuttX can boot the ESP32 directly using the so-called "Simple Boot". An externally-built
+2nd stage bootloader is not required in this case as all functions required to boot the device
+are built within NuttX. Simple boot does not require any specific configuration (it is selectable
+by default if no other 2nd stage bootloader is used).
 
-where ``<port>`` is typically ``/dev/ttyUSB0`` or similar. You can change the baudrate by passing ``ESPTOOL_BAUD``.
+If other features are required, an externally-built 2nd stage bootloader is needed. The bootloader
+is built using the ``make bootloader`` command. This command generates the firmware in the
+``nuttx`` folder. The ``ESPTOOL_BINDIR`` is used in the ``make flash`` command to specify the path
+to the bootloader. For compatibility among other SoCs and future options of 2nd stage bootloaders,
+the commands ``make bootloader`` and the ``ESPTOOL_BINDIR`` option (for the ``make flash``) can be
+used even if no externally-built 2nd stage bootloader is being built (they will be ignored if
+Simple Boot is used, for instance)::
+
+  $ make bootloader
+
+.. note:: It is recommended that if this is the first time you are using the board with NuttX to
+   perform a complete SPI FLASH erase.
+
+    .. code-block:: console
+
+      $ esptool.py erase_flash
+
+Building and Flashing
+---------------------
+
+First, make sure that ``esptool.py`` is installed.  This tool is used to convert the ELF to a
+compatible ESP32 image and to flash the image into the board.
+It can be installed with: ``pip install esptool==4.8.dev4``.
+
+It's a two-step process where the first converts the ELF file into an ESP32 compatible binary
+and the second flashes it to the board. These steps are included in the build system and it is
+possible to build and flash the NuttX firmware simply by running::
+
+    $ make flash ESPTOOL_PORT=<port> ESPTOOL_BINDIR=./
+
+where ``<port>`` is typically ``/dev/ttyUSB0`` or similar. ``ESPTOOL_BINDIR=./`` is the path of the
+externally-built 2nd stage bootloader and the partition table (if applicable): when built using the
+``make bootloader``, these files are placed into ``nuttx`` folder. ``ESPTOOL_BAUD`` is able to
+change the flash baud rate if desired.
 
 Debugging with OpenOCD
 ======================
@@ -135,24 +169,6 @@ OpenOCD can then be used::
 
   openocd -c 'set ESP_RTOS hwthread; set ESP_FLASH_SIZE 0' -f board/esp32-wrover-kit-1.8v.cfg
 
-Bootloader and partitions
--------------------------
-
-ESP32 requires a bootloader to be flashed as well as a set of FLASH partitions. This is only needed the first time
-(or any time you which to modify either of these). An easy way is to use prebuilt binaries for NuttX `from here <https://github.com/espressif/esp-nuttx-bootloader>`__. In there you will find instructions to rebuild these if necessary.
-Once you downloaded both binaries, you can flash them by adding an ``ESPTOOL_BINDIR`` parameter, pointing to the directory where these binaries were downloaded:
-
-.. code-block:: console
-
-   $ make flash ESPTOOL_PORT=<port> ESPTOOL_BINDIR=<dir>
-
-.. note:: It is recommended that if this is the first time you are using the board with NuttX that you perform a complete
-   SPI FLASH erase.
-
-   .. code-block:: console
-
-      $ esptool.py erase_flash
-
 Peripheral Support
 ==================
 
diff --git a/arch/xtensa/src/common/espressif/Make.defs b/arch/xtensa/src/common/espressif/Make.defs
index bad999fb28..60684d1749 100644
--- a/arch/xtensa/src/common/espressif/Make.defs
+++ b/arch/xtensa/src/common/espressif/Make.defs
@@ -30,6 +30,7 @@ CHIP_CSRCS += esp_mcpwm.c
 endif
 
 ifeq ($(filter $(CONFIG_ESPRESSIF_SIMPLE_BOOT) \
+      $(CONFIG_ESP32_APP_FORMAT_MCUBOOT) \
       $(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) \
       $(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y),y)
 CHIP_CSRCS += esp_loader.c
diff --git a/arch/xtensa/src/common/espressif/esp_loader.c b/arch/xtensa/src/common/espressif/esp_loader.c
index a0099ea777..bf21c5f096 100644
--- a/arch/xtensa/src/common/espressif/esp_loader.c
+++ b/arch/xtensa/src/common/espressif/esp_loader.c
@@ -35,10 +35,13 @@
 #include "hal/cache_types.h"
 #include "hal/cache_ll.h"
 #include "hal/cache_hal.h"
-#include "soc/extmem_reg.h"
 #include "rom/cache.h"
 #include "spi_flash_mmap.h"
 
+#ifndef CONFIG_ARCH_CHIP_ESP32
+#  include "soc/extmem_reg.h"
+#endif
+
 #  include "bootloader_flash_priv.h"
 #ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
 #  include "bootloader_init.h"
@@ -107,6 +110,16 @@ extern uint8_t _image_drom_size[];
 
 extern int ets_printf(const char *fmt, ...) printf_like(1, 2);
 
+#ifdef CONFIG_ARCH_CHIP_ESP32
+extern void cache_read_enable(int cpu);
+extern void cache_read_disable(int cpu);
+extern void cache_flush(int cpu);
+extern unsigned int cache_flash_mmu_set(int cpu_no, int pid,
+                                        unsigned int vaddr,
+                                        unsigned int paddr,
+                                        int psize, int num);
+#endif
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -140,6 +153,11 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
   uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
   uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK;
 
+#ifdef CONFIG_ARCH_CHIP_ESP32
+  uint32_t drom_page_count = 0;
+  uint32_t irom_page_count = 0;
+#endif
+
 #ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
   esp_image_header_t image_header; /* Header for entire image */
   esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr;
@@ -244,7 +262,8 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
 #endif
 
 #if defined (CONFIG_ESP32S2_APP_FORMAT_MCUBOOT) || \
-    defined (CONFIG_ESP32S3_APP_FORMAT_MCUBOOT)
+    defined (CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \
+    defined (CONFIG_ESP32_APP_FORMAT_MCUBOOT)
   ets_printf("IROM segment aligned lma 0x%08x vma 0x%08x len 0x%06x (%u)\n",
       app_irom_start_aligned, app_irom_vaddr_aligned,
       app_irom_size, app_irom_size);
@@ -253,7 +272,12 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
       app_drom_size, app_drom_size);
 #endif
 
+#ifdef CONFIG_ARCH_CHIP_ESP32
+  cache_read_disable(0);
+  cache_flush(0);
+#else
   cache_hal_disable(CACHE_TYPE_ALL);
+#endif
 
   /* Clear the MMU entries that are already set up,
    * so the new app only has the mappings it creates.
@@ -261,6 +285,25 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
 
   mmu_hal_unmap_all();
 
+#ifdef CONFIG_ARCH_CHIP_ESP32
+  drom_page_count = (app_drom_size + SPI_FLASH_MMU_PAGE_SIZE - 1) /
+                              SPI_FLASH_MMU_PAGE_SIZE;
+  rc  = cache_flash_mmu_set(0, 0, app_drom_vaddr_aligned,
+                            app_drom_start_aligned, 64,
+                            (int)drom_page_count);
+  rc |= cache_flash_mmu_set(1, 0, app_drom_vaddr_aligned,
+                            app_drom_start_aligned, 64,
+                            (int)drom_page_count);
+
+  irom_page_count = (app_irom_size + SPI_FLASH_MMU_PAGE_SIZE - 1) /
+                              SPI_FLASH_MMU_PAGE_SIZE;
+  rc |= cache_flash_mmu_set(0, 0, app_irom_vaddr_aligned,
+                            app_irom_start_aligned, 64,
+                            (int)irom_page_count);
+  rc |= cache_flash_mmu_set(1, 0, app_irom_vaddr_aligned,
+                            app_irom_start_aligned, 64,
+                            (int)irom_page_count);
+#else
   mmu_hal_map_region(0, MMU_TARGET_FLASH0,
                      app_drom_vaddr_aligned, app_drom_start_aligned,
                      app_drom_size, &actual_mapped_len);
@@ -268,6 +311,7 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
   mmu_hal_map_region(0, MMU_TARGET_FLASH0,
                      app_irom_vaddr_aligned, app_irom_start_aligned,
                      app_irom_size, &actual_mapped_len);
+#endif
 
   /* ------------------Enable corresponding buses--------------------- */
 
@@ -285,7 +329,10 @@ int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr,
 
   /* ------------------Enable Cache----------------------------------- */
 
+#ifdef CONFIG_ARCH_CHIP_ESP32
+  cache_read_enable(0);
+#else
   cache_hal_enable(CACHE_TYPE_ALL);
-
+#endif
   return (int)rc;
 }
diff --git a/arch/xtensa/src/esp32/Bootloader.mk b/arch/xtensa/src/esp32/Bootloader.mk
index 3041f370a0..2fd6e99165 100644
--- a/arch/xtensa/src/esp32/Bootloader.mk
+++ b/arch/xtensa/src/esp32/Bootloader.mk
@@ -20,7 +20,7 @@
 
 .PHONY: bootloader clean_bootloader
 
-ifeq ($(CONFIG_ESP32_BOOTLOADER_BUILD_FROM_SOURCE),y)
+ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),)
 
 TOOLSDIR           = $(TOPDIR)/tools/espressif
 CHIPDIR            = $(TOPDIR)/arch/xtensa/src/chip
@@ -112,8 +112,13 @@ else ifeq ($(CONFIG_ESP32_APP_FORMAT_LEGACY),y)
 		$(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32_PARTITION_TABLE_OFFSET)) \
 	} >> $(BOOTLOADER_CONFIG)
 endif
+endif
 
-ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
+ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+bootloader:
+	$(Q) echo "Using direct bootloader to boot NuttX."
+
+else ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
 
 BOOTLOADER_BIN        = $(TOPDIR)/mcuboot-esp32.bin
 BOOTLOADER_SIGNED_BIN = $(TOPDIR)/mcuboot-esp32.signed.bin
@@ -186,22 +191,3 @@ clean_bootloader:
 	$(call DELFILE,$(TOPDIR)/partition-table-esp32.bin)
 
 endif
-
-else ifeq ($(CONFIG_ESP32_BOOTLOADER_DOWNLOAD_PREBUILT),y)
-
-BOOTLOADER_VERSION = latest
-BOOTLOADER_URL     = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION)
-
-ifeq ($(CONFIG_ESP32_APP_FORMAT_LEGACY),y)
-
-bootloader:
-	$(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32.bin,$(TOPDIR)/bootloader-esp32.bin)
-	$(call DOWNLOAD,$(BOOTLOADER_URL),partition-table-esp32.bin,$(TOPDIR)/partition-table-esp32.bin)
-
-clean_bootloader:
-	$(call DELFILE,$(TOPDIR)/bootloader-esp32.bin)
-	$(call DELFILE,$(TOPDIR)/partition-table-esp32.bin)
-
-endif
-
-endif
diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig
index a3f62ea313..9135ee6562 100644
--- a/arch/xtensa/src/esp32/Kconfig
+++ b/arch/xtensa/src/esp32/Kconfig
@@ -103,6 +103,11 @@ config ESPRESSIF_CHIP_SERIES
 	string
 	default "esp32"
 
+config ESPRESSIF_NUM_CPUS
+	int
+	default 1 if ESP32_SINGLE_CPU
+	default 2 if ESP32_DUAL_CPU
+
 config ESP32_SINGLE_CPU
 	bool
 	default n
@@ -1890,7 +1895,6 @@ comment "Partition Table Configuration"
 config ESP32_PARTITION_TABLE
 	bool "Create MTD partitions from Partition Table"
 	default n
-	select ESP32_BOOTLOADER_BUILD_FROM_SOURCE
 	---help---
 		Decode partition table and initialize partitions as MTD.
 
@@ -2560,10 +2564,14 @@ config ESP32_HAVE_OTA_PARTITION
 
 menu "Bootloader and Image Configuration"
 
+config ESPRESSIF_SIMPLE_BOOT
+	bool
+	depends on !ESP32_APP_FORMAT_MCUBOOT && !ESP32_APP_FORMAT_LEGACY
+	default y
+
 config ESP32_APP_FORMAT_LEGACY
 	bool "Enable legacy IDF bootloader format"
-	default y if !ESP32_APP_FORMAT_MCUBOOT
-	depends on !ESP32_APP_FORMAT_MCUBOOT
+	default y if BUILD_PROTECTED
 	---help---
 		This is the legacy application image format, as supported by the ESP-IDF
 		2nd stage bootloader.
@@ -2571,28 +2579,11 @@ config ESP32_APP_FORMAT_LEGACY
 config ESP32_APP_FORMAT_MCUBOOT
 	bool "Enable MCUboot-bootable format"
 	depends on !MCUBOOT_BOOTLOADER
+	default n
 	select ESP32_HAVE_OTA_PARTITION
-	select ESP32_BOOTLOADER_BUILD_FROM_SOURCE
 	---help---
 		Enables the Espressif port of MCUboot to be used as 2nd stage bootloader.
 
-config ESP32_BOOTLOADER_DOWNLOAD_PREBUILT
-	bool
-	default y if !ESP32_BOOTLOADER_BUILD_FROM_SOURCE
-	depends on !ESP32_BOOTLOADER_BUILD_FROM_SOURCE
-	---help---
-		The build system will download the prebuilt binaries from
-		https://github.com/espressif/esp-nuttx-bootloader according to the chosen
-		Application Image Format (ESP32_APP_FORMAT_LEGACY or ESP32_APP_FORMAT_MCUBOOT)
-
-config ESP32_BOOTLOADER_BUILD_FROM_SOURCE
-	bool "Build binaries from source"
-	---help---
-		The build system will build all the required binaries from source. It will clone
-		the https://github.com/espressif/esp-nuttx-bootloader repository and build a
-		custom bootloader according to the chosen Application Image Format
-		(ESP32_APP_FORMAT_LEGACY or ESP32_APP_FORMAT_MCUBOOT) and partition information.
-
 choice
 	prompt "Target slot for image flashing"
 	default ESP32_ESPTOOL_TARGET_PRIMARY
@@ -2637,7 +2628,6 @@ config ESP32_CUSTOM_PARTITION_TABLE_OFFSET
 	bool "Customize partition table offset"
 	default n
 	depends on ESP32_APP_FORMAT_LEGACY
-	select ESP32_BOOTLOADER_BUILD_FROM_SOURCE
 	---help---
 		Enable to select the offset of the partition table in the flash.
 
diff --git a/arch/xtensa/src/esp32/Kconfig.security b/arch/xtensa/src/esp32/Kconfig.security
index 1422b23e55..67ccaaf605 100644
--- a/arch/xtensa/src/esp32/Kconfig.security
+++ b/arch/xtensa/src/esp32/Kconfig.security
@@ -20,9 +20,6 @@ config ESP32_SECURE_BOOT
 
 if ESP32_SECURE_BOOT
 
-comment "Secure Boot support requires building the bootloader from source (ESP32_BOOTLOADER_BUILD_FROM_SOURCE)"
-	depends on !ESP32_BOOTLOADER_BUILD_FROM_SOURCE
-
 config ESP32_SECURE_BOOT_BUILD_SIGNED_BINARIES
 	bool "Sign binaries during build"
 	default y
@@ -117,9 +114,6 @@ config ESP32_SECURE_FLASH_ENC_ENABLED
 
 if ESP32_SECURE_FLASH_ENC_ENABLED
 
-comment "Flash Encryption support requires building the bootloader from source (ESP32_BOOTLOADER_BUILD_FROM_SOURCE)"
-	depends on !ESP32_BOOTLOADER_BUILD_FROM_SOURCE
-
 choice ESP32_SECURE_FLASH_ENCRYPTION_MODE
 	bool "Enable usage mode"
 	default ESP32_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs
index a7a604e754..e88f10847d 100644
--- a/arch/xtensa/src/esp32/Make.defs
+++ b/arch/xtensa/src/esp32/Make.defs
@@ -208,7 +208,7 @@ endif
 
 ESP_HAL_3RDPARTY_REPO   = esp-hal-3rdparty
 ifndef ESP_HAL_3RDPARTY_VERSION
-	ESP_HAL_3RDPARTY_VERSION = 966f1bbf7d80d3fac9a43f414e864985cbcfd680
+	ESP_HAL_3RDPARTY_VERSION = 0e6895d4ce431ce95b156027e6e3af50f9b4df37
 endif
 
 ifndef ESP_HAL_3RDPARTY_URL
@@ -232,6 +232,10 @@ chip/$(ESP_HAL_3RDPARTY_REPO):
 
 CFLAGS += -Wno-undef -Wno-unused-variable
 
+# Enable strict volatile bitfield access
+
+CFLAGS += -fstrict-volatile-bitfields
+
 # Files that require the HAL recipe
 
 CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES))
@@ -251,9 +255,6 @@ ifeq ($(CONFIG_ESP32_WIRELESS),y)
 	$(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch
 endif
 
-distclean::
-	$(call DELDIR, chip/$(ESP_HAL_3RDPARTY_REPO))
-
 ifeq ($(CONFIG_ESP32_WIRELESS),y)
 include chip/Wireless.mk
 endif
diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c
index 30679d7840..584f687572 100644
--- a/arch/xtensa/src/esp32/esp32_start.c
+++ b/arch/xtensa/src/esp32/esp32_start.c
@@ -47,6 +47,12 @@
 #include "hardware/esp32_dport.h"
 #include "hardware/esp32_rtccntl.h"
 #include "rom/esp32_libc_stubs.h"
+#include "espressif/esp_loader.h"
+
+#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
+#  include "bootloader_init.h"
+#  include "esp_rom_spiflash.h"
+#endif
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -58,28 +64,26 @@
 #  define showprogress(c)
 #endif
 
-#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
+#if defined(CONFIG_ESP32_APP_FORMAT_MCUBOOT) || \
+    defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
+#  ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
+#    define PRIMARY_SLOT_OFFSET   CONFIG_ESP32_OTA_PRIMARY_SLOT_OFFSET
+#  else
+     /* Force offset to the beginning of the whole image */
 
-#define PRIMARY_SLOT_OFFSET   CONFIG_ESP32_OTA_PRIMARY_SLOT_OFFSET
-
-#define HDR_ATTR              __attribute__((section(".entry_addr"))) \
+#    define PRIMARY_SLOT_OFFSET   0x0000
+#  endif
+#  define HDR_ATTR              __attribute__((section(".entry_addr"))) \
                                 __attribute__((used))
 
-/* Cache MMU block size */
-
-#define MMU_BLOCK_SIZE        0x00010000  /* 64 KB */
-
-/* Cache MMU address mask (MMU tables ignore bits which are zero) */
-
-#define MMU_FLASH_MASK        (~(MMU_BLOCK_SIZE - 1))
-
 #endif
 
 /****************************************************************************
  * Private Types
  ****************************************************************************/
 
-#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
+#if defined(CONFIG_ESP32_APP_FORMAT_MCUBOOT) || \
+    defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
 extern uint8_t _image_irom_vma[];
 extern uint8_t _image_irom_lma[];
 extern uint8_t _image_irom_size[];
@@ -95,21 +99,12 @@ extern uint8_t _image_drom_size[];
 
 extern int ets_printf(const char *fmt, ...) printf_like(1, 2);
 
-#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
-extern void cache_read_enable(int cpu);
-extern void cache_read_disable(int cpu);
-extern void cache_flush(int cpu);
-extern unsigned int cache_flash_mmu_set(int cpu_no, int pid,
-                                        unsigned int vaddr,
-                                        unsigned int paddr,
-                                        int psize, int num);
-#endif
-
 /****************************************************************************
  * Private Function Prototypes
  ****************************************************************************/
 
-#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
+#if defined(CONFIG_ESP32_APP_FORMAT_MCUBOOT) || \
+    defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
 noreturn_function void __start(void);
 #endif
 
@@ -125,7 +120,8 @@ extern void esp32_lowsetup(void);
  * Private Data
  ****************************************************************************/
 
-#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
+#if defined(CONFIG_ESP32_APP_FORMAT_MCUBOOT) || \
+    defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
 HDR_ATTR static void (*_entry_point)(void) = __start;
 #endif
 
@@ -144,9 +140,10 @@ uint32_t g_idlestack[IDLETHREAD_STACKWORDS]
 
 static noreturn_function void __esp32_start(void)
 {
-  uint32_t sp;
   uint32_t regval unused_data;
   uint32_t chip_rev;
+#ifndef CONFIG_ESPRESSIF_SIMPLE_BOOT
+  uint32_t sp;
 
   /* Make sure that normal interrupts are disabled.  This is really only an
    * issue when we are started in un-usual ways (such as from IRAM).  In this
@@ -193,6 +190,8 @@ static noreturn_function void __esp32_start(void)
 
   memset(_sbss, 0, _ebss - _sbss);
 
+#endif
+
 #ifndef CONFIG_SMP
   /* Make sure that the APP_CPU is disabled for now */
 
@@ -295,109 +294,6 @@ static noreturn_function void __esp32_start(void)
   for (; ; ); /* Should not return */
 }
 
-/****************************************************************************
- * Name: calc_mmu_pages
- *
- * Description:
- *   Calculate the number of cache pages to map.
- *
- * Input Parameters:
- *   size  - Size of data to map
- *   vaddr - Virtual address where data will be mapped
- *
- * Returned Value:
- *   Number of cache MMU pages required to do the mapping.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
-static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr)
-{
-  return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) /
-    MMU_BLOCK_SIZE;
-}
-#endif
-
-/****************************************************************************
- * Name: map_rom_segments
- *
- * Description:
- *   Configure the MMU and Cache peripherals for accessing ROM code and data.
- *
- * Input Parameters:
- *   None.
- *
- * Returned Value:
- *   None.
- *
- ****************************************************************************/
-
-#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
-static int map_rom_segments(void)
-{
-  uint32_t rc = 0;
-  uint32_t regval;
-  uint32_t drom_lma_aligned;
-  uint32_t drom_vma_aligned;
-  uint32_t drom_page_count;
-  uint32_t irom_lma_aligned;
-  uint32_t irom_vma_aligned;
-  uint32_t irom_page_count;
-
-  size_t partition_offset = PRIMARY_SLOT_OFFSET;
-  uint32_t app_irom_lma = partition_offset + (uint32_t)_image_irom_lma;
-  uint32_t app_irom_size = (uint32_t)_image_irom_size;
-  uint32_t app_irom_vma = (uint32_t)_image_irom_vma;
-  uint32_t app_drom_lma = partition_offset + (uint32_t)_image_drom_lma;
-  uint32_t app_drom_size = (uint32_t)_image_drom_size;
-  uint32_t app_drom_vma = (uint32_t)_image_drom_vma;
-
-  volatile uint32_t *pro_flash_mmu_table =
-    (volatile uint32_t *)DPORT_PRO_FLASH_MMU_TABLE_REG;
-
-  cache_read_disable(0);
-  cache_flush(0);
-
-  /* Clear the MMU entries that are already set up, so the new app only has
-   * the mappings it creates.
-   */
-
-  for (int i = 0; i < DPORT_FLASH_MMU_TABLE_SIZE; i++)
-    {
-      putreg32(DPORT_FLASH_MMU_TABLE_INVALID_VAL, pro_flash_mmu_table++);
-    }
-
-  drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK;
-  drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK;
-  drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma);
-  rc  = cache_flash_mmu_set(0, 0, drom_vma_aligned, drom_lma_aligned, 64,
-                            (int)drom_page_count);
-  rc |= cache_flash_mmu_set(1, 0, drom_vma_aligned, drom_lma_aligned, 64,
-                            (int)drom_page_count);
-
-  irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK;
-  irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK;
-  irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma);
-  rc |= cache_flash_mmu_set(0, 0, irom_vma_aligned, irom_lma_aligned, 64,
-                            (int)irom_page_count);
-  rc |= cache_flash_mmu_set(1, 0, irom_vma_aligned, irom_lma_aligned, 64,
-                            (int)irom_page_count);
-
-  regval  = getreg32(DPORT_PRO_CACHE_CTRL1_REG);
-  regval &= ~(DPORT_PRO_CACHE_MASK_IRAM0 | DPORT_PRO_CACHE_MASK_DROM0 |
-              DPORT_PRO_CACHE_MASK_DRAM1);
-  putreg32(regval, DPORT_PRO_CACHE_CTRL1_REG);
-
-  regval  = getreg32(DPORT_APP_CACHE_CTRL1_REG);
-  regval &= ~(DPORT_APP_CACHE_MASK_IRAM0 | DPORT_APP_CACHE_MASK_DROM0 |
-              DPORT_APP_CACHE_MASK_DRAM1);
-  putreg32(regval, DPORT_APP_CACHE_CTRL1_REG);
-
-  cache_read_enable(0);
-  return (int)rc;
-}
-#endif
-
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -415,10 +311,44 @@ static int map_rom_segments(void)
  *
  ****************************************************************************/
 
-void __start(void)
+noreturn_function void __start(void)
 {
-#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
-  if (map_rom_segments() != 0)
+#if defined(CONFIG_ESP32_APP_FORMAT_MCUBOOT) || \
+    defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
+  size_t partition_offset = PRIMARY_SLOT_OFFSET;
+  uint32_t app_irom_start = partition_offset + (uint32_t)_image_irom_lma;
+  uint32_t app_irom_size  = (uint32_t)_image_irom_size;
+  uint32_t app_irom_vaddr = (uint32_t)_image_irom_vma;
+  uint32_t app_drom_start = partition_offset + (uint32_t)_image_drom_lma;
+  uint32_t app_drom_size  = (uint32_t)_image_drom_size;
+  uint32_t app_drom_vaddr = (uint32_t)_image_drom_vma;
+
+#  ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT
+  uint32_t sp;
+
+  /* Move CPU0 exception vectors to IRAM */
+
+  __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start));
+
+  /* Move the stack to a known location.  Although we were given a stack
+   * pointer at start-up, we don't know where that stack pointer is
+   * positioned with respect to our memory map.  The only safe option is to
+   * switch to a well-known IDLE thread stack.
+   */
+
+  sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE;
+  __asm__ __volatile__("mov sp, %0\n" : : "r"(sp));
+
+  if (bootloader_init() != 0)
+    {
+      ets_printf("Hardware init failed, aborting\n");
+      while (true);
+    }
+
+#  endif
+
+  if (map_rom_segments(app_drom_start, app_drom_vaddr, app_drom_size,
+                       app_irom_start, app_irom_vaddr, app_irom_size) != 0)
     {
       ets_printf("Failed to setup XIP, aborting\n");
       while (true);
diff --git a/arch/xtensa/src/esp32/hal.mk b/arch/xtensa/src/esp32/hal.mk
index b9009a1be7..e0c795aa49 100644
--- a/arch/xtensa/src/esp32/hal.mk
+++ b/arch/xtensa/src/esp32/hal.mk
@@ -53,6 +53,11 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash
+INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include
 INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include
 
@@ -67,7 +72,7 @@ ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c
 
-# Please note that the following source file depends on `CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD` and `CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK` 
+# Please note that the following source file depends on `CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD` and `CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK`
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)without_key_purposes$(DELIM)three_key_blocks$(DELIM)esp_efuse_api_key.c
 
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c
@@ -102,6 +107,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c
@@ -109,4 +115,35 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c
 
+ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console_loader.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_${CHIP_SERIES}.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_init.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c
+  CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c
+
+  LDFLAGS += --wrap=bootloader_print_banner
+endif
+
 CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1
diff --git a/boards/xtensa/esp32/common/scripts/esp32_rom.ld b/boards/xtensa/esp32/common/scripts/esp32_rom.ld
index 43964d41f0..7554b74c32 100644
--- a/boards/xtensa/esp32/common/scripts/esp32_rom.ld
+++ b/boards/xtensa/esp32/common/scripts/esp32_rom.ld
@@ -1992,27 +1992,11 @@ PROVIDE ( xthal_set_intclear = 0x4000c1ec );
 PROVIDE ( _xtos_set_intlevel = 0x4000bfdc );
 PROVIDE ( g_ticks_per_us_pro = 0x3ffe01e0 );
 PROVIDE ( g_ticks_per_us_app = 0x3ffe40f0 );
-PROVIDE ( esp_rom_spiflash_attach = 0x40062a6c );
 PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 );
 PROVIDE ( esp_rom_spiflash_config_param = 0x40063238 );
-PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062b64 ); /* SPIMasterReadModeCnfig */
-PROVIDE ( esp_rom_spiflash_enable_write = 0x40062320 );
-PROVIDE ( esp_rom_spiflash_erase_area = 0x400631ac );
-PROVIDE ( esp_rom_spiflash_erase_block = 0x40062c4c );
-PROVIDE ( esp_rom_spiflash_erase_chip = 0x40062c14 );
-PROVIDE ( esp_rom_spiflash_erase_sector = 0x40062ccc );
-PROVIDE ( esp_rom_spiflash_lock = 0x400628f0 );
 PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );
-PROVIDE ( esp_rom_spiflash_read = 0x40062ed8 );
-PROVIDE ( esp_rom_spiflash_read_status = 0x4006226c );
-PROVIDE ( esp_rom_spiflash_read_statushigh = 0x40062448 );
 PROVIDE ( esp_rom_spiflash_read_user_cmd = 0x400621b0 );
 PROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc );
-PROVIDE ( esp_rom_spiflash_write = 0x40062d50 );
-PROVIDE ( esp_rom_spiflash_write_encrypted = 0x40062e78 );
-PROVIDE ( esp_rom_spiflash_write_encrypted_disable = 0x40062e60 );
-PROVIDE ( esp_rom_spiflash_write_encrypted_enable = 0x40062df4 );
-PROVIDE ( esp_rom_spiflash_write_status = 0x400622f0 );
 PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );
 PROVIDE ( hci_le_rd_rem_used_feats_cmd_handler = 0x400417b4 );
 PROVIDE ( llcp_length_req_handler = 0x40043808 );
@@ -2054,6 +2038,23 @@ PROVIDE ( esp_rom_spiflash_prepare_encrypted_data = 0x40062e1c );
 PROVIDE ( esp_rom_printf   = ets_printf );
 PROVIDE ( esp_rom_delay_us = ets_delay_us );
 
+/* ESP32 ROM SPIFLASH functions */
+
+PROVIDE ( esp_rom_spiflash_attach = 0x40062a6c );
+PROVIDE ( esp_rom_spiflash_config_readmode = 0x40062b64 );
+PROVIDE ( esp_rom_spiflash_enable_write = 0x40062320 );
+PROVIDE ( esp_rom_spiflash_erase_area = 0x400631ac );
+PROVIDE ( esp_rom_spiflash_erase_block = 0x40062c4c );
+PROVIDE ( esp_rom_spiflash_erase_chip = 0x40062c14 );
+PROVIDE ( esp_rom_spiflash_erase_sector = 0x40062ccc );
+PROVIDE ( esp_rom_spiflash_lock = 0x400628f0 );
+PROVIDE ( esp_rom_spiflash_read = 0x40062ed8 );
+PROVIDE ( esp_rom_spiflash_read_status = 0x4006226c );
+PROVIDE ( esp_rom_spiflash_read_statushigh = 0x40062448 );
+PROVIDE ( esp_rom_spiflash_write = 0x40062d50 );
+PROVIDE ( esp_rom_spiflash_write_encrypted = 0x40062e78 );
+PROVIDE ( esp_rom_spiflash_write_status = 0x400622f0 );
+
 /* Following are static data, but can be used, not generated by script <<<<< btdm data */
 
 PROVIDE ( hci_tl_env = 0x3ffb8154 );
diff --git a/boards/xtensa/esp32/common/scripts/flat_memory.ld b/boards/xtensa/esp32/common/scripts/flat_memory.ld
index 942d1794e8..ed92a58676 100644
--- a/boards/xtensa/esp32/common/scripts/flat_memory.ld
+++ b/boards/xtensa/esp32/common/scripts/flat_memory.ld
@@ -43,6 +43,8 @@
 #  define FLASH_SIZE 0x1000000
 #endif
 
+#define SRAM1_IRAM_LEN 0xa000
+
 MEMORY
 {
 #ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT
@@ -58,6 +60,17 @@ MEMORY
   metadata (RX) :        org = CONFIG_ESP32_APP_MCUBOOT_HEADER_SIZE, len = 0x20
   ROM (RX) :             org = ORIGIN(metadata) + LENGTH(metadata),
                          len = FLASH_SIZE - ORIGIN(ROM)
+
+#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
+  /* The 0x20 offset is a convenience for the app binary image generation.
+   * Flash cache has 64KB pages. The .bin file which is flashed to the chip
+   * has a 0x18 byte file header, and each segment has a 0x08 byte segment
+   * header. Setting this offset makes it simple to meet the flash cache MMU's
+   * constraint that (paddr % 64KB == vaddr % 64KB).
+   */
+
+  ROM (RX) :             org = 0x20,
+                         len = FLASH_SIZE - ORIGIN(ROM)
 #endif
 
   /* Below values assume the flash cache is on, and have the blocks this
@@ -68,7 +81,7 @@ MEMORY
 
   /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
 
-  iram0_0_seg (RX) :     org = 0x40080000, len = 0x20000
+  iram0_0_seg (RX) :     org = 0x40080000, len = 0x20000 + SRAM1_IRAM_LEN
 
   /* Flash mapped instruction data. */
 
@@ -152,13 +165,18 @@ MEMORY
   REGION_ALIAS("default_code_seg", irom0_0_seg);
 #endif /* CONFIG_ESP32_RUN_IRAM */
 
+_sram1_iram_start = 0x400a0000;
+_sram1_iram_len = ( _iram_text_end > _sram1_iram_start) ? (_iram_text_end - _sram1_iram_start) : 0;
+
 /* Heap ends at top of dram0_0_seg */
 
-_eheap = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
+_eheap = (_iram_text_end > _sram1_iram_start) ?
+  ALIGN(0x40000000 - _sram1_iram_len - 3, 4) - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM :
+  0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
 
 /* IRAM heap ends at top of dram0_0_seg */
 
-_eiramheap = 0x400a0000;
+_eiramheap = (_iram_text_end > _sram1_iram_start) ? ALIGN(_iram_text_end, 4) : 0x400a0000;
 
 /* Mark the end of the RTC heap (top of the RTC region) */
 
diff --git a/boards/xtensa/esp32/common/scripts/mcuboot_sections.ld b/boards/xtensa/esp32/common/scripts/mcuboot_sections.ld
index 21eefff381..b9a850ff9c 100644
--- a/boards/xtensa/esp32/common/scripts/mcuboot_sections.ld
+++ b/boards/xtensa/esp32/common/scripts/mcuboot_sections.ld
@@ -63,8 +63,16 @@ SECTIONS
   {
     . = ALIGN(4);
     _srodata = ABSOLUTE(.);
-    *(EXCLUDE_FILE (*libarch.a:esp32_spiflash.* esp32_start.*) .rodata)
-    *(EXCLUDE_FILE (*libarch.a:esp32_spiflash.* esp32_start.*) .rodata.*)
+    *(EXCLUDE_FILE (*libarch.a:esp32_spiflash.* esp32_start.*
+                    *libarch.a:*esp_loader.*
+                    *libarch.a:*uart_hal.*
+                    *libarch.a:*mmu_hal.*
+                    ) .rodata)
+    *(EXCLUDE_FILE (*libarch.a:esp32_spiflash.* esp32_start.*
+                    *libarch.a:*esp_loader.*
+                    *libarch.a:*uart_hal.*
+                    *libarch.a:*mmu_hal.*
+                    ) .rodata.*)
     *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
     *(.gnu.linkonce.r.*)
     *(.rodata1)
@@ -157,12 +165,15 @@ SECTIONS
 
     _iram_text_start = ABSOLUTE(.);
     *(.iram1 .iram1.*)
+    esp32_start.*(.literal .text .literal.* .text.*)
     *libphy.a:(.literal .text .literal.* .text.*)
     *librtc.a:(.literal .text .literal.* .text.*)
     *libpp.a:(.literal .text .literal.* .text.*)
     *libhal.a:(.literal .text .literal.* .text.*)
     *libarch.a:esp32_spiflash.*(.literal .text .literal.* .text.*)
-    esp32_start.*(.literal .text .literal.* .text.*)
+    *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_loader.*(.text .text.* .literal .literal.*)
     *(.wifirxiram .wifirxiram.*)
     *(.wifirxiram .wifi0iram.*)
     *(.wifislpiram .wifislpiram.*)
@@ -183,6 +194,7 @@ SECTIONS
     /* .bss initialized on power-up */
 
     . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
     _sbss = ABSOLUTE(.);
     *(.dynsbss)
     *(.sbss)
@@ -200,6 +212,7 @@ SECTIONS
     *(COMMON)
     . = ALIGN(8);
     _ebss = ABSOLUTE(.);
+    _bss_end = ABSOLUTE(.);
   } >dram0_0_seg
 
   .noinit (NOLOAD):
@@ -231,8 +244,11 @@ SECTIONS
     KEEP (*(.gnu.linkonce.s2.*))
     KEEP (*(.jcr))
     *(.dram1 .dram1.*)
-    *libarch.a:esp32_spiflash.*(.rodata  .rodata.*)
     esp32_start.*(.rodata  .rodata.*)
+    *libarch.a:esp32_spiflash.*(.rodata  .rodata.*)
+    *libarch.a:*esp_loader.*(.rodata .rodata.*)
+    *libarch.a:*mmu_hal.*(.rodata .rodata.*)
+    *libarch.a:*uart_hal.*(.rodata .rodata.*)
     _edata = ABSOLUTE(.);
     . = ALIGN(4);
 
@@ -256,7 +272,7 @@ SECTIONS
   _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
 
   /* The alignment of the ".flash.text" output section is forced to
-   * 0x0000FFFF (64KB) to ensure that it will be allocated at the beginning
+   * 0x00010000 (64KB) to ensure that it will be allocated at the beginning
    * of the next available Flash block.
    * This is required to meet the following constraint from the external
    * flash MMU:
@@ -266,7 +282,7 @@ SECTIONS
    * be equal.
    */
 
-  .flash.text : ALIGN(0x0000FFFF)
+  .flash.text : ALIGN(0x00010000)
   {
     _stext = .;
     _text_start = ABSOLUTE(.);
diff --git a/boards/xtensa/esp32/common/scripts/simple_boot_sections.ld b/boards/xtensa/esp32/common/scripts/simple_boot_sections.ld
new file mode 100644
index 0000000000..b5225645fd
--- /dev/null
+++ b/boards/xtensa/esp32/common/scripts/simple_boot_sections.ld
@@ -0,0 +1,539 @@
+/****************************************************************************
+ * boards/xtensa/esp32/common/scripts/simple_boot_sections.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Default entry point: */
+
+ENTRY(__start);
+
+SECTIONS
+{
+  /* Send .iram0 code to iram */
+
+  .iram0.vectors :
+  {
+    /* Vectors go to IRAM */
+
+    _init_start = ABSOLUTE(.);
+
+    /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */
+
+    . = 0x0;
+    KEEP (*(.window_vectors.text));
+    . = 0x180;
+    KEEP (*(.xtensa_level2_vector.text));
+    . = 0x1c0;
+    KEEP (*(.xtensa_level3_vector.text));
+    . = 0x200;
+    KEEP (*(.xtensa_level4_vector.text));
+    . = 0x240;
+    KEEP (*(.xtensa_level5_vector.text));
+    . = 0x280;
+    KEEP (*(.debug_exception_vector.text));
+    . = 0x2c0;
+    KEEP (*(.nmi_vector.text));
+    . = 0x300;
+    KEEP (*(.kernel_exception_vector.text));
+    . = 0x340;
+    KEEP (*(.user_exception_vector.text));
+    . = 0x3c0;
+    KEEP (*(.double_exception_vector.text));
+    . = 0x400;
+    *(.*_vector.literal)
+
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+    _init_end = ABSOLUTE(.);
+  } >iram0_0_seg AT>ROM
+
+  .iram0.text : ALIGN(4)
+  {
+    /* Code marked as running out of IRAM */
+
+    _iram_text_start = ABSOLUTE(.);
+    *(.iram1 .iram1.*)
+    esp32_start.*(.literal .text .literal.* .text.*)
+    *libphy.a:(.literal .text .literal.* .text.*)
+    *librtc.a:(.literal .text .literal.* .text.*)
+    *libpp.a:(.literal .text .literal.* .text.*)
+    *libhal.a:(.literal .text .literal.* .text.*)
+    *libarch.a:*esp_loader.*(.literal .text .literal.* .text.*)
+    *libarch.a:*brownout_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*cpu.*(.text .text.* .literal .literal.*)
+    *libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*)
+    *libarch.a:*clk.*(.text .text.* .literal .literal.*)
+    *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*)
+    *libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*)
+    *libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*)
+    *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*)
+    *libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*)
+    *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*)
+    *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_esp32.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_flash_config_esp32.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libarch.a:*bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libarch.a:*bootloader_random_esp32.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*)
+    *libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*)
+    *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
+    *libarch.a:*uart_periph.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*)
+    *libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*)
+    *libarch.a:*log.*(.text .text.* .literal .literal.*)
+    *libarch.a:*log_noos.*(.text .text.* .literal .literal.*)
+    *libarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*)
+
+#ifdef CONFIG_STACK_CANARIES
+    *libc.a:lib_stackchk.*(.literal .text .literal.* .text.*)
+#endif
+    *libarch.a:esp32_cpuindex.*(.literal .text .literal.* .text.*)
+    *libarch.a:esp32_irq.*(.literal .text .literal.* .text.*)
+    *libarch.a:esp32_spicache.*(.literal .text .literal.* .text.*)
+    *libarch.a:esp32_spiflash.*(.literal .text .literal.* .text.*)
+    *libarch.a:esp32_user.*(.literal .text .literal.* .text.*)
+    *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*)
+    *libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*)
+    *libarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*)
+    *libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*)
+    *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*)
+    *libarch.a:xtensa_saveusercontext.*(.literal .text .literal.* .text.*)
+    *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
+
+    *libc.a:lib_assert.*(.literal .text .literal.* .text.*)
+    *libc.a:lib_utsname.*(.literal .text .literal.* .text.*)
+#ifdef CONFIG_ESP32_BLE
+    *libc.a:sq_remlast.*(.literal .text .literal.* .text.*)
+#endif
+
+    *libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*)
+
+    *libsched.a:assert.*(.literal .text .literal.* .text.*)
+    *libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
+    *libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
+    *libsched.a:irq_spinlock.*(.literal .text .literal.* .text.*)
+    *libsched.a:panic_notifier.*(.literal.panic_notifier_call_chain .text.panic_notifier_call_chain)
+    *libsched.a:sched_gettcb.*(.literal .text .literal.* .text.*)
+    *libsched.a:sched_lock.*(.literal .text .literal.* .text.*)
+    *libsched.a:sched_note.*(.literal .text .literal.* .text.*)
+    *libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*)
+    *libsched.a:sched_thistask.*(.literal .text .literal.* .text.*)
+    *libsched.a:sched_unlock.*(.literal .text .literal.* .text.*)
+    *libsched.a:spinlock.*(.literal .text .literal.* .text.*)
+
+    *(.wifirxiram .wifirxiram.*)
+    *(.wifi0iram .wifi0iram.*)
+    *(.wifiorslpiram .wifiorslpiram.*)
+    *(.wifislpiram .wifislpiram.*)
+    *(.wifislprxiram .wifislprxiram.*)
+    *(.phyiram .phyiram.*)
+
+    . = ALIGN(4) + 16;
+
+    _iram_text_end = ABSOLUTE(.);
+
+    /* IRAM heap starts at the end of iram0_0_seg */
+
+    . = ALIGN (4);
+    _siramheap = ABSOLUTE(.);
+  } >iram0_0_seg AT>ROM
+
+  /* Shared RAM */
+
+  .noinit (NOLOAD):
+  {
+    /* This section contains data that is not initialized during load,
+     * or during the application's initialization sequence.
+     */
+
+    . = ALIGN(8);
+    *(.noinit)
+    *(.noinit.*)
+    . = ALIGN(8);
+  } >dram0_0_seg
+
+  .dram0.bss (NOLOAD) :
+  {
+    /* .bss initialized on power-up */
+
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    _sbss = ABSOLUTE(.);
+    *(EXCLUDE_FILE(*libble_app.a *libbt.a *libbtdm_app.a *libnimble.a) .bss EXCLUDE_FILE(*libble_app.a *libbt.a *libbtdm_app.a *libnimble.a) .bss.*)
+    *(.ext_ram.bss*)
+    *(EXCLUDE_FILE(*libble_app.a *libbt.a *libbtdm_app.a *libnimble.a) COMMON)
+    . = ALIGN(4);
+    _bt_controller_bss_start = ABSOLUTE(.);
+    *libble_app.a:(.bss .bss.*)
+    . = ALIGN(4);
+    _bt_controller_bss_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _bt_controller_common_start = ABSOLUTE(.);
+    *libble_app.a:(COMMON)
+    . = ALIGN(4);
+    _bt_controller_common_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _bt_bss_start = ABSOLUTE(.);
+    *libbt.a:(.bss .bss.*)
+    . = ALIGN(4);
+    _bt_bss_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _bt_common_start = ABSOLUTE(.);
+    *libbt.a:(COMMON)
+    . = ALIGN(4);
+    _bt_common_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _btdm_bss_start = ABSOLUTE(.);
+    *libbtdm_app.a:(.bss .bss.*)
+    . = ALIGN(4);
+    _btdm_bss_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _btdm_common_start = ABSOLUTE(.);
+    *libbtdm_app.a:(COMMON)
+    . = ALIGN(4);
+    _btdm_common_end = ABSOLUTE(.);
+    . = ALIGN (8);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    KEEP (*(.bss))
+    *(.bss.*)
+    *(.share.mem)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+#ifdef CONFIG_STACK_CANARIES
+    *libc.a:lib_stackchk.*(.bss  .bss.*  COMMON)
+#endif
+    *libarch.a:esp32_spicache.*(.bss  .bss.*  COMMON)
+    *libarch.a:esp32_spiflash.*(.bss  .bss.*  COMMON)
+    *libarch.a:xtensa_cpupause.*(.bss  .bss.*  COMMON)
+    *libarch.a:xtensa_copystate.*(.bss  .bss.*  COMMON)
+    *libarch.a:xtensa_interruptcontext.*(.bss  .bss.*  COMMON)
+    *libarch.a:xtensa_testset.*(.bss  .bss.*  COMMON)
+
+    *libsched.a:sched_suspendscheduler.*(.bss  .bss.*  COMMON)
+    *libsched.a:sched_thistask.*(.bss  .bss.*  COMMON)
+    *libsched.a:sched_note.*(.bss  .bss.*  COMMON)
+    *libsched.a:spinlock.*(.bss  .bss.*  COMMON)
+    *libsched.a:irq_csection.*(.bss  .bss.*  COMMON)
+    *libsched.a:irq_dispatch.*(.bss  .bss.*  COMMON)
+
+    . = ALIGN(8);
+    _ebss = ABSOLUTE(.);
+    _bss_end = ABSOLUTE(.);
+  } >dram0_0_seg
+
+  .dram0.data :
+  {
+    /* .data initialized on power-up in ROMed configurations. */
+
+    _sdata = ABSOLUTE(.);
+    _data_start = ABSOLUTE(.);
+    _bt_data_start = ABSOLUTE(.);
+    *libbt.a:(.data .data.*)
+    . = ALIGN (4);
+    _bt_data_end = ABSOLUTE(.);
+    _btdm_data_start = ABSOLUTE(.);
+    *libbtdm_app.a:(.data .data.*)
+    . = ALIGN (4);
+    _btdm_data_end = ABSOLUTE(.);
+    KEEP (*(.data))
+    KEEP (*(.data.*))
+    KEEP (*(.gnu.linkonce.d.*))
+    KEEP (*(.data1))
+    KEEP (*(.sdata))
+    KEEP (*(.sdata.*))
+    KEEP (*(.gnu.linkonce.s.*))
+    KEEP (*(.sdata2))
+    KEEP (*(.sdata2.*))
+    KEEP (*(.gnu.linkonce.s2.*))
+    KEEP (*(.jcr))
+    *(.dram1 .dram1.*)
+    esp32_start.*(.rodata  .rodata.*)
+    *libphy.a:(.rodata  .rodata.*)
+#ifdef CONFIG_STACK_CANARIES
+    *libc.a:lib_stackchk.*(.rodata  .rodata.*)
+#endif
+    *libarch.a:xtensa_context.*(.rodata  .rodata.*)
+    *libarch.a:xtensa_copystate.*(.rodata  .rodata.*)
+    *libarch.a:xtensa_cpupause.*(.rodata  .rodata.*)
+    *libarch.a:xtensa_testset.*(.rodata  .rodata.*)
+
+    *libdrivers.a:syslog_channel.*(.rodata  .rodata.*)
+
+    *libsched.a:sched_suspendscheduler.*(.rodata  .rodata.*)
+    *libsched.a:sched_thistask.*(.rodata  .rodata.*)
+    *libsched.a:sched_note.*(.rodata  .rodata.*)
+    *libsched.a:spinlock.*(.rodata  .rodata.*)
+    *libsched.a:irq_csection.*(.rodata  .rodata.*)
+    *libsched.a:irq_dispatch.*(.rodata  .rodata.*)
+
+    *libarch.a:esp32_spicache.*(.rodata  .rodata.*)
+    *libarch.a:esp32_spiflash.*(.rodata  .rodata.*)
+    *libarch.a:*esp_loader.*(.rodata .rodata.*)
+    *libarch.a:*brownout.*(.rodata .rodata.*)
+    *libarch.a:*cpu.*(.rodata .rodata.*)
+    *libarch.a:*gpio_hal.*(.rodata .rodata.*)
+    *libarch.a:*periph_ctrl.*(.rodata .rodata.*)
+    *libarch.a:*clk.*(.rodata .rodata.*)
+    *libarch.a:*esp_clk.*(.rodata .rodata.*)
+    *libarch.a:*esp_clk_tree.*(.rodata .rodata.*)
+    *libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*)
+    *libarch.a:*clk_tree_hal.*(.rodata .rodata.*)
+    *libarch.a:*rtc_init.*(.rodata .rodata.*)
+    *libarch.a:*rtc_clk.*(.rodata .rodata.*)
+    *libarch.a:*rtc_clk_init.*(.rodata .rodata.*)
+    *libarch.a:*rtc_time.*(.rodata .rodata.*)
+    *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*)
+    *libarch.a:*uart_hal_iram.*(.rodata .rodata.*)
+    *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_init.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_common.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_common_loader.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_console.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_console_loader.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_esp32.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_flash.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_flash_config_esp32.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_clock_init.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_efuse.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_panic.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_mem.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_random.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_random_esp32.*(.rodata .rodata.*)
+    *libarch.a:*esp_image_format.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_soc.*(.rodata .rodata.*)
+    *libarch.a:*bootloader_sha.*(.rodata .rodata.*)
+    *libarch.a:*uart_hal.*(.rodata .rodata.*)
+    *libarch.a:*mpu_hal.*(.rodata .rodata.*)
+    *libarch.a:*mmu_hal.*(.rodata .rodata.*)
+    *libarch.a:*efuse_hal.*(.rodata .rodata.*)
+    *libarch.a:*uart_periph.*(.rodata .rodata.*)
+    *libarch.a:*esp_rom_uart.*(.rodata .rodata.*)
+    *libarch.a:*esp_rom_sys.*(.rodata .rodata.*)
+    *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*)
+    *libarch.a:*esp_rom_wdt.*(.rodata .rodata.*)
+    *libarch.a:*esp_efuse_fields.*(.rodata .rodata.*)
+    *libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*)
+    *libarch.a:*log.*(.rodata .rodata.*)
+    *libarch.a:*log_noos.*(.rodata .rodata.*)
+    *libarch.a:*cpu_region_protect.*(.rodata .rodata.*)
+    _edata = ABSOLUTE(.);
+    _data_end = ABSOLUTE(.);
+
+    . = ALIGN(4);
+
+    /* Heap starts at the end of .data */
+
+    _sheap = ABSOLUTE(.);
+  } >dram0_0_seg AT>ROM
+
+  _image_drom_vma = ADDR(.flash.rodata);
+  _image_drom_lma = LOADADDR(.flash.rodata);
+  _image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma;
+
+  /* The alignment of the ".flash.rodata" output section is forced to
+   * 0x00010000 (64KB) to ensure that it will be allocated at the beginning
+   * of the next available Flash block.
+   * This is required to meet the following constraint from the external
+   * flash MMU:
+   *    VMA % 64KB == LMA % 64KB
+   * i.e. the lower 16 bits of both the virtual address (address seen by the
+   * CPU) and the load address (physical address of the external flash) must
+   * be equal.
+   */
+
+  .flash.rodata_dummy (NOLOAD) :
+  {
+    . = ALIGN(0x10000);
+  } > ROM
+
+  .flash.rodata :
+  {
+    . = ALIGN(4);
+    _srodata = ABSOLUTE(.);
+    *(EXCLUDE_FILE (*libarch.a:esp32_spiflash.* *libarch.a:esp32_spicache.*
+                    *libarch.a:esp_loader.* esp32_start.*) .rodata)
+    *(EXCLUDE_FILE (*libarch.a:esp32_spiflash.* *libarch.a:esp32_spicache.*
+                    *libarch.a:esp_loader.* esp32_start.*) .rodata.*)
+    *(.srodata.*)
+    *(.rodata)
+    *(.rodata.*)
+#ifdef CONFIG_ESP32_WIRELESS
+    *(.rodata_wlog_verbose.*)
+    *(.rodata_wlog_debug.*)
+    *(.rodata_wlog_info.*)
+    *(.rodata_wlog_warning.*)
+    *(.rodata_wlog_error.*)
+#endif
+    *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gcc_except_table.*)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+
+    . = (. + 3) & ~ 3;
+
+    /* C++ constructor and destructor tables, properly ordered: */
+
+    _sinit = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    _einit = ABSOLUTE(.);
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+
+    /* C++ exception handlers table: */
+
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+
+    /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
+
+    soc_reserved_memory_region_start = ABSOLUTE(.);
+    KEEP (*(.reserved_memory_address))
+    soc_reserved_memory_region_end = ABSOLUTE(.);
+
+    . = ALIGN(4);               /* This table MUST be 4-byte aligned */
+    _erodata = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+  } >default_rodata_seg AT>ROM
+
+  _image_irom_vma = ADDR(.flash.text);
+  _image_irom_lma = LOADADDR(.flash.text);
+  _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma;
+
+  /* The alignment of the ".flash.text" output section is forced to
+   * 0x00010000 (64KB) to ensure that it will be allocated at the beginning
+   * of the next available Flash block.
+   * This is required to meet the following constraint from the external
+   * flash MMU:
+   *    VMA % 64KB == LMA % 64KB
+   * i.e. the lower 16 bits of both the virtual address (address seen by the
+   * CPU) and the load address (physical address of the external flash) must
+   * be equal.
+   */
+
+  .flash.text_dummy (NOLOAD) :
+  {
+    . += SIZEOF(.flash.rodata);
+    . = ALIGN(0x10000);
+  } >default_code_seg AT> ROM
+
+  .flash.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    . = ALIGN(4);
+
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >default_code_seg AT>ROM
+
+  /* External memory bss, from any global variable with EXT_RAM_ATTR attribute */
+
+  .extmem.bss (NOLOAD) :
+  {
+    _sbss_extmem = ABSOLUTE(.);
+    *(.extmem.bss .extmem.bss.*)
+    . = ALIGN(4);
+    _ebss_extmem = ABSOLUTE(.);
+  } >extmem_seg
+
+  .rtc.text :
+  {
+    . = ALIGN(4);
+    *(.rtc.literal .rtc.text)
+  } >rtc_iram_seg AT>ROM
+
+  .rtc.data :
+  {
+    *(.rtc.data)
+    *(.rtc.rodata)
+
+   /* Whatever is left from the RTC memory is used as a special heap. */
+
+    . = ALIGN (4);
+    _srtcheap = ABSOLUTE(.);
+  } >rtc_slow_seg AT>ROM
+}
diff --git a/boards/xtensa/esp32/esp32-2432S028/scripts/Make.defs b/boards/xtensa/esp32/esp32-2432S028/scripts/Make.defs
index 499de88a9b..248d2224b5 100644
--- a/boards/xtensa/esp32/esp32-2432S028/scripts/Make.defs
+++ b/boards/xtensa/esp32/esp32-2432S028/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/esp32-audio-kit/scripts/Make.defs b/boards/xtensa/esp32/esp32-audio-kit/scripts/Make.defs
index 11cc302c5b..4a9390102f 100644
--- a/boards/xtensa/esp32/esp32-audio-kit/scripts/Make.defs
+++ b/boards/xtensa/esp32/esp32-audio-kit/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig
index 56c46e1e19..21d092f172 100644
--- a/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig
+++ b/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig
@@ -26,7 +26,6 @@ CONFIG_DEBUG_ASSERTIONS=y
 CONFIG_DEBUG_FEATURES=y
 CONFIG_DEBUG_FULLOPT=y
 CONFIG_DEBUG_SYMBOLS=y
-CONFIG_ESP32_BOOTLOADER_BUILD_FROM_SOURCE=y
 CONFIG_ESP32_PID=y
 CONFIG_ESP32_UART0=y
 CONFIG_EXPERIMENTAL=y
diff --git a/boards/xtensa/esp32/esp32-devkitc/scripts/Make.defs b/boards/xtensa/esp32/esp32-devkitc/scripts/Make.defs
index f4948996cb..63d4efed6e 100644
--- a/boards/xtensa/esp32/esp32-devkitc/scripts/Make.defs
+++ b/boards/xtensa/esp32/esp32-devkitc/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/Make.defs b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/Make.defs
index fbd3e2ecdb..d3e7388c57 100644
--- a/boards/xtensa/esp32/esp32-ethernet-kit/scripts/Make.defs
+++ b/boards/xtensa/esp32/esp32-ethernet-kit/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/esp32-lyrat/scripts/Make.defs b/boards/xtensa/esp32/esp32-lyrat/scripts/Make.defs
index c2d6f54b65..bec8609932 100644
--- a/boards/xtensa/esp32/esp32-lyrat/scripts/Make.defs
+++ b/boards/xtensa/esp32/esp32-lyrat/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/esp32-pico-kit/scripts/Make.defs b/boards/xtensa/esp32/esp32-pico-kit/scripts/Make.defs
index 93783a01cc..855c037b91 100644
--- a/boards/xtensa/esp32/esp32-pico-kit/scripts/Make.defs
+++ b/boards/xtensa/esp32/esp32-pico-kit/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/scripts/Make.defs b/boards/xtensa/esp32/esp32-sparrow-kit/scripts/Make.defs
index fa7765a3dc..d0bb88c89c 100644
--- a/boards/xtensa/esp32/esp32-sparrow-kit/scripts/Make.defs
+++ b/boards/xtensa/esp32/esp32-sparrow-kit/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/esp32-wrover-kit/scripts/Make.defs b/boards/xtensa/esp32/esp32-wrover-kit/scripts/Make.defs
index 291e6de697..b45db06f8c 100644
--- a/boards/xtensa/esp32/esp32-wrover-kit/scripts/Make.defs
+++ b/boards/xtensa/esp32/esp32-wrover-kit/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/scripts/Make.defs b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/scripts/Make.defs
index b85e6a7196..118e8b4ef9 100644
--- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/scripts/Make.defs
+++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/ttgo_eink5_v2/scripts/Make.defs b/boards/xtensa/esp32/ttgo_eink5_v2/scripts/Make.defs
index 6c81780354..a7324aa8f4 100644
--- a/boards/xtensa/esp32/ttgo_eink5_v2/scripts/Make.defs
+++ b/boards/xtensa/esp32/ttgo_eink5_v2/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/scripts/Make.defs b/boards/xtensa/esp32/ttgo_lora_esp32/scripts/Make.defs
index cac88f8f74..c37b59878b 100644
--- a/boards/xtensa/esp32/ttgo_lora_esp32/scripts/Make.defs
+++ b/boards/xtensa/esp32/ttgo_lora_esp32/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/scripts/Make.defs b/boards/xtensa/esp32/ttgo_t_display_esp32/scripts/Make.defs
index 88fd40c266..c0eb070a05 100644
--- a/boards/xtensa/esp32/ttgo_t_display_esp32/scripts/Make.defs
+++ b/boards/xtensa/esp32/ttgo_t_display_esp32/scripts/Make.defs
@@ -36,6 +36,8 @@ else
 
   ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
     ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
+  else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
+    ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
   else
     ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
   endif
diff --git a/tools/esp32/Config.mk b/tools/esp32/Config.mk
index 2e3e6ee562..f702fcd709 100644
--- a/tools/esp32/Config.mk
+++ b/tools/esp32/Config.mk
@@ -124,6 +124,13 @@ else ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y)
 	IMGTOOL_SIGN_ARGS := --pad $(VERIFIED) $(IMGTOOL_ALIGN_ARGS) -v 0 -s auto \
 		-H $(CONFIG_ESP32_APP_MCUBOOT_HEADER_SIZE) --pad-header \
 		-S $(CONFIG_ESP32_OTA_SLOT_SIZE)
+else
+#   CONFIG_ESPRESSIF_SIMPLE_BOOT
+
+	APP_OFFSET     := 0x1000
+	APP_IMAGE      := nuttx.bin
+	FLASH_APP      := $(APP_OFFSET) $(APP_IMAGE)
+	ESPTOOL_BINDIR := .
 endif
 
 ESPTOOL_BINS += $(FLASH_APP)
@@ -256,6 +263,25 @@ define MKIMAGE
 	$(Q) echo nuttx.bin >> nuttx.manifest
 	$(Q) echo "Generated: nuttx.bin (MCUboot compatible)"
 endef
+else
+define MKIMAGE
+	$(Q) echo "MKIMAGE: ESP32 binary"
+	$(Q) if ! esptool.py version 1>/dev/null 2>&1; then \
+		echo ""; \
+		echo "esptool.py not found.  Please run: \"pip install esptool==4.8.dev4\""; \
+		echo ""; \
+		echo "Run make again to create the nuttx.bin image."; \
+		exit 1; \
+	fi
+	$(Q) if [ -z $(FLASH_SIZE) ]; then \
+		echo "Missing Flash memory size configuration."; \
+		exit 1; \
+	fi
+	$(eval ELF2IMAGE_OPTS := $(if $(CONFIG_ESPRESSIF_SIMPLE_BOOT),--ram-only-header) -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ))
+	esptool.py -c esp32 elf2image $(ELF2IMAGE_OPTS) -o nuttx.bin nuttx
+	$(Q) echo nuttx.bin >> nuttx.manifest
+	$(Q) echo "Generated: nuttx.bin"
+endef
 endif
 endif