include/nuttx/net/w5500.h: Finishes off register bitfield definitions. Driver will follow.
This commit is contained in:
Gregory Nutt
parent
53cefb812b
commit
594734e0ae
@ -1,4 +1,4 @@
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/****************************************************************************
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/************************************************************************************
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* include/nuttx/net/w5500.h
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* WIZnet W5500 Ethernet Controller
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*
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@ -32,14 +32,14 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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************************************************************************************/
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#ifndef __INCLUDE_NUTTX_NET_W5500_H
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#define __INCLUDE_NUTTX_NET_W5500_H
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/****************************************************************************'
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/************************************************************************************'
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* Included Files
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****************************************************************************/
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************************************************************************************/
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#include <nuttx/config.h>
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@ -48,122 +48,242 @@
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#ifdef CONFIG_NET_W5500
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/****************************************************************************'
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/************************************************************************************
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* Included Files
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****************************************************************************/
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************************************************************************************/
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/* W5500 Register Addresses *************************************************/
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/* W5500 Register Addresses *********************************************************/
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/* Common Register Block */
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#define W5500_MR 0x0000 /* Mode */
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#define W5500_GAR0 0x0001 /* Gateway Address */
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#define W5500_GAR1 0x0002
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#define W5500_GAR2 0x0003
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#define W5500_GAR3 0x0004
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#define W5500_SUBR0 0x0005 /* Subnet Mask Address */
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#define W5500_SUBR1 0x0006
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#define W5500_SUBR2 0x0007
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#define W5500_SUBR3 0x0008
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#define W5500_SHAR0 0x0009 /* Source Hardware Address */
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#define W5500_SHAR1 0x000a
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#define W5500_SHAR2 0x000b
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#define W5500_SHAR3 0x000c
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#define W5500_SHAR4 0x000d
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#define W5500_SHAR5 0x000e
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#define W5500_SIPR0 0x000f /* Source IP Address */
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#define W5500_SIPR1 0x0010
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#define W5500_SIPR2 0x0011
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#define W5500_SIPR3 0x0012
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#define W5500_INTLEVEL0 0x0013 /* Interrupt Low Level Timer */
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#define W5500_INTLEVEL1 0x0014
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#define W5500_IR 0x0015 /* Interrupt */
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#define W5500_IMR 0x0016 /* Interrupt Mask */
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#define W5500_SIR 0x0017 /* Socket Interrupt */
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#define W5500_SIMR 0x0018 /* Socket Interrupt Mask */
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#define W5500_RTR0 0x0019 /* Retry Time */
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#define W5500_RTR1 0x001a
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#define W5500_RCR 0x001b /* Retry Count */
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#define W5500_PTIMER 0x001c /* PPP LCP Request Timer */
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#define W5500_PMAGIC 0x001d /* PPP LCP Magic number */
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#define W5500_PHAR0 0x001e /* PPP Destination MAC Address */
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#define W5500_PHAR1 0x001f
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#define W5500_PHAR2 0x0020
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#define W5500_PHAR3 0x0021
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#define W5500_PHAR4 0x0022
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#define W5500_PHAR5 0x0023
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#define W5500_PSID0 0x0024 /* PPP Session Identification */
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#define W5500_PSID1 0x0025
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#define W5500_PMRU0 0x0026 /* PPP Maximum Segment Size */
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#define W5500_PMRU1 0x0027
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#define W5500_UIPR0 0x0028 /* Unreachable IP address */
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#define W5500_UIPR1 0x0029
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#define W5500_UIPR2 0x002a
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#define W5500_UIPR3 0x002b
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#define W5500_UPORTR0 0x002c /* Unreachable Port */
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#define W5500_UPORTR1 0x002d
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#define W5500_PHYCFGR 0x002e /* PHY Configuration */
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/* 0x002f-0x0038: Reserved */
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#define W5500_VERSIONR 0x0039 /* Chip version */
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/* 0x003a-0xffff: Reserved */
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#define W5500_MR 0x0000 /* Mode */
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#define W5500_GAR0 0x0001 /* Gateway Address */
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#define W5500_GAR1 0x0002
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#define W5500_GAR2 0x0003
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#define W5500_GAR3 0x0004
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#define W5500_SUBR0 0x0005 /* Subnet Mask Address */
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#define W5500_SUBR1 0x0006
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#define W5500_SUBR2 0x0007
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#define W5500_SUBR3 0x0008
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#define W5500_SHAR0 0x0009 /* Source Hardware Address */
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#define W5500_SHAR1 0x000a
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#define W5500_SHAR2 0x000b
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#define W5500_SHAR3 0x000c
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#define W5500_SHAR4 0x000d
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#define W5500_SHAR5 0x000e
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#define W5500_SIPR0 0x000f /* Source IP Address */
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#define W5500_SIPR1 0x0010
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#define W5500_SIPR2 0x0011
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#define W5500_SIPR3 0x0012
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#define W5500_INTLEVEL0 0x0013 /* Interrupt Low Level Timer */
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#define W5500_INTLEVEL1 0x0014
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#define W5500_IR 0x0015 /* Interrupt */
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#define W5500_IMR 0x0016 /* Interrupt Mask */
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#define W5500_SIR 0x0017 /* Socket Interrupt */
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#define W5500_SIMR 0x0018 /* Socket Interrupt Mask */
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#define W5500_RTR0 0x0019 /* Retry Time */
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#define W5500_RTR1 0x001a
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#define W5500_RCR 0x001b /* Retry Count */
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#define W5500_PTIMER 0x001c /* PPP LCP Request Timer */
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#define W5500_PMAGIC 0x001d /* PPP LCP Magic number */
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#define W5500_PHAR0 0x001e /* PPP Destination MAC Address */
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#define W5500_PHAR1 0x001f
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#define W5500_PHAR2 0x0020
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#define W5500_PHAR3 0x0021
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#define W5500_PHAR4 0x0022
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#define W5500_PHAR5 0x0023
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#define W5500_PSID0 0x0024 /* PPP Session Identification */
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#define W5500_PSID1 0x0025
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#define W5500_PMRU0 0x0026 /* PPP Maximum Segment Size */
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#define W5500_PMRU1 0x0027
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#define W5500_UIPR0 0x0028 /* Unreachable IP address */
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#define W5500_UIPR1 0x0029
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#define W5500_UIPR2 0x002a
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#define W5500_UIPR3 0x002b
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#define W5500_UPORTR0 0x002c /* Unreachable Port */
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#define W5500_UPORTR1 0x002d
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#define W5500_PHYCFGR 0x002e /* PHY Configuration */
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/* 0x002f-0x0038: Reserved */
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#define W5500_VERSIONR 0x0039 /* Chip version */
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/* 0x003a-0xffff: Reserved */
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/* Socket Register Block */
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#define W5500_SN_MR 0x0000 /* Socket n Mode */
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#define W5500_SN_CR 0x0001 /* Socket n Command */
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#define W5500_SN_IR 0x0002 /* Socket n Interrupt */
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#define W5500_SN_SR 0x0003 /* Socket n Status */
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#define W5500_SN_PORT0 0x0004 /* Socket n Source Port */
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#define W5500_SN_PORT1 0x0005
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#define W5500_SN_DHAR0 0x0006 /* Socket n Destination Hardware Address */
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#define W5500_SN_DHAR1 0x0007
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#define W5500_SN_DHAR2 0x0008
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#define W5500_SN_DHAR3 0x0009
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#define W5500_SN_DHAR4 0x000a
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#define W5500_SN_DHAR5 0x000b
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#define W5500_SN_DIPR0 0x000c /* Socket n Destination IP Address */
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#define W5500_SN_DIPR1 0x000d
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#define W5500_SN_DIPR2 0x000e
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#define W5500_SN_DIPR3 0x000f
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#define W5500_SN_DPORT0 0x0010 /* Socket n Destination Port */
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#define W5500_SN_DPORT1 0x0011
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#define W5500_SN_MSSR0 0x0012 /* Socket n Maximum Segment Size */
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#define W5500_SN_MSSR1 0x0013
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/* 0x0014: Reserved */
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#define W5500_SN_TOS 0x0015 /* Socket n IP TOS */
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#define W5500_SN_TTL 0x0016 /* Socket n IP TTL */
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/* 0x0017-0x001d: Reserved */
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#define W5500_SN_RXBUF_SIZE 0x001e /* Socket n Receive Buffer Size */
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#define W5500_SN_TXBUF_SIZE 0x001f /* Socket n Transmit Buffer Size */
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#define W5500_SN_TX_FSR0 0x0020 /* Socket n TX Free Size */
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#define W5500_SN_TX_FSR1 0x0021
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#define W5500_SN_TX_RD0 0x0022 /* Socket n TX Read Pointer */
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#define W5500_SN_TX_RD1 0x0023
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#define W5500_SN_TX_WR0 0x0024 /* Socket n TX Write Pointer */
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#define W5500_SN_TX_WR1 0x0025
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#define W5500_SN_RX_RSR0 0x0026 /* Socket n RX Received Size */
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#define W5500_SN_RX_RSR1 0x0027
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#define W5500_SN_RX_RD0 0x0028 /* Socket n RX Read Pointer */
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#define W5500_SN_RX_RD1 0x0029
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#define W5500_SN_RX_WR0 0x002a /* Socket n RX Write Pointer */
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#define W5500_SN_RX_WR1 0x002b
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#define W5500_SN_IMR 0x002c /* Socket n Interrupt Mask */
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#define W5500_SN_FRAG0 0x002d /* Socket n Fragment Offset in IP header */
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#define W5500_SN_FRAG1 0x002e
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#define W5500_SN_KPALVTR 0x002f /* Keep alive timer */
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/* 0x0030-0xffff: Reserved */
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#define W5500_SN_MR 0x0000 /* Socket n Mode */
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#define W5500_SN_CR 0x0001 /* Socket n Command */
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#define W5500_SN_IR 0x0002 /* Socket n Interrupt */
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#define W5500_SN_SR 0x0003 /* Socket n Status */
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#define W5500_SN_PORT0 0x0004 /* Socket n Source Port */
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#define W5500_SN_PORT1 0x0005
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#define W5500_SN_DHAR0 0x0006 /* Socket n Destination Hardware Address */
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#define W5500_SN_DHAR1 0x0007
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#define W5500_SN_DHAR2 0x0008
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#define W5500_SN_DHAR3 0x0009
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#define W5500_SN_DHAR4 0x000a
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#define W5500_SN_DHAR5 0x000b
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#define W5500_SN_DIPR0 0x000c /* Socket n Destination IP Address */
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#define W5500_SN_DIPR1 0x000d
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#define W5500_SN_DIPR2 0x000e
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#define W5500_SN_DIPR3 0x000f
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#define W5500_SN_DPORT0 0x0010 /* Socket n Destination Port */
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#define W5500_SN_DPORT1 0x0011
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#define W5500_SN_MSSR0 0x0012 /* Socket n Maximum Segment Size */
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#define W5500_SN_MSSR1 0x0013
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/* 0x0014: Reserved */
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#define W5500_SN_TOS 0x0015 /* Socket n IP TOS */
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#define W5500_SN_TTL 0x0016 /* Socket n IP TTL */
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/* 0x0017-0x001d: Reserved */
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#define W5500_SN_RXBUF_SIZE 0x001e /* Socket n Receive Buffer Size */
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#define W5500_SN_TXBUF_SIZE 0x001f /* Socket n Transmit Buffer Size */
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#define W5500_SN_TX_FSR0 0x0020 /* Socket n TX Free Size */
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#define W5500_SN_TX_FSR1 0x0021
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#define W5500_SN_TX_RD0 0x0022 /* Socket n TX Read Pointer */
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#define W5500_SN_TX_RD1 0x0023
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#define W5500_SN_TX_WR0 0x0024 /* Socket n TX Write Pointer */
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#define W5500_SN_TX_WR1 0x0025
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#define W5500_SN_RX_RSR0 0x0026 /* Socket n RX Received Size */
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#define W5500_SN_RX_RSR1 0x0027
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#define W5500_SN_RX_RD0 0x0028 /* Socket n RX Read Pointer */
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#define W5500_SN_RX_RD1 0x0029
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#define W5500_SN_RX_WR0 0x002a /* Socket n RX Write Pointer */
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#define W5500_SN_RX_WR1 0x002b
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#define W5500_SN_IMR 0x002c /* Socket n Interrupt Mask */
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#define W5500_SN_FRAG0 0x002d /* Socket n Fragment Offset in IP header */
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#define W5500_SN_FRAG1 0x002e
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#define W5500_SN_KPALVTR 0x002f /* Keep alive timer */
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/* 0x0030-0xffff: Reserved */
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/* W5500 Register Bitfield Definitions **************************************/
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/* W5500 Register Bitfield Definitions **********************************************/
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/* Common Register Block */
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/* Mode Register (MR) */
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#define MR_FARP (1 << 1) /* Bit 1: Force ARP */
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#define MR_PPPOE (1 << 3) /* Bit 3: PPPoE Mode */
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#define MR_PB (1 << 4) /* Bit 4: Ping Block Mode */
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#define MR_WOL (1 << 5) /* Bit 5: Wake on LAN */
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#define MR_RST (1 << 7) /* Bit 7: Reset registers */
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/* Interrupt Register (IR), Interrupt Mask Register (IMR) */
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#define INT_MP (1 << 4) /* Bit 4: Magic Packet */
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#define INT_PPPOE (1 << 5) /* Bit 5: PPPoE Connection Close */
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#define INT_UNREACH (1 << 6) /* Bit 6: Destination unreachable */
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#define INT_CONFLICT (1 << 7) /* Bit 7: IP Conflict */
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/* Socket Interrupt Register (SIR) */
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#define SIR(n) (1 << (n))
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/* Socket Interrupt Mask Register (SIMR)) */
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#define SIMR(n) (1 << (n))
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/* PHY Configuration Register (PHYCFGR) */
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#define PHYCFGR_LNK (1 << 0) /* Bit 0: Link Status */
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#define PHYCFGR_SPI (1 << 1 /* Bit 2: Speed Status */
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#define PHYCFGR_DPX (1 << 2) /* Bit 3: Duplex Status */
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#define PHYCFGR_OPMDC_SHIFT (3) /* Bits 3-5: Operation Mode Configuration */
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#define PHYCFGR_OPMDC_MASK (7 << PHYCFGR_OPMDC_SHIFT)
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# define PHYCFGR_OPMDC_10BT_HD_NAN (0 << PHYCFGR_OPMDC_SHIFT) /* 10BT Half-duplex */
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# define PHYCFGR_OPMDC_10BT_HFD_NAN (1 << PHYCFGR_OPMDC_SHIFT) /* 10BT Full-duplex */
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# define PHYCFGR_OPMDC_100BT_HD_NAN (2 << PHYCFGR_OPMDC_SHIFT) /* 100BT Half-duplex */
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# define PHYCFGR_OPMDC_10BT_FD_NAN (3 << PHYCFGR_OPMDC_SHIFT) /* 100BT Full-duplex,
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* Auto-negotiation */
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# define PHYCFGR_OPMDC_100BT_HD_AN (4 << PHYCFGR_OPMDC_SHIFT) /* 100BT Half-duplex,
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* Auto-negotiation */
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# define PHYCFGR_OPMDC_POWER_DOWN (6 << PHYCFGR_OPMDC_SHIFT) /* Power Down mode */
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# define PHYCFGR_OPMDC_ALLCAP_AN (7 << PHYCFGR_OPMDC_SHIFT) /* All capable,
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* Auto-negotiation */
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#define PHYCFGR_OPMD (1 << 6) /* Bit 6: Configure PHY Operation Mode */
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#define PHYCFGR_RST (1 << 7) /* Bit 7: Reset */
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/* Socket Register Block */
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/* Socket n Mode Register (SN_MR) */
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/****************************************************************************'
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#define SN_MR_PROTOCOL_SHIFT (0) /* Bits 0-3: Protocol */
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#define SN_MR_PROTOCOL_MASK (15 << SN_MR_PROTOCOL_SHIFT)
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# define SN_MR_P0 (1 << (SN_MR_PROTOCOL_SHIFT + 0))
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# define SN_MR_P1 (1 << (SN_MR_PROTOCOL_SHIFT + 1))
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# define SN_MR_P2 (1 << (SN_MR_PROTOCOL_SHIFT + 2))
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# define SN_MR_P3 (1 << (SN_MR_PROTOCOL_SHIFT + 3))
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# define SM_MR_CLOSED 0
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# define SM_MR_TCP SN_MR_P0
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# define SM_MR_UDP SN_MR_P1
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# define SM_MR_MACRAW SN_MR_P2
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#define SN_MR_UCASTB (1 << 4) /* Bit 4: UNICAST Blocking in UDP mode */
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#define SN_MR_MIP6B (1 << 4) /* Bit 4: IPv6 packet Blocking in MACRAW mode */
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#define SN_MR_ND (1 << 5) /* Bit 5: Use No Delayed ACK */
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#define SN_MR_MC (1 << 5) /* Bit 5: Multicast */
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#define SN_MR_MMB (1 << 5) /* Bit 5: Multicast Blocking in MACRAW mode */
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#define SN_MR_BCASTB (1 << 6) /* Bit 6: Broadcast Blocking in MACRAW and
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* UDP mode */
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#define SN_MR_MULTI (1 << 7) /* Bit 7: Multicasting in UDP mode */
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#define SN_MR_MFEN (1 << 7) /* Bit 7: MAC Filter Enable in MACRAW mode */
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/* Socket n Command Register (SN_CR) */
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#define SN_CR_OPEN 0x01 /* Socket n is initialized and opened according
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* to the protocol selected in SN_MR */
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#define SN_CR_LISTEN 0x02 /* Socket n operates as a 'TCP server' and waits
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* for connection request from any 'TCP client' */
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#define SN_CR_CONNECT 0x04 /* 'TCP client' connection request */
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#define SN_CR_DISCON 0x08 /* TCP disconnection request */
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#define SN_CR_CLOSE 0x10 /* Close socket n */
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#define SN_CR_SEND 0x20 /* Transmit all data in Socket n TX buffer */
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#define SN_CR_SEND_MAC 0x21 /* Transmit all UDP data (no ARP) */
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#define SN_CR_SEND_KEEP 0x22 /* Send TCP keep-alive packet */
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#define SN_CR_RECV 0x40 /* Complete received data in Socket n RX buffer */
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/* Socket n Interrupt Register (SN_IR) and Socket n Interrupt Mask Register (SN_IMR) */
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#define SN_INT_CON (1 << 0) /* Bit 0: Connection with peer successful */
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#define SN_INT_DISCON (1 << 1) /* Bit 1: FIN or FIN/ACK received from peer */
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#define SN_INT_RECV (1 << 2) /* Bit 2: Data received from peer */
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#define SN_INT_TIMEOUT (1 << 3) /* Bit 3: ARP or TCP timeout */
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#define SN_INT_SEND_OK (1 << 4) /* Bit 4: SEND command completed */
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/* Socket n Status Register (SN_SR) */
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#define SN_SR_SOCK_CLOSED 0x00
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#define SN_SR_SOCK_INIT 0x13
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#define SN_SR_SOCK_LISTEN 0x14
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#define SN_SR_SOCK_ESTABLISHED 0x17
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#define SN_SR_SOCK_CLOSE_WAIT 0x1c
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#define SN_SR_SOCK_UDP 0x22
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#define SN_SR_SOCK_MACRAW 0x42
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#define SN_SR_SOCK_SYNSENT 0x15 /* Transitional status */
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#define SN_SR_SOCK_SYNRECV 0x16
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#define SN_SR_SOCK_FIN_WAIT 0x18
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#define SN_SR_SOCK_CLOSING 0x1a
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#define SN_SR_SOCK_TIME_WAIT 0x1b
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#define SN_SR_SOCK_LAST_ACK 0x1d
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/* Socket n RX Buffer Size Register (SN_RXBUF) */
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#define SN_RXBUF_0KB 0
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#define SN_RXBUF_1KB 1
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#define SN_RXBUF_2KB 2
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#define SN_RXBUF_4KB 4
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#define SN_RXBUF_8KB 5
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#define SN_RXBUF_16KB 16
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/* Socket n TX Buffer Size Register (SN_TXBUF) */
|
||||
|
||||
#define SN_TXBUF_0KB 0
|
||||
#define SN_TXBUF_1KB 1
|
||||
#define SN_TXBUF_2KB 2
|
||||
#define SN_TXBUF_4KB 4
|
||||
#define SN_TXBUF_8KB 5
|
||||
#define SN_TXBUF_16KB 16
|
||||
|
||||
/************************************************************************************'
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
/* This structure describes the lower-half interface provided by board-
|
||||
* specific logic.
|
||||
@ -188,11 +308,11 @@ struct w5500_lower_s
|
||||
void (*reset)(FAR const struct w5500_lower_s *lower, bool reset);
|
||||
};
|
||||
|
||||
/****************************************************************************'
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
/************************************************************************************
|
||||
* Name: w5500_initialize
|
||||
*
|
||||
* Description:
|
||||
@ -206,7 +326,7 @@ struct w5500_lower_s
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
************************************************************************************/
|
||||
|
||||
int w5500_initialize(FAR struct w5500_lower_s *lower);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user