From 5a4bb1714d3426436367214d82e630a9472271bd Mon Sep 17 00:00:00 2001
From: Efim Monjak <monjakefim@yahoo.com>
Date: Fri, 26 Jun 2015 06:52:37 -0600
Subject: [PATCH] In ARMV71-Xplained clock configuration, divider was set to 25
 to get 25*12MHz=300MHz CPU clock.  The correct multiplier is 24 becaue the
 calculatin if (24+1)*12MHz.  So the board was running at 312MHz.  From Efim
 Monjak.

---
 configs/samv71-xult/include/board.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/configs/samv71-xult/include/board.h b/configs/samv71-xult/include/board.h
index f8e7d1cfdb..5b616a464f 100644
--- a/configs/samv71-xult/include/board.h
+++ b/configs/samv71-xult/include/board.h
@@ -82,13 +82,11 @@
  * Yields:
  *
  *   PLLACK = 25 * 12MHz / 1 = 300MHz
- *
- * REVISIT: Isn't the actual multiplier = MUL+1?  Is this being overclocked at 312MHz?
  */
 
 #define BOARD_CKGR_PLLAR_STMODE    PMC_CKGR_PLLAR_STMODE_FAST
 #define BOARD_CKGR_PLLAR_COUNT     (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
-#define BOARD_CKGR_PLLAR_MUL       PMC_CKGR_PLLAR_MUL(25)
+#define BOARD_CKGR_PLLAR_MUL       PMC_CKGR_PLLAR_MUL(24)
 #define BOARD_CKGR_PLLAR_DIV       PMC_CKGR_PLLAR_DIV_BYPASS
 
 /* PMC master clock register settings.