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Adds support for STM32F302K8 and STM32F302K6. From Ben Dyer via PX4/David Sidrane.

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This commit is contained in:
Gregory Nutt 2015-05-08 14:10:55 -06:00
parent 6519dc475d
commit 5a5d044bc5
5 changed files with 73 additions and 17 deletions
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40
arch/arm/include/stm32/chip.h
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@ -1010,10 +1010,50 @@
* Where
* sss = 302/303 or 372/373
* c = C (48pins) R (68 pins) V (100 pins)
* c = K (32 pins), C (48 pins), R (68 pins), V (100 pins)
* f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH)
* f = 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH)
* xxx = Package, temperature range, options (ignored here)
*/
#elif defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */
# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */
# define STM32_NSPI 2 /* (3) SPI1-3 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */
# define STM32_NI2C 3 /* (3) I2C1-3 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 24 /* GPIOA-F */
# define STM32_NADC 1 /* (1) 12-bit ADC1 */
# define STM32_NDAC 1 /* (1) 12-bit DAC1 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */

2
arch/arm/include/stm32/stm32f30xxx_irq.h
View File

@ -144,7 +144,7 @@
#define STM32_IRQ_COMP456 (STM32_IRQ_INTERRUPTS+65) /* 65: COMP4 & COMP5 & COMP6 interrupts, or */
#define STM32_IRQ_EXTI3012 (STM32_IRQ_INTERRUPTS+65) /* 65: EXTI Lines 30, 31 and 32 interrupts */
#define STM32_IRQ_COMP7 (STM32_IRQ_INTERRUPTS+66) /* 66: COMP7 interrupt, or */
#define STM32_IRQ_EXTI35 (STM32_IRQ_INTERRUPTS+66) /* 66: EXTI Line 33 interrupt */
#define STM32_IRQ_EXTI33 (STM32_IRQ_INTERRUPTS+66) /* 66: EXTI Line 33 interrupt */
#define STM32_IRQ_RESERVED67 (STM32_IRQ_INTERRUPTS+67) /* 67: Reserved */
#define STM32_IRQ_RESERVED68 (STM32_IRQ_INTERRUPTS+68) /* 68: Reserved */
#define STM32_IRQ_RESERVED69 (STM32_IRQ_INTERRUPTS+69) /* 69: Reserved */

12
arch/arm/src/stm32/Kconfig
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@ -406,6 +406,18 @@ config ARCH_CHIP_STM32F207ZE
select STM32_STM32F20XX
select STM32_STM32F207
config ARCH_CHIP_STM32F302K6
bool "STM32F302K6"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302K8
bool "STM32F302K8"
select ARCH_CORTEXM4
select STM32_STM32F30XX
select ARCH_HAVE_FPU
config ARCH_CHIP_STM32F302CB
bool "STM32F302CB"
select ARCH_CORTEXM4

12
arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h
View File

@ -70,12 +70,12 @@
/* CAN */
#define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
#define GPIO_CAN_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
#define GPIO_CAN_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_CAN_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1)
#define GPIO_CAN_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
#define GPIO_CAN_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
#define GPIO_CAN_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN0)
#define GPIO_CAN_RX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
#define GPIO_CAN_RX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
#define GPIO_CAN_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN1)
#define GPIO_CAN_TX_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
#define GPIO_CAN_TX_3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_25MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
/* Comparator Outputs */

24
arch/arm/src/stm32/stm32_flash.c
View File

@ -55,9 +55,10 @@
#include "up_arch.h"
/* Only for the STM32F10xx family for now */
/* Only for the STM32F[1|3|4]0xx family for now */
#if defined(CONFIG_STM32_STM32F10XX) || defined (CONFIG_STM32_STM32F40XX)
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined (CONFIG_STM32_STM32F40XX)
/************************************************************************************
* Pre-processor Definitions
@ -66,7 +67,7 @@
#define FLASH_KEY1 0x45670123
#define FLASH_KEY2 0xCDEF89AB
#if defined(CONFIG_STM32_STM32F10XX)
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
#define FLASH_CR_PAGE_ERASE FLASH_CR_PER
#define FLASH_SR_WRITE_PROTECTION_ERROR FLASH_SR_WRPRT_ERR
#elif defined(CONFIG_STM32_STM32F40XX)
@ -103,7 +104,7 @@ void stm32_flash_lock(void)
* Public Functions
************************************************************************************/
#ifdef CONFIG_STM32_STM32F10XX
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
size_t up_progmem_pagesize(size_t page)
{
@ -135,7 +136,7 @@ size_t up_progmem_getaddress(size_t page)
return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE;
}
#endif /* def CONFIG_STM32_STM32F10XX */
#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) */
#ifdef CONFIG_STM32_STM32F40XX
@ -226,9 +227,9 @@ bool up_progmem_isuniform(void)
ssize_t up_progmem_erasepage(size_t page)
{
#ifdef CONFIG_STM32_STM32F10XX
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
size_t page_address;
#endif /* def CONFIG_STM32_STM32F10XX */
#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) */
if (page >= STM32_FLASH_NPAGES)
{
@ -246,10 +247,12 @@ ssize_t up_progmem_erasepage(size_t page)
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE);
#if defined(CONFIG_STM32_STM32F10XX)
/* must be valid - page index checked above */
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
/* Must be valid - page index checked above */
page_address = up_progmem_getaddress(page);
putreg32(page_address, STM32_FLASH_AR);
#elif defined(CONFIG_STM32_STM32F40XX)
modifyreg32(STM32_FLASH_CR, FLASH_CR_SNB_MASK, FLASH_CR_SNB(page));
#endif
@ -363,4 +366,5 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
return written;
}
#endif /* defined(CONFIG_STM32_STM32F10XX) || defined (CONFIG_STM32_STM32F40XX) */
#endif /* defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
defined (CONFIG_STM32_STM32F40XX) */