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Squashed commit of the following:

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arch/arm/src/lpc54xx:  Adds the LPC54-specific clock configuration logic to the leveraged SD/MMC driver.
    arch/arm/src/lpc54xx:  Leveraged SD/MMC driver builds without error but is still missing clock configuration logic.
    arch/arm/src/lpc54xx:  Bring in LPC43xx SD/MMC driver from https://github.com/Smoothieware/smoothie-nuttx/tree/master/nuttx/arch/arm/src/lpc43xx
This commit is contained in:
Gregory Nutt 2017-12-19 12:09:22 -06:00
parent c17651e26e
commit 5a66684293
10 changed files with 2843 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/src/lpc43xx/chip/lpc43_sdmmc.h
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@ -174,7 +174,7 @@
/* Bits 2-31: Reserved */
/* Clock enable register CLKENA */
#define SDMMC_CLKENA_EMABLE (1 << 0) /* Bit 0: Clock enable */
#define SDMMC_CLKENA_ENABLE (1 << 0) /* Bit 0: Clock enable */
/* Bits 1-15: Reserved */
#define SDMMC_CLKENA_LOWPOWER (1 << 16) /* Bit 16: Low-power mode */
/* Bits 17-31: Reserved */

32
arch/arm/src/lpc54xx/Kconfig
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@ -246,6 +246,11 @@ config LPC54_LCD
default n
depends on ARCH_LPC54_HAVE_LCD
config LPC54_SDMMC
bool "SD/MMC"
default n
select ARCH_HAVE_SDIO
config LPC54_SPI0_MASTER
bool "SPI0 Master"
default n
@ -630,6 +635,33 @@ endif # LPC54_EMC_DYNAMIC
endmenu # EMC Configuration
menu "SD/MMC Configuration"
depends on LPC54_SDMMC
config LPC54_SDMMC_DMA
bool "Support DMA data transfers"
default y
select SDIO_SETUP_DMA_BEFORE_WRITE
---help---
Support DMA data transfers.
config LPC54_SDMMC_WIDTH_D1_ONLY
bool "Use D1 only"
default n
---help---
Select 1-bit transfer mode. This may be selected to force the driver
operate with only a single data line (the default is to use all
4 SD data lines).Default: 4-bit transfer mode.
config LPC54_SDMMC_REGDEBUG
bool "Register level debug"
default n
depends on DEBUG_MEMCARD_INFO
---help---
Output detailed register-level SD/MMC debug information.
endmenu # SD/MMC Configuration
menu "LCD Configuration"
depends on LPC54_LCD

5
arch/arm/src/lpc54xx/Make.defs
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@ -120,3 +120,8 @@ endif
ifeq ($(CONFIG_LPC54_LCD),y)
CHIP_CSRCS += lpc54_lcd.c
endif
ifeq ($(CONFIG_LPC54_SDMMC),y)
CHIP_CSRCS += lpc54_sdmmc.c
endif

2
arch/arm/src/lpc54xx/chip/lpc546x_pinmux.h
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@ -628,7 +628,7 @@
#define GPIO_MCLK_4 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN7)
#define GPIO_MCLK_5 (GPIO_ALT3 | GPIO_MODE_DIGITAL | GPIO_PORT2 | GPIO_PIN21)
/* MIcrophone (PDM) */
/* Microphone (PDM) */
#define GPIO_PDM0_CLK_1 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT3 | GPIO_PIN0)
#define GPIO_PDM0_CLK_2 (GPIO_ALT2 | GPIO_MODE_DIGITAL | GPIO_PORT5 | GPIO_PIN8)

9
arch/arm/src/lpc54xx/chip/lpc54_sdmmc.h
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@ -162,7 +162,7 @@
/* Clock enable register CLKENA */
#define SDMMC_CLKENA_EMABLE (1 << 0) /* Bit 0: Clock enable */
#define SDMMC_CLKENA_ENABLE (1 << 0) /* Bit 0: Clock enable */
/* Bits 1-15: Reserved */
#define SDMMC_CLKENA_LOWPOWER (1 << 16) /* Bit 16: Low-power mode */
/* Bits 17-31: Reserved */
@ -208,13 +208,20 @@
#define SDMMC_INT_SDMMC (1 << 16) /* Bit 16: Mask SD/MMC interrupt */
/* Bits 17-31: Reserved */
#define SDMMC_INT_ALL (0x1ffff)
#define SDMMC_INT_RESET (0)
/* Command register CMD */
#define SDMMC_CMD_CMDINDEX_SHIFT (0) /* Bits 0-5: 5:0 Command index */
#define SDMMC_CMD_CMDINDEX_MASK (63 << SDMMC_CMD_CMDINDEX_SHIFT)
#define SDMMC_CMD_RESPONSE (1 << 6) /* Bit 6: Response expected from card */
#define SDMMC_CMD_LONGRESP (1 << 7) /* Bit 7: Long response expected from card */
#define SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 6-7: Response expected */
#define SDMMC_CMD_WAITRESP_MASK (3 << SDMMC_CMD_WAITRESP_SHIFT)
# define SDMMC_CMD_NORESPONSE (0 << SDMMC_CMD_WAITRESP_SHIFT) /* x0: No response */
# define SDMMC_CMD_SHORTRESPONSE (1 << SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */
# define SDMMC_CMD_LONGRESPONSE (3 << SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */
#define SDMMC_CMD_RESPCRC (1 << 8) /* Bit 8: Check response CRC */
#define SDMMC_CMD_DATAXFREXPTD (1 << 9) /* Bit 9: Data transfer expected (read/write) */
#define SDMMC_CMD_WRITE (1 << 10) /* Bit 10: Write to card */

42
arch/arm/src/lpc54xx/chip/lpc54_syscon.h
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@ -564,7 +564,14 @@
# define SYSCON_LCDCLKSEL_NONE (3 << SYSCON_LCDCLKSEL_SHIFT) /* None */
/* SDIO clock source select */
#define SYSCON_SDIOCLKSEL_
#define SYSCON_SDIOCLKSEL_SHIFT (0) /* Bits 0-2: SDIO clock source select */
#define SYSCON_SDIOCLKSEL_MASK (7 << SYSCON_SDIOCLKSEL_SHIFT)
# define SYSCON_SDIOCLKSEL_MAINCLK (0 << SYSCON_SDIOCLKSEL_SHIFT) /* Main clock (main_clk) */
# define SYSCON_SDIOCLKSEL_PLLCLK (1 << SYSCON_SDIOCLKSEL_SHIFT) /* System PLL output (pll_clk) */
# define SYSCON_SDIOCLKSEL_USBPLLCLK (2 << SYSCON_SDIOCLKSEL_SHIFT) /* USB PLL clock (usb_pll_clk) */
# define SYSCON_SDIOCLKSEL_FROHF (3 << SYSCON_SDIOCLKSEL_SHIFT) /* FRO 96 or 48 MHz (fro_hf) */
# define SYSCON_SDIOCLKSEL_AUDIOPLLCLK (4 << SYSCON_SDIOCLKSEL_SHIFT) /* Audio PLL clock (audio_pll_clk) */
/* SYSTICK clock divider */
@ -641,7 +648,13 @@
#define SYSCON_EMCCLKDIV_REQFLAG (1 << 31) /* Bit 31: Divider status flag */
/* SDIO clock divider */
#define SYSCON_SDIOCLKDIV_
#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0) /* Bits 0-7: Clock divider value */
#define SYSCON_SDIOCLKDIV_DIV_MASK (0xff <<SYSCON_SDIOCLKDIV_DIV_SHIFT)
# define SYSCON_SDIOCLKDIV_DIV(n) ((uint32_t)((n)-1) << SYSCON_SDIOCLKDIV_DIV_SHIFT)
#define SYSCON_SDIOCLKDIV_RESET (1 << 29) /* Bit 29: Resets the divider counter */
#define SYSCON_SDIOCLKDIV_HALT (1 << 30) /* Bit 30: Halts the divider counter */
#define SYSCON_SDIOCLKDIV_REQFLAG (1 << 31) /* Bit 31: Divider status flag */
/* Flash wait states configuration */
@ -690,8 +703,31 @@
#define SYSCON_ETHPHYSEL_
/* Ethernet SBD flow control */
#define SYSCON_ETHSBDCTRL_
/* SDIO CCLKIN phase and delay control */
#define SYSCON_SDIOCLKCTRL_
#define SYSCON_SDIOCLKCTRL_DRVPHASE_SHIFT (0) /* Bit 0-1: cclk_in_drv phase */
#define SYSCON_SDIOCLKCTRL_DRVPHASE_MASK (3 << SYSCON_SDIOCLKCTRL_DRVPHASE_SHIFT)
# define SYSCON_SDIOCLKCTRL_DRVPHASE_0 (0 << SYSCON_SDIOCLKCTRL_DRVPHASE_SHIFT) /* 0 degree shift */
# define SYSCON_SDIOCLKCTRL_DRVPHASE_90 (1 << SYSCON_SDIOCLKCTRL_DRVPHASE_SHIFT) /* 90 degree shift */
# define SYSCON_SDIOCLKCTRL_DRVPHASE_180 (2 << SYSCON_SDIOCLKCTRL_DRVPHASE_SHIFT) /* 180 degree shift */
# define SYSCON_SDIOCLKCTRL_DRVPHASE_270 (3 << SYSCON_SDIOCLKCTRL_DRVPHASE_SHIFT) /* 270 degree shift */
#define SYSCON_SDIOCLKCTRL_SMPPHASE_SHIFT (2) /* Bits 2-3: cclk_in_sample delay */
#define SYSCON_SDIOCLKCTRL_SMPPHASE_MASK (3 << SYSCON_SDIOCLKCTRL_SMPPHASE_SHIFT)
# define SYSCON_SDIOCLKCTRL_SMPPHASE_0 (0 << SYSCON_SDIOCLKCTRL_SMPPHASE_SHIFT) /* 0 degree shift */
# define SYSCON_SDIOCLKCTRL_SMPPHASE_90 (1 << SYSCON_SDIOCLKCTRL_SMPPHASE_SHIFT) /* 90 degree shift */
# define SYSCON_SDIOCLKCTRL_SMPPHASE_180 (2 << SYSCON_SDIOCLKCTRL_SMPPHASE_SHIFT) /* 180 degree shift */
# define SYSCON_SDIOCLKCTRL_SMPPHASE_270 (3 << SYSCON_SDIOCLKCTRL_SMPPHASE_SHIFT) /* 270 degree shift */
#define SYSCON_SDIOCLKCTRL_PHASEACTIVE (1 << 7) /* Bit 7: Enables the delays */
#define SYSCON_SDIOCLKCTRL_DRVDLY_SHIFT (16) /* Bits 16-20: cclk_in_drv delay */
#define SYSCON_SDIOCLKCTRL_DRVDLY_MASK (0x1f << SYSCON_SDIOCLKCTRL_DRVDLY_SHIFT)
# define SYSCON_SDIOCLKCTRL_DRVDLY(n) ((uint32_t)((n)-1) << SYSCON_SDIOCLKCTRL_DRVDLY_SHIFT)
#define SYSCON_SDIOCLKCTRL_DRVDLYACTIVE (1 << 23) /* Bit 23: Enables drive delay */
#define SYSCON_SDIOCLKCTRL_SMP_DLY_SHIFT (24) /* Bits 24-28: cclk_in_sample delay */
#define SYSCON_SDIOCLKCTRL_SMP_DLY_MASK (0x1f << SYSCON_SDIOCLKCTRL_SMP_DLY_SHIFT)
# define SYSCON_SDIOCLKCTRL_SMP_DLY(n) ((uint32_t)((n)-1) << SYSCON_SDIOCLKCTRL_SMP_DLY_SHIFT)
#define SYSCON_SDIOCLKCTRL_CCLK_SMPDLYACTIVE (1 << 31) /* Bit 31: Enables sample delay */
/* FRO oscillator control */
#define SYSCON_FROCTRL_
/* System oscillator control */

6
arch/arm/src/lpc54xx/lpc546x_enableclk.h
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@ -107,7 +107,7 @@
#define lpc54_ctimer1_enableclk() lpc54_periph1_enableclk(SYSCON_AHBCLKCTRL1_CTIMER1)
#define lpc54_lcd_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_LCD)
#define lpc54_sdio_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SDIO)
#define lpc54_sdmmc_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_SDIO)
#define lpc54_usb1h_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB1H)
#define lpc54_usb1d_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB1D)
#define lpc54_usb1ram_enableclk() lpc54_periph2_enableclk(SYSCON_AHBCLKCTRL2_USB1RAM)
@ -173,7 +173,7 @@
#define lpc54_ctimer1_disableclk() lpc54_periph1_disableclk(SYSCON_AHBCLKCTRL1_CTIMER1)
#define lpc54_lcd_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_LCD)
#define lpc54_sdio_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SDIO)
#define lpc54_sdmmc_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_SDIO)
#define lpc54_usb1h_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB1H)
#define lpc54_usb1d_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB1D)
#define lpc54_usb1ram_disableclk() lpc54_periph2_disableclk(SYSCON_AHBCLKCTRL2_USB1RAM)
@ -239,7 +239,7 @@
#define lpc54_ctimer1_isenabled() lpc54_periph1_isenabled(SYSCON_AHBCLKCTRL1_CTIMER1)
#define lpc54_lcd_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_LCD)
#define lpc54_sdio_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SDIO)
#define lpc54_sdmmc_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_SDIO)
#define lpc54_usb1h_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB1H)
#define lpc54_usb1d_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB1D)
#define lpc54_usb1ram_isenabled() lpc54_periph2_isenabled(SYSCON_AHBCLKCTRL2_USB1RAM)

2594
arch/arm/src/lpc54xx/lpc54_sdmmc.c Normal file
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File diff suppressed because it is too large Load Diff

127
arch/arm/src/lpc54xx/lpc54_sdmmc.h Normal file
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@ -0,0 +1,127 @@
/************************************************************************************
* arch/arm/src/lpc54xx/lpc54_sdmmc.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC54XX_LPC54_SDMMC_H
#define __ARCH_ARM_SRC_LPC54XX_LPC54_SDMMC_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdbool.h>
#include "chip.h"
#include "chip/lpc54_sdmmc.h"
/************************************************************************************
* Public Functions
************************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: lpc54_sdmmc_initialize
*
* Description:
* Initialize SDIO for operation.
*
* Input Parameters:
* slotno - Not used.
*
* Returned Values:
* A reference to an SDIO interface structure. NULL is returned on failures.
*
****************************************************************************/
struct lpc54_sdmmc_dev_s; /* See include/nuttx/sdio.h */
FAR struct sdio_dev_s *lpc54_sdmmc_initialize(int slotno);
/****************************************************************************
* Name: lpc54_sdmmc_mediachange
*
* Description:
* Called by board-specific logic -- posssible from an interrupt handler --
* in order to signal to the driver that a card has been inserted or
* removed from the slot
*
* Input Parameters:
* dev - An instance of the SDIO driver device state structure.
* cardinslot - true is a card has been detected in the slot; false if a
* card has been removed from the slot. Only transitions
* (inserted->removed or removed->inserted should be reported)
*
* Returned Values:
* None
*
****************************************************************************/
void lpc54_sdmmc_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
/****************************************************************************
* Name: lpc54_sdmmc_wrprotect
*
* Description:
* Called by board-specific logic to report if the card in the slot is
* mechanically write protected.
*
* Input Parameters:
* dev - An instance of the SDIO driver device state structure.
* wrprotect - true is a card is writeprotected.
*
* Returned Values:
* None
*
****************************************************************************/
void lpc54_sdmmc_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_LPC54XX_LPC54_SDMMC_H */

33
configs/lpcxpresso-lpc54628/include/board.h
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@ -141,6 +141,7 @@
*/
/* Revisit: FRGCLK <= 48MHz cannot be realized with the MainClk source */
#define BOARD FRGCLK_CLKSEL SYSCON_FRGCLKSEL_MAINCLK
#define BOARD_FRGCLK_INPUT BOARD_MAIN_CLK /* FRG input frequency */
#define BOARD_FRGCLK 48000000 /* May not be exact */
@ -192,6 +193,15 @@
#endif
#define BOARD_EMC_FREQUENCY (BOARD_CPU_FREQUENCY / BOARD_EMC_CLKDIV)
/* SD/MMC or SDIO interface
*
* NOTE: The SDIO function clock to the interface can be up to 50 MHZ.
*/
#define BOARD_SDMMC_CLKSRC SYSCON_SDIOCLKSEL_MAINCLK
#define BOARD_SDMMC_CLKDIV (BOARD_MAIN_CLK / 50000000)
#define BOARD_SDMMC_FREQUENCY (BOARD_MAIN_CLK / BOARD_SDMMC_CLKDIV)
/* LED definitions *********************************************************/
/* The LPCXpress-LPC54628 has three user LEDs: D9, D11, and D12. These
* LEDs are for application use. They are illuminated when the driving
@ -313,6 +323,29 @@
GPIO_FILTER_OFF | _I2CFILTER | \
_I2CDRIVE)
/* SD/MMC
*
* P2_10-SD_CDn
* P2_6-SD_D0
* P2_7-SD_D1
* P2_8-SD_D2
* P2_9-SD_D3
* P2_3-SD_CLK
* P2_4-SD_CMD
* P2_5-SD_POW_EN
* P3_15-SD_WPn
*/
#define GPIO_SD_CARD_DET_N GPIO_SD_CARD_DET_N_2 /* P2.10 */
#define GPIO_SD_D0 GPIO_SD_D0_3 /* P2.9 */
#define GPIO_SD_D1 GPIO_SD_D1_3 /* P2.7 */
#define GPIO_SD_D2 GPIO_SD_D2_3 /* P2.8 */
#define GPIO_SD_D3 GPIO_SD_D3_3 /* P2.9 */
#define GPIO_SD_CLK GPIO_SD_CLK_3 /* P2.3 */
#define GPIO_SD_CMD GPIO_SD_CMD_3 /* P2.4 */
#define GPIO_SD_POW_EN GPIO_SD_POW_EN_2 /* P2.5 */
#define GPIO_SD_WR_PRT GPIO_SD_WR_PRT_2 /* P2.15 */
/* LCD
*
* There are no alternatives for LCD pins except for the VD0-VD3 pins.