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arch/arm/src/stm32l4/stm32l4_dumpgpio.c: Fix using wrong GPIO enable register.

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This commit is contained in:
Juha Niskanen 2019-09-27 06:30:45 -06:00 committed by Gregory Nutt
parent dc43f4e648
commit 5a73b54dc7
5 changed files with 15 additions and 11 deletions
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5
arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h
View File

@ -390,7 +390,7 @@
/* AHB2 peripheral reset register */
#define RCC_AHB1ENR_GPIOEN(port) (1 << (port))
#define RCC_AHB2RSTR_GPIORST(n) (1 << (n))
#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
@ -467,6 +467,7 @@
/* AHB2 Peripheral Clock enable register */
#define RCC_AHB2ENR_GPIOEN(n) (1 << (n))
#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */
#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */
#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */
@ -522,7 +523,7 @@
/* APB2 Peripheral Clock enable register */
#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: System configuration controller enable */
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
#define RCC_APB2ENR_SDMMCEN (1 << 10) /* Bit 10: SDMMC enable */
#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 enable */
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 enable */

5
arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h
View File

@ -355,7 +355,7 @@
/* AHB2 peripheral reset register */
#define RCC_AHB1ENR_GPIOEN(port) (1 << (port))
#define RCC_AHB2RSTR_GPIORST(n) (1 << (n))
#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
@ -427,6 +427,7 @@
/* AHB2 Peripheral Clock enable register */
#define RCC_AHB2ENR_GPIOEN(n) (1 << (n))
#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */
#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */
#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */
@ -477,7 +478,7 @@
/* APB2 Peripheral Clock enable register */
#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: System configuration controller enable */
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
#define RCC_APB2ENR_SDMMCEN (1 << 10) /* Bit 10: SDMMC enable */
#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 enable */
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 enable */

5
arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h
View File

@ -389,7 +389,7 @@
/* AHB2 peripheral reset register */
#define RCC_AHB1ENR_GPIOEN(port) (1 << (port))
#define RCC_AHB2RSTR_GPIORST(n) (1 << (n))
#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
@ -470,6 +470,7 @@
/* AHB2 Peripheral Clock enable register */
#define RCC_AHB2ENR_GPIOEN(n) (1 << (n))
#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */
#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */
#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */
@ -529,7 +530,7 @@
/* APB2 Peripheral Clock enable register */
#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: System configuration controller enable */
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
#define RCC_APB2ENR_SDMMCEN (1 << 10) /* Bit 10: SDMMC enable */
#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 enable */
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 enable */

5
arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h
View File

@ -419,7 +419,7 @@
/* AHB2 peripheral reset register */
#define RCC_AHB1ENR_GPIOEN(port) (1 << (port))
#define RCC_AHB2RSTR_GPIORST(n) (1 << (n))
#define RCC_AHB2RSTR_GPIOARST (1 << 0) /* Bit 0: IO port A reset */
#define RCC_AHB2RSTR_GPIOBRST (1 << 1) /* Bit 1: IO port B reset */
#define RCC_AHB2RSTR_GPIOCRST (1 << 2) /* Bit 2: IO port C reset */
@ -503,6 +503,7 @@
/* AHB2 Peripheral Clock enable register */
#define RCC_AHB2ENR_GPIOEN(n) (1 << (n))
#define RCC_AHB2ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A enable */
#define RCC_AHB2ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B enable */
#define RCC_AHB2ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C enable */
@ -562,7 +563,7 @@
/* APB2 Peripheral Clock enable register */
#define RCC_APB2ENR_SYSCFGEN (1 << 0) /* Bit 0: System configuration controller enable */
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
#define RCC_APB2ENR_FWEN (1 << 7) /* Bit 7: Firewall enable */
#define RCC_APB2ENR_TIM1EN (1 << 11) /* Bit 11: TIM1 enable */
#define RCC_APB2ENR_SPI1EN (1 << 12) /* Bit 12: SPI1 enable */
#define RCC_APB2ENR_TIM8EN (1 << 13) /* Bit 13: TIM8 enable */

6
arch/arm/src/stm32l4/stm32l4_dumpgpio.c
View File

@ -124,7 +124,7 @@ int stm32l4_dumpgpio(uint32_t pinset, const char *msg)
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32L4_RCC_AHB1ENR) & RCC_AHB1ENR_GPIOEN(port)) != 0)
if ((getreg32(STM32L4_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0)
{
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32L4_GPIO_MODER_OFFSET),
@ -142,8 +142,8 @@ int stm32l4_dumpgpio(uint32_t pinset, const char *msg)
}
else
{
_info(" GPIO%c not enabled: AHB1ENR: %08x\n",
g_portchar[port], getreg32(STM32L4_RCC_AHB1ENR));
_info(" GPIO%c not enabled: AHB2ENR: %08x\n",
g_portchar[port], getreg32(STM32L4_RCC_AHB2ENR));
}
leave_critical_section(flags);