Complete some missing logic for STM32 F3 DMA
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5634 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f10xxx_dma.h
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*
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* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -275,6 +275,10 @@
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* sources/sinks of data. The requests from peripherals assigned to a channel
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* are simply OR'ed together before entering the DMA block. This means that only
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* one request on a given channel can be enabled at once.
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*
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* Alternative DMA channel selections are provided with a numeric suffix like _1,
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* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
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* Additional definitions are required in the board.h file.
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*/
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#define STM32_DMA1_CHAN1 (0)
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@ -291,68 +295,171 @@
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#define STM32_DMA2_CHAN4 (10)
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#define STM32_DMA2_CHAN5 (11)
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#define DMACHAN_ADC1 STM32_DMA1_CHAN1
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#define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
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#define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
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#define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
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#define DMACHAN_USART3_TX STM32_DMA1_CHAN2
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#define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
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#define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
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#define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
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#define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
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#define DMACHAN_USART3_RX STM32_DMA1_CHAN3
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#define DMACHAN_TIM1_CH2 STM32_DMA1_CHAN3
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#define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
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#define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
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#define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
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#define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
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#define DMACHAN_USART1_TX STM32_DMA1_CHAN4
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#define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
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#define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
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#define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
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#define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
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#define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
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#define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
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#define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
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#define DMACHAN_USART1_RX STM32_DMA1_CHAN5
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#define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
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#define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
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#define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
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#define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
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#define DMACHAN_USART2_RX STM32_DMA1_CHAN6
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#define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
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#define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
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#define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
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#define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
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#define DMACHAN_USART2_TX STM32_DMA1_CHAN7
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#define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
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#define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
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#define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
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#define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
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#define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
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#define DMACHAN_I2S3_RX STM32_DMA2_CHAN1
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#define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1
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#define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1
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#define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1
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#define DMACHAN_TIM8_UP STM32_DMA2_CHAN1
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#define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
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#define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
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#define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2
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#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
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#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
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#define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
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#define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
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#define DMACHAN_UART4_RX STM32_DMA2_CHAN3
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#define DMACHAN_TIM6_UP STM32_DMA2_CHAN3
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#define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3
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#define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3
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#define DMACHAN_SDIO STM32_DMA2_CHAN4
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#define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4
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#define DMACHAN_TIM7_UP STM32_DMA2_CHAN4
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#define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4
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#define DMACHAN_ADC3 STM32_DMA2_CHAN5
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#define DMACHAN_UART4_TX STM32_DMA2_CHAN5
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#define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5
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#define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
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#if defined(CONFIG_STM32_STM32F10XX)
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# define DMACHAN_ADC1 STM32_DMA1_CHAN1
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# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
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# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
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# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
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# define DMACHAN_USART3_TX STM32_DMA1_CHAN2
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# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
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# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
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# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
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# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
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# define DMACHAN_USART3_RX STM32_DMA1_CHAN3
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# define DMACHAN_TIM1_CH2 STM32_DMA1_CHAN3
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# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
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# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
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# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
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# define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
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# define DMACHAN_USART1_TX STM32_DMA1_CHAN4
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# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
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# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
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# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
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# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
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# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
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# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
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# define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
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# define DMACHAN_USART1_RX STM32_DMA1_CHAN5
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# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
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# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
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# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
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# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
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# define DMACHAN_USART2_RX STM32_DMA1_CHAN6
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# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
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# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
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# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
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# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
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# define DMACHAN_USART2_TX STM32_DMA1_CHAN7
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# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
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# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
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# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
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# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
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# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
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# define DMACHAN_I2S3_RX STM32_DMA2_CHAN1
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# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1
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# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1
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# define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1
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# define DMACHAN_TIM8_UP STM32_DMA2_CHAN1
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# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
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# define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
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# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2
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# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
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# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
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# define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
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# define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
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# define DMACHAN_UART4_RX STM32_DMA2_CHAN3
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# define DMACHAN_TIM6_UP STM32_DMA2_CHAN3
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# define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3
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# define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3
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# define DMACHAN_SDIO STM32_DMA2_CHAN4
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# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4
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# define DMACHAN_TIM7_UP STM32_DMA2_CHAN4
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# define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4
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# define DMACHAN_ADC3 STM32_DMA2_CHAN5
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# define DMACHAN_UART4_TX STM32_DMA2_CHAN5
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# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5
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# define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
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#elif defined(CONFIG_STM32_STM32F30XX)
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# define DMACHAN_ADC1 STM32_DMA1_CHAN1
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# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
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# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
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# define DMACHAN_TIM17_CH1 STM32_DMA1_CHAN1
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# define DMACHAN_TIM17_UP STM32_DMA1_CHAN1
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# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
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# define DMACHAN_USART3_TX STM32_DMA1_CHAN2
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# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
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# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
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# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
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# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
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# define DMACHAN_USART3_RX STM32_DMA1_CHAN3
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# define DMACHAN_TIM1_CH2_1 STM32_DMA1_CHAN3
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# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
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# define DMACHAN_TIM3_UP_2 STM32_DMA1_CHAN3
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# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
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# define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
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# define DMACHAN_USART1_TX STM32_DMA1_CHAN4
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# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
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# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
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# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
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# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
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# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
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# define DMACHAN_TIM7_UP_1 STM32_DMA1_CHAN4
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# define DMACHAN_DAC_CH2 STM32_DMA1_CHAN4
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# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
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# define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
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# define DMACHAN_USART1_RX STM32_DMA1_CHAN5
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# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
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# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
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# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
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# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
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# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5
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# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5
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# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5
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# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5
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# define DMACHAN_USART2_RX STM32_DMA1_CHAN6
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# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
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# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
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# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
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# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
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# define DMACHAN_TIM16_CH1 STM32_DMA1_CHAN6
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# define DMACHAN_TIM16_UP STM32_DMA1_CHAN6
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# define DMACHAN_USART2_TX STM32_DMA1_CHAN7
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# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
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# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
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# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
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# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
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# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7
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# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7
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# define DMACHAN_ADC2_1 STM32_DMA2_CHAN1
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# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
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# define DMACHAN_I2S3_RX STM32_DMA2_CHAN1
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# define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1
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# define DMACHAN_TIM8_UP STM32_DMA2_CHAN1
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# define DMACHAN_ADC4_1 STM32_DMA2_CHAN2
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# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
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# define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
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# define DMACHAN_TIM8_CH4 STM32_DMA2_CHAN2
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# define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
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# define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
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# define DMACHAN_ADC2_2 STM32_DMA2_CHAN3
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# define DMACHAN_UART4_RX STM32_DMA2_CHAN3
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# define DMACHAN_TIM6_UP STM32_DMA2_CHAN3
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# define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3
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# define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3
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# define DMACHAN_ADC4_2 STM32_DMA2_CHAN4
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# define DMACHAN_TIM7_UP_2 STM32_DMA2_CHAN4
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# define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4
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# define DMACHAN_ADC3 STM32_DMA2_CHAN5
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# define DMACHAN_UART4_TX STM32_DMA2_CHAN5
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# define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
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#else
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# error "Unknown DMA channel assignments"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H */
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/stm32_dma.h
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*
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* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -61,7 +61,7 @@
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* DMA callback function (see dma_callback_t).
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*/
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#if defined(CONFIG_STM32_STM32F10XX)
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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# define DMA_STATUS_FEIF 0 /* (Not available in F1) */
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# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
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# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
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@ -103,7 +103,7 @@ typedef FAR void *DMA_HANDLE;
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typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
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#ifdef CONFIG_DEBUG_DMA
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#if defined(CONFIG_STM32_STM32F10XX)
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#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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struct stm32_dmaregs_s
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{
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uint32_t isr;
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# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)"
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# endif
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# elif defined(CONFIG_STM32_STM32F10XX)
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# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \
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defined(CONFIG_USART3_RXDMA)
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/* DMA priority */
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# ifndef CONFIG_USART_DMAPRIO
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# if defined(CONFIG_STM32_STM32F10XX)
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# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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# define CONFIG_USART_DMAPRIO DMA_CCR_PRIMED
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# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
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# define CONFIG_USART_DMAPRIO DMA_SCR_PRIMED
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# error "Unknown STM32 DMA"
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# endif
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# endif
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# if defined(CONFIG_STM32_STM32F10XX)
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# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
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# if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
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# error "Illegal value for CONFIG_USART_DMAPRIO"
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# endif
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