Complete some missing logic for STM32 F3 DMA
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5634 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
ad447766ff
commit
5abde71611
@ -1,7 +1,7 @@
|
|||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* arch/arm/src/stm32/chip/stm32f10xxx_dma.h
|
* arch/arm/src/stm32/chip/stm32f10xxx_dma.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@ -275,6 +275,10 @@
|
|||||||
* sources/sinks of data. The requests from peripherals assigned to a channel
|
* sources/sinks of data. The requests from peripherals assigned to a channel
|
||||||
* are simply OR'ed together before entering the DMA block. This means that only
|
* are simply OR'ed together before entering the DMA block. This means that only
|
||||||
* one request on a given channel can be enabled at once.
|
* one request on a given channel can be enabled at once.
|
||||||
|
*
|
||||||
|
* Alternative DMA channel selections are provided with a numeric suffix like _1,
|
||||||
|
* _2, etc. Drivers, however, will use the pin selection without the numeric suffix.
|
||||||
|
* Additional definitions are required in the board.h file.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define STM32_DMA1_CHAN1 (0)
|
#define STM32_DMA1_CHAN1 (0)
|
||||||
@ -291,68 +295,171 @@
|
|||||||
#define STM32_DMA2_CHAN4 (10)
|
#define STM32_DMA2_CHAN4 (10)
|
||||||
#define STM32_DMA2_CHAN5 (11)
|
#define STM32_DMA2_CHAN5 (11)
|
||||||
|
|
||||||
#define DMACHAN_ADC1 STM32_DMA1_CHAN1
|
#if defined(CONFIG_STM32_STM32F10XX)
|
||||||
#define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
|
|
||||||
#define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
|
# define DMACHAN_ADC1 STM32_DMA1_CHAN1
|
||||||
#define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
|
# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
|
||||||
#define DMACHAN_USART3_TX STM32_DMA1_CHAN2
|
# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
|
||||||
#define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
|
|
||||||
#define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
|
# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
|
||||||
#define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
|
# define DMACHAN_USART3_TX STM32_DMA1_CHAN2
|
||||||
#define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
|
# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
|
||||||
#define DMACHAN_USART3_RX STM32_DMA1_CHAN3
|
# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
|
||||||
#define DMACHAN_TIM1_CH2 STM32_DMA1_CHAN3
|
# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
|
||||||
#define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
|
|
||||||
#define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
|
# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
|
||||||
#define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
|
# define DMACHAN_USART3_RX STM32_DMA1_CHAN3
|
||||||
#define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
|
# define DMACHAN_TIM1_CH2 STM32_DMA1_CHAN3
|
||||||
#define DMACHAN_USART1_TX STM32_DMA1_CHAN4
|
# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
|
||||||
#define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
|
# define DMACHAN_TIM3_UP STM32_DMA1_CHAN3
|
||||||
#define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
|
|
||||||
#define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
|
# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
|
||||||
#define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
|
# define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
|
||||||
#define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
|
# define DMACHAN_USART1_TX STM32_DMA1_CHAN4
|
||||||
#define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
|
# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
|
||||||
#define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
|
# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
|
||||||
#define DMACHAN_USART1_RX STM32_DMA1_CHAN5
|
# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
|
||||||
#define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
|
# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
|
||||||
#define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
|
# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
|
||||||
#define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
|
|
||||||
#define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
|
# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
|
||||||
#define DMACHAN_USART2_RX STM32_DMA1_CHAN6
|
# define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
|
||||||
#define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
|
# define DMACHAN_USART1_RX STM32_DMA1_CHAN5
|
||||||
#define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
|
# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
|
||||||
#define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
|
# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
|
||||||
#define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
|
# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
|
||||||
#define DMACHAN_USART2_TX STM32_DMA1_CHAN7
|
# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
|
||||||
#define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
|
|
||||||
#define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
|
# define DMACHAN_USART2_RX STM32_DMA1_CHAN6
|
||||||
#define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
|
# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
|
||||||
#define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
|
# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
|
||||||
#define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
|
# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
|
||||||
#define DMACHAN_I2S3_RX STM32_DMA2_CHAN1
|
# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
|
||||||
#define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1
|
|
||||||
#define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1
|
# define DMACHAN_USART2_TX STM32_DMA1_CHAN7
|
||||||
#define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1
|
# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
|
||||||
#define DMACHAN_TIM8_UP STM32_DMA2_CHAN1
|
# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
|
||||||
#define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
|
# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
|
||||||
#define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
|
# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
|
||||||
#define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2
|
|
||||||
#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
|
# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
|
||||||
#define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
|
# define DMACHAN_I2S3_RX STM32_DMA2_CHAN1
|
||||||
#define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
|
# define DMACHAN_TIM5_CH4 STM32_DMA2_CHAN1
|
||||||
#define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
|
# define DMACHAN_TIM5_TRIG STM32_DMA2_CHAN1
|
||||||
#define DMACHAN_UART4_RX STM32_DMA2_CHAN3
|
# define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1
|
||||||
#define DMACHAN_TIM6_UP STM32_DMA2_CHAN3
|
# define DMACHAN_TIM8_UP STM32_DMA2_CHAN1
|
||||||
#define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3
|
|
||||||
#define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3
|
# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
|
||||||
#define DMACHAN_SDIO STM32_DMA2_CHAN4
|
# define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
|
||||||
#define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4
|
# define DMACHAN_TIM5_CH3 STM32_DMA2_CHAN2
|
||||||
#define DMACHAN_TIM7_UP STM32_DMA2_CHAN4
|
# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
|
||||||
#define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4
|
# define DMACHAN_TIM5_UP STM32_DMA2_CHAN2
|
||||||
#define DMACHAN_ADC3 STM32_DMA2_CHAN5
|
# define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
|
||||||
#define DMACHAN_UART4_TX STM32_DMA2_CHAN5
|
# define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
|
||||||
#define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5
|
|
||||||
#define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
|
# define DMACHAN_UART4_RX STM32_DMA2_CHAN3
|
||||||
|
# define DMACHAN_TIM6_UP STM32_DMA2_CHAN3
|
||||||
|
# define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3
|
||||||
|
# define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3
|
||||||
|
|
||||||
|
# define DMACHAN_SDIO STM32_DMA2_CHAN4
|
||||||
|
# define DMACHAN_TIM5_CH2 STM32_DMA2_CHAN4
|
||||||
|
# define DMACHAN_TIM7_UP STM32_DMA2_CHAN4
|
||||||
|
# define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4
|
||||||
|
|
||||||
|
# define DMACHAN_ADC3 STM32_DMA2_CHAN5
|
||||||
|
# define DMACHAN_UART4_TX STM32_DMA2_CHAN5
|
||||||
|
# define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5
|
||||||
|
# define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
|
||||||
|
|
||||||
|
#elif defined(CONFIG_STM32_STM32F30XX)
|
||||||
|
|
||||||
|
# define DMACHAN_ADC1 STM32_DMA1_CHAN1
|
||||||
|
# define DMACHAN_TIM2_CH3 STM32_DMA1_CHAN1
|
||||||
|
# define DMACHAN_TIM4_CH1 STM32_DMA1_CHAN1
|
||||||
|
# define DMACHAN_TIM17_CH1 STM32_DMA1_CHAN1
|
||||||
|
# define DMACHAN_TIM17_UP STM32_DMA1_CHAN1
|
||||||
|
|
||||||
|
# define DMACHAN_SPI1_RX STM32_DMA1_CHAN2
|
||||||
|
# define DMACHAN_USART3_TX STM32_DMA1_CHAN2
|
||||||
|
# define DMACHAN_TIM1_CH1 STM32_DMA1_CHAN2
|
||||||
|
# define DMACHAN_TIM2_UP STM32_DMA1_CHAN2
|
||||||
|
# define DMACHAN_TIM3_CH3 STM32_DMA1_CHAN2
|
||||||
|
|
||||||
|
# define DMACHAN_SPI1_TX STM32_DMA1_CHAN3
|
||||||
|
# define DMACHAN_USART3_RX STM32_DMA1_CHAN3
|
||||||
|
# define DMACHAN_TIM1_CH2_1 STM32_DMA1_CHAN3
|
||||||
|
# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
|
||||||
|
# define DMACHAN_TIM3_UP_2 STM32_DMA1_CHAN3
|
||||||
|
|
||||||
|
# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
|
||||||
|
# define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
|
||||||
|
# define DMACHAN_USART1_TX STM32_DMA1_CHAN4
|
||||||
|
# define DMACHAN_I2C2_TX STM32_DMA1_CHAN4
|
||||||
|
# define DMACHAN_TIM1_CH4 STM32_DMA1_CHAN4
|
||||||
|
# define DMACHAN_TIM1_TRIG STM32_DMA1_CHAN4
|
||||||
|
# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
|
||||||
|
# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
|
||||||
|
# define DMACHAN_TIM7_UP_1 STM32_DMA1_CHAN4
|
||||||
|
# define DMACHAN_DAC_CH2 STM32_DMA1_CHAN4
|
||||||
|
|
||||||
|
# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_USART1_RX STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_I2C2_RX STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_TIM1_UP STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_TIM2_CH1 STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_TIM4_CH3 STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_TIM15_CH1 STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5
|
||||||
|
# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5
|
||||||
|
|
||||||
|
# define DMACHAN_USART2_RX STM32_DMA1_CHAN6
|
||||||
|
# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6
|
||||||
|
# define DMACHAN_TIM1_CH3 STM32_DMA1_CHAN6
|
||||||
|
# define DMACHAN_TIM3_CH1 STM32_DMA1_CHAN6
|
||||||
|
# define DMACHAN_TIM3_TRIG STM32_DMA1_CHAN6
|
||||||
|
# define DMACHAN_TIM16_CH1 STM32_DMA1_CHAN6
|
||||||
|
# define DMACHAN_TIM16_UP STM32_DMA1_CHAN6
|
||||||
|
|
||||||
|
# define DMACHAN_USART2_TX STM32_DMA1_CHAN7
|
||||||
|
# define DMACHAN_I2C1_RX STM32_DMA1_CHAN7
|
||||||
|
# define DMACHAN_TIM2_CH2 STM32_DMA1_CHAN7
|
||||||
|
# define DMACHAN_TIM2_CH4 STM32_DMA1_CHAN7
|
||||||
|
# define DMACHAN_TIM4_UP STM32_DMA1_CHAN7
|
||||||
|
# define DMACHAN_TIM17_CH1_2 STM32_DMA1_CHAN7
|
||||||
|
# define DMACHAN_TIM17_UP_2 STM32_DMA1_CHAN7
|
||||||
|
|
||||||
|
# define DMACHAN_ADC2_1 STM32_DMA2_CHAN1
|
||||||
|
# define DMACHAN_SPI3_RX STM32_DMA2_CHAN1
|
||||||
|
# define DMACHAN_I2S3_RX STM32_DMA2_CHAN1
|
||||||
|
# define DMACHAN_TIM8_CH3 STM32_DMA2_CHAN1
|
||||||
|
# define DMACHAN_TIM8_UP STM32_DMA2_CHAN1
|
||||||
|
|
||||||
|
# define DMACHAN_ADC4_1 STM32_DMA2_CHAN2
|
||||||
|
# define DMACHAN_SPI3_TX STM32_DMA2_CHAN2
|
||||||
|
# define DMACHAN_I2S3_TX STM32_DMA2_CHAN2
|
||||||
|
# define DMACHAN_TIM8_CH4 STM32_DMA2_CHAN2
|
||||||
|
# define DMACHAN_TIM8_TRIG STM32_DMA2_CHAN2
|
||||||
|
# define DMACHAN_TIM8_COM STM32_DMA2_CHAN2
|
||||||
|
|
||||||
|
# define DMACHAN_ADC2_2 STM32_DMA2_CHAN3
|
||||||
|
# define DMACHAN_UART4_RX STM32_DMA2_CHAN3
|
||||||
|
# define DMACHAN_TIM6_UP STM32_DMA2_CHAN3
|
||||||
|
# define DMACHAN_DAC_CHAN1 STM32_DMA2_CHAN3
|
||||||
|
# define DMACHAN_TIM8_CH1 STM32_DMA2_CHAN3
|
||||||
|
|
||||||
|
# define DMACHAN_ADC4_2 STM32_DMA2_CHAN4
|
||||||
|
# define DMACHAN_TIM7_UP_2 STM32_DMA2_CHAN4
|
||||||
|
# define DMACHAN_DAC_CHAN2 STM32_DMA2_CHAN4
|
||||||
|
|
||||||
|
# define DMACHAN_ADC3 STM32_DMA2_CHAN5
|
||||||
|
# define DMACHAN_UART4_TX STM32_DMA2_CHAN5
|
||||||
|
# define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
|
||||||
|
|
||||||
|
#else
|
||||||
|
# error "Unknown DMA channel assignments"
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H */
|
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H */
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* arch/arm/src/stm32/stm32_dma.h
|
* arch/arm/src/stm32/stm32_dma.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@ -61,7 +61,7 @@
|
|||||||
* DMA callback function (see dma_callback_t).
|
* DMA callback function (see dma_callback_t).
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(CONFIG_STM32_STM32F10XX)
|
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||||
# define DMA_STATUS_FEIF 0 /* (Not available in F1) */
|
# define DMA_STATUS_FEIF 0 /* (Not available in F1) */
|
||||||
# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
|
# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
|
||||||
# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
|
# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
|
||||||
@ -103,7 +103,7 @@ typedef FAR void *DMA_HANDLE;
|
|||||||
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
|
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
|
||||||
|
|
||||||
#ifdef CONFIG_DEBUG_DMA
|
#ifdef CONFIG_DEBUG_DMA
|
||||||
#if defined(CONFIG_STM32_STM32F10XX)
|
#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||||
struct stm32_dmaregs_s
|
struct stm32_dmaregs_s
|
||||||
{
|
{
|
||||||
uint32_t isr;
|
uint32_t isr;
|
||||||
|
|||||||
@ -138,7 +138,7 @@
|
|||||||
# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)"
|
# error "USART6 DMA channel not defined (DMAMAP_USART6_RX)"
|
||||||
# endif
|
# endif
|
||||||
|
|
||||||
# elif defined(CONFIG_STM32_STM32F10XX)
|
# elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||||
|
|
||||||
# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \
|
# if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \
|
||||||
defined(CONFIG_USART3_RXDMA)
|
defined(CONFIG_USART3_RXDMA)
|
||||||
@ -173,7 +173,7 @@
|
|||||||
/* DMA priority */
|
/* DMA priority */
|
||||||
|
|
||||||
# ifndef CONFIG_USART_DMAPRIO
|
# ifndef CONFIG_USART_DMAPRIO
|
||||||
# if defined(CONFIG_STM32_STM32F10XX)
|
# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||||
# define CONFIG_USART_DMAPRIO DMA_CCR_PRIMED
|
# define CONFIG_USART_DMAPRIO DMA_CCR_PRIMED
|
||||||
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
|
||||||
# define CONFIG_USART_DMAPRIO DMA_SCR_PRIMED
|
# define CONFIG_USART_DMAPRIO DMA_SCR_PRIMED
|
||||||
@ -181,7 +181,7 @@
|
|||||||
# error "Unknown STM32 DMA"
|
# error "Unknown STM32 DMA"
|
||||||
# endif
|
# endif
|
||||||
# endif
|
# endif
|
||||||
# if defined(CONFIG_STM32_STM32F10XX)
|
# if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
|
||||||
# if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
|
# if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
|
||||||
# error "Illegal value for CONFIG_USART_DMAPRIO"
|
# error "Illegal value for CONFIG_USART_DMAPRIO"
|
||||||
# endif
|
# endif
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user