sergiotarxz/nuttx
sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Misc updates to STL32L15X logic

Browse Source
This commit is contained in:
Gregory Nutt 2013-05-20 10:08:44 -06:00
parent 5b86207177
commit 5ad97e995c
6 changed files with 143 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/src/stm32/chip/stm32l15xxx_rcc.h
View File

@ -111,6 +111,8 @@
#define RCC_ICSCR_MSITRIM_SHIFT (24) /* Bits 24-31: MSI clock trimming */
#define RCC_ICSCR_MSITRIM_MASK (0xff << RCC_ICSCR_MSITRIM_SHIFT)
#define RCC_ICSR_RSTVAL 0x0000b000
/* Clock configuration register */
#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */
@ -188,6 +190,8 @@
# define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) /* 011: MCO is divided by 8 */
# define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) /* 100: MCO is divided by 16 */
/* Bit 31: Reserved */
#define RCC_CFGR_RESET 0x00000000
/* Clock interrupt register */
#define RCC_CIR_LSIRDYF (1 << 0) /* Bit 0: LSI ready interrupt flag */
@ -286,6 +290,7 @@
/* AHB Peripheral Clock enable register */
#define RCC_AHBENR_GPIOEN(n) (1 << (n))
#define RCC_AHBENR_GPIOPAEN (1 << 0) /* Bit 0: I/O port A clock enable */
#define RCC_AHBENR_GPIOPBEN (1 << 1) /* Bit 1: I/O port B clock enable */
#define RCC_AHBENR_GPIOPCEN (1 << 2) /* Bit 2: I/O port C clock enable */

31
arch/arm/src/stm32/stm32_dumpgpio.c
View File

@ -147,7 +147,36 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
g_portchar[port], getreg32(STM32_RCC_APB2ENR));
}
#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F30XX)
#elif defined(CONFIG_STM32_STM32L15XX)
DEBUGASSERT(port < STM32_NGPIO_PORTS);
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_AHBENR) & RCC_AHBENR_GPIOEN(port)) != 0)
{
lldbg(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
lldbg(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
lldbg(" AFRH: %08x AFRL: %08x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET));
}
else
{
lldbg(" GPIO%c not enabled: AHBENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_AHBENR));
}
#elif defined(CONFIG_STM32_STM32F30XX)
DEBUGASSERT(port < STM32_NGPIO_PORTS);

78
arch/arm/src/stm32/stm32l15xxx_rcc.c
View File

@ -69,34 +69,83 @@ static inline void rcc_reset(void)
{
uint32_t regval;
/* Make sure that all devices are out of reset */
putreg32(0, STM32_RCC_AHBRSTR); /* Disable AHB Peripheral Reset */
putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
/* Disable all clocking (other than to FLASH) */
putreg32(RCC_AHBENR_FLITFEN, STM32_RCC_AHBENR); /* FLITF Clock ON */
putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
regval = getreg32(STM32_RCC_CR); /* Enable the HSI */
regval |= RCC_CR_HSION;
/* Set the Internal clock sources calibration register to its reset value.
* MSI to the default frequency (nomially 2.097MHz), MSITRIM=0, HSITRIM=0x10 */
putreg32(RCC_ICSR_RSTVAL, STM32_RCC_ICSCR);
/* Enable the internal MSI */
regval = getreg32(STM32_RCC_CR); /* Enable the MSI */
regval |= RCC_CR_MSION;
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CFGR); /* Reset SW, HPRE, PPRE1, PPRE2, and MCO bits */
/* Set the CFGR register to its reset value: Reset SW, HPRE, PPRE1, PPRE2,
* and MCO bits. Resetting SW selects the MSI clock as the system clock
* source. We do not clear PLL values yet because the PLL may be providing
* the SYSCLK and we want the PLL to be stable through the transition.
*/
regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
RCC_CFGR_PPRE2_MASK | RCC_CFGR_MCOSEL_MASK | RCC_CFGR_MCOPRE_MASK);
putreg32(regval, STM32_RCC_CFGR);
/* Make sure that the selected MSI source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI);
/* Now we can disable the alternative clock sources: HSE, HSI, and PLL. Also,
* reset the HSE bypass.
*/
regval = getreg32(STM32_RCC_CR); /* Disable the HSE and the PLL */
regval &= ~(RCC_CR_HSEON | RCC_CR_PLLON);
regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */
regval &= ~RCC_CR_HSEBYP;
putreg32(regval, STM32_RCC_CR);
regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLXTPRE, PLLMUL, and PLLDIV bits */
/* Now we can reset the CFGR PLL fields to their reset value */
regval = getreg32(STM32_RCC_CFGR); /* Reset PLLSRC, PLLMUL, and PLLDIV bits */
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK | RCC_CFGR_PLLDIV_MASK);
putreg32(regval, STM32_RCC_CFGR);
/* Make sure that all interrupts are disabled */
putreg32(0, STM32_RCC_CIR); /* Disable all interrupts */
/* Rest the FLASH controller to 32-bit mode, no wait states.
*
* First, program the new number of WS to the LATENCY bit in Flash access
* control register (FLASH_ACR)
*/
regval = getreg32(STM32_FLASH_ACR);
regval &= ~FLASH_ACR_LATENCY; /* No wait states */
putreg32(regval, STM32_FLASH_ACR);
/* Check that the new number of WS is taken into account by reading FLASH_ACR */
/* Program the 32-bit access by clearing ACC64 in FLASH_ACR */
regval &= ~FLASH_ACR_ACC64; /* 32-bit access mode */
putreg32(regval, STM32_FLASH_ACR);
/* Check that 32-bit access is taken into account by reading FLASH_ACR */
}
/****************************************************************************
@ -400,13 +449,13 @@ static inline bool stm32_rcc_enablehse(void)
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
/* Check if the HSERDY flag is set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
/* If so, then return TRUE */
break;
return true;
}
}
@ -414,7 +463,7 @@ static inline bool stm32_rcc_enablehse(void)
* strategy. This is almost always a hardware failure or misconfiguration.
*/
return timeout > 0;
return false;
}
#endif
@ -471,7 +520,7 @@ static void stm32_stdclockconfig(void)
* bits) or/and the AHB prescaler value (HPRE bits), respectively, in the
* RCC_CFGR register
*/
regval = getreg32(STM32_FLASH_ACR);
regval |= FLASH_ACR_ACC64; /* 64-bit access mode */
putreg32(regval, STM32_FLASH_ACR);
@ -509,10 +558,13 @@ static void stm32_stdclockconfig(void)
#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
/* Set the PLL divider and multipler */
/* Set the PLL divider and multipler. NOTE: The PLL needs to be disabled
* to do these operation. We know this is the case here because pll_reset()
* was previously called by stm32_clockconfig().
*/
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK);
regval = getreg32(STM32_RCC_CFGR);
regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK | RCC_CFGR_PLLDIV_MASK);
regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLMUL | STM32_CFGR_PLLDIV);
putreg32(regval, STM32_RCC_CFGR);

74
configs/stm32ldiscovery/README.txt
View File

@ -161,7 +161,7 @@ GNU Toolchain Options
toolchain options.
1. The CodeSourcery GNU toolchain,
2. The Atollic Toolchain,
2. The Atollic Toolchain,
3. The devkitARM GNU toolchain,
4. Raisonance GNU toolchain, or
5. The NuttX buildroot Toolchain (see below).
@ -240,7 +240,7 @@ GNU Toolchain Options
In order to compile successfully. Otherwise, you will get errors like:
"C++ Compiler only available in TrueSTUDIO Professional"
The make may then fail in some of the post link processing because of some of
the other missing tools. The Make.defs file replaces the ar and nm with
the default system x86 tool versions and these seem to work okay. Disable all
@ -262,7 +262,7 @@ IDEs
NuttX is built using command-line make. It can be used with an IDE, but some
effort will be required to create the project.
Makefile Build
--------------
Under Eclipse, it is pretty easy to set up an "empty makefile project" and
@ -359,7 +359,7 @@ NXFLAT Toolchain
tools -- just the NXFLAT tools. The buildroot with the NXFLAT tools can
be downloaded from the NuttX SourceForge download site
(https://sourceforge.net/projects/nuttx/files/).
This GNU toolchain builds and executes in the Linux or Cygwin environment.
1. You must have already configured Nuttx in <some-dir>/nuttx.
@ -440,6 +440,10 @@ used if either the LCD or the on-board LEDs are disabled.
PC10 USART3_TX LCD SEG22 P2, pin 15
PC11 USART3_RX LCD SEG23 P2, pin 14
GND and (external) 5V are available on both P1 and P2. Note: These signals
may be at lower voltage levels and, hence, may not properly drive an external
RS-232 transceiver.
A USB serial console is another option.
Debugging
@ -501,7 +505,7 @@ STM32L-Discovery-specific Configuration Options
configuration features.
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
hence, the board that supports the particular chip or SoC.
@ -562,7 +566,7 @@ STM32L-Discovery-specific Configuration Options
CONFIG_STM32_FLITF
CONFIG_STM32_DMA1
CONFIG_STM32_DMA2
APB2
----
CONFIG_STM32_SYSCFG
@ -613,7 +617,7 @@ STM32L-Discovery-specific Configuration Options
configuration settings:
CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
NOTE: The STM32 timers are each capable of generating different signals on
each of the four channels with different duty cycles. That capability is
not supported by this driver: Only one output channel per timer.
@ -685,13 +689,10 @@ Where <subdir> is one of the following:
nsh:
---
Configures the NuttShell (nsh) located at apps/examples/nsh. The
Configuration enables the serial interfaces on UART2. Support for
builtin applications is enabled, but in the base configuration no
builtin applications are selected (see NOTES below).
Configures the NuttShell (nsh) located at apps/examples/nsh.
NOTES:
1. This configuration uses the mconf-based configuration tool. To
change this configuration using that tool, you should:
@ -701,7 +702,14 @@ Where <subdir> is one of the following:
b. Execute 'make menuconfig' in nuttx/ in order to start the
reconfiguration process.
2. By default, this configuration uses the CodeSourcery toolchain
2. The serial console is on UART1 and NuttX LED support is enabled.
Therefore, you will need an external RS232 driver or TTL serial-to-
USB converter. The UART1 TX and RX pins should be available on
PA9 and PA10, respectively.
3. Support for NSH built-in applications is *not* enabled.
4. By default, this configuration uses the CodeSourcery toolchain
for Windows and builds under Cygwin (or probably MSYS). That
can easily be reconfigured, of course.
@ -709,7 +717,14 @@ Where <subdir> is one of the following:
CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
3. This configuration includes USB Support (CDC/ACM device)
5. This configuration can support USB (CDC/ACM device)
a) Enable NSH builtin application support
CONFIG_BUILTIN=y
CONFIG_NSH_BUILTIN_APPS=y
b) Enable USB device and CDC/ACM class support
CONFIG_STM32_USB=y : STM32 USB device support
CONFIG_USBDEV=y : USB device support must be enabled
@ -717,14 +732,16 @@ Where <subdir> is one of the following:
CONFIG_NSH_BUILTIN_APPS=y : NSH built-in application support must be enabled
CONFIG_NSH_ARCHINIT=y : To perform USB initialization
The CDC/ACM example is included as two NSH "built-in" commands.\
c) Enable the CDC/ACM example
The CDC/ACM example is included as two NSH "built-in" commands.
CONFIG_EXAMPLES_CDCACM=y : Enable apps/examples/cdcacm
The two commands are:
sercon : Connect the serial device a create /dev/ttyACM0
serdis : Disconnect the serial device.
serdis : Disconnect the serial device.
NOTE: The serial connections/disconnections do not work as advertised.
This is because the STM32L-Discovery board does not provide circuitry for
@ -735,25 +752,8 @@ Where <subdir> is one of the following:
1) Start NSH with USB disconnected
2) enter to 'sercon' command to start the CDC/ACM device, then
3) Connect the USB device to the host.
and to close the connection:
4) Disconnect the USB device from the host
5) Enter the 'serdis' command
4. This example can support the watchdog timer test (apps/examples/watchdog)
but this must be enabled by selecting:
CONFIG_EXAMPLES_WATCHDOG=y : Enable the apps/examples/watchdog
CONFIG_WATCHDOG=y : Enables watchdog timer driver support
CONFIG_STM32_WWDG=y : Enables the WWDG timer facility, OR
CONFIG_STM32_IWDG=y : Enables the IWDG timer facility (but not both)
The WWDG watchdog is driven off the (fast) 42MHz PCLK1 and, as result,
has a maximum timeout value of 49 milliseconds. for WWDG watchdog, you
should also add the fillowing to the configuration file:
CONFIG_EXAMPLES_WATCHDOG_PINGDELAY=20
CONFIG_EXAMPLES_WATCHDOG_TIMEOUT=49
The IWDG timer has a range of about 35 seconds and should not be an issue.

6
configs/stm32ldiscovery/include/board.h
View File

@ -136,10 +136,10 @@
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
/* APB1 clock (PCLK1) is HCLK (32MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY)
/* APB1 timers 2-7 will receive PCLK1 */

6
configs/stm32ldiscovery/nsh/defconfig
View File

@ -266,7 +266,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y
#
# Board Settings
#
CONFIG_BOARD_LOOPSPERMSEC=6522
CONFIG_BOARD_LOOPSPERMSEC=2500
# CONFIG_ARCH_CALIBRATION is not set
CONFIG_DRAM_START=0x20000000
CONFIG_DRAM_SIZE=16384
@ -293,9 +293,9 @@ CONFIG_ARCH_BOARD="stm32ldiscovery"
# Common Board Options
#
CONFIG_ARCH_HAVE_LEDS=y
# CONFIG_ARCH_LEDS is not set
CONFIG_ARCH_LEDS=y
CONFIG_ARCH_HAVE_BUTTONS=y
CONFIG_ARCH_BUTTONS=y
# CONFIG_ARCH_BUTTONS is not set
CONFIG_ARCH_HAVE_IRQBUTTONS=y
# CONFIG_ARCH_IRQBUTTONS is not set
CONFIG_NSH_MMCSDMINOR=0