From 5b684b9b6c28e0efb3f863cc8c13cc91d79ddfe1 Mon Sep 17 00:00:00 2001 From: patacongo Date: Wed, 11 May 2011 20:44:33 +0000 Subject: [PATCH] More PIC32 header files git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3590 42af7a65-404d-4744-a932-0658087f49c3 --- arch/mips/src/pic32mx/chip.h | 17 ++ arch/mips/src/pic32mx/pic32mx-ioport.h | 295 ++++++++++++++++++++++ arch/mips/src/pic32mx/pic32mx-memorymap.h | 32 +-- arch/mips/src/pic32mx/pic32mx-uart.h | 200 +++++++++++++++ 4 files changed, 528 insertions(+), 16 deletions(-) create mode 100755 arch/mips/src/pic32mx/pic32mx-ioport.h create mode 100755 arch/mips/src/pic32mx/pic32mx-uart.h diff --git a/arch/mips/src/pic32mx/chip.h b/arch/mips/src/pic32mx/chip.h index 8f9b9f32ff..1912eb6e28 100755 --- a/arch/mips/src/pic32mx/chip.h +++ b/arch/mips/src/pic32mx/chip.h @@ -63,6 +63,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -86,6 +87,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -109,6 +111,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -132,6 +135,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -155,6 +159,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -178,6 +183,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -201,6 +207,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -224,6 +231,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -247,6 +255,7 @@ # define CHIP_VREG # define CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -270,6 +279,7 @@ # define CHIP_VREG # define CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -293,6 +303,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 1 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -316,6 +327,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 1 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -339,6 +351,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 1 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -362,6 +375,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 1 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -385,6 +399,7 @@ # define CHIP_VREG # undef CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -408,6 +423,7 @@ # define CHIP_VREG # define CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 @@ -431,6 +447,7 @@ # define CHIP_VREG # define CHIP_TRACE # define CHIP_NEUARTS 2 +# define CHIP_UARTFIFOD 4 # define CHIP_NSPI 2 # define CHIP_NI2C 2 # define CHIP_NADC10 16 diff --git a/arch/mips/src/pic32mx/pic32mx-ioport.h b/arch/mips/src/pic32mx/pic32mx-ioport.h new file mode 100755 index 0000000000..c730e8dcf0 --- /dev/null +++ b/arch/mips/src/pic32mx/pic32mx-ioport.h @@ -0,0 +1,295 @@ +/******************************************************************************************** + * arch/mips/src/pic32mx/pic32mx-ioport.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "pic32mx-memorymap.h" + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* Register Offsets *************************************************************************/ +/* Offsets relative to PIC32MX_IOPORTn_K1BASE */ + +#define PIC32MX_IOPORT_TRIS_OFFSET 0x0000 /* Tri-state register */ +#define PIC32MX_IOPORT_TRISCLR_OFFSET 0x0004 /* Tri-state clear register */ +#define PIC32MX_IOPORT_TRISSET_OFFSET 0x0008 /* Tri-state set register */ +#define PIC32MX_IOPORT_TRISINV_OFFSET 0x000c /* Tri-state invert register */ +#define PIC32MX_IOPORT_PORT_OFFSET 0x0010 /* Port register */ +#define PIC32MX_IOPORT_PORTCLR_OFFSET 0x0014 /* Port clear register */ +#define PIC32MX_IOPORT_PORTSET_OFFSET 0x0018 /* Port set register */ +#define PIC32MX_IOPORT_PORTINV_OFFSET 0x001c /* Port invert register */ +#define PIC32MX_IOPORT_LAT_OFFSET 0x0020 /* Port data latch register */ +#define PIC32MX_IOPORT_LATCLR_OFFSET 0x0024 /* Port data latch clear register */ +#define PIC32MX_IOPORT_LATSET_OFFSET 0x0028 /* Port data latch set register */ +#define PIC32MX_IOPORT_LATINV_OFFSET 0x002c /* Port data latch invert register */ +#define PIC32MX_IOPORT_ODC_OFFSET 0x0030 /* Open drain control register */ +#define PIC32MX_IOPORT_ODCCLR_OFFSET 0x0034 /* Open drain control clear register */ +#define PIC32MX_IOPORT_ODCSET_OFFSET 0x0038 /* Open drain control set register */ +#define PIC32MX_IOPORT_ODCINV_OFFSET 0x003c /* Open drain control invert register */ + +/* Offsets relative to PIC32MX_IOPORTCN_K1BASE */ + +#define PIC32MX_IOPORT_CNCON_OFFSET 0x0000 /* Interrupt-on-change control register */ +#define PIC32MX_IOPORT_CNCONCLR_OFFSET 0x0004 /* Interrupt-on-change control clear register */ +#define PIC32MX_IOPORT_CNCONSET_OFFSET 0x0008 /* Interrupt-on-change control set register */ +#define PIC32MX_IOPORT_CNCONINV_OFFSET 0x000c /* Interrupt-on-change control invert register */ +#define PIC32MX_IOPORT_CNEN_OFFSET 0x0010 /* Input change notification interrupt enable */ +#define PIC32MX_IOPORT_CNENCLR_OFFSET 0x0014 /* Input change notification interrupt enable clear */ +#define PIC32MX_IOPORT_CNENSET_OFFSET 0x0018 /* Input change notification interrupt enable set */ +#define PIC32MX_IOPORT_CNENINV_OFFSET 0x001c /* Input change notification interrupt enable invert */ +#define PIC32MX_IOPORT_CNPUE_OFFSET 0x0020 /* Input change notification pull-up enable */ +#define PIC32MX_IOPORT_CNPUECLR_OFFSET 0x0024 /* Input change notification pull-up enable clear */ +#define PIC32MX_IOPORT_CNPUESET_OFFSET 0x0028 /* Input change notification pull-up enable set */ +#define PIC32MX_IOPORT_CNPUEINV_OFFSET 0x002c /* Input change notification pull-up enable invert */ + +/* Register Addresses ***********************************************************************/ + +#define PIC32MX_IOPORT_TRIS(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRIS_OFFSET) +#define PIC32MX_IOPORT_TRISCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISCLR_OFFSET) +#define PIC32MX_IOPORT_TRISSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISSET_OFFSET) +#define PIC32MX_IOPORT_TRISINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_TRISINV_OFFSET) +#define PIC32MX_IOPORT_PORT(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORT_OFFSET) +#define PIC32MX_IOPORT_PORTCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORTCLR_OFFSET) +#define PIC32MX_IOPORT_PORTSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORTSET_OFFSET) +#define PIC32MX_IOPORT_PORTINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_PORTINV_OFFSET) +#define PIC32MX_IOPORT_LAT(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LAT_OFFSET) +#define PIC32MX_IOPORT_LATCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LATCLR_OFFSET) +#define PIC32MX_IOPORT_LATSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LATSET_OFFSET) +#define PIC32MX_IOPORT_LATINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_LATINV_OFFSET) +#define PIC32MX_IOPORT_ODC(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODC_OFFSET) +#define PIC32MX_IOPORT_ODCCLR(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCCLR_OFFSET) +#define PIC32MX_IOPORT_ODCSET(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCSET_OFFSET) +#define PIC32MX_IOPORT_ODCINV(n) (PIC32MX_IOPORT_K1BASE(n)+PIC32MX_IOPORT_ODCINV_OFFSET) + +#define PIC32MX_IOPORTA_TRIS (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) +#define PIC32MX_IOPORTA_TRISCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) +#define PIC32MX_IOPORTA_TRISSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) +#define PIC32MX_IOPORTA_TRISINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET) +#define PIC32MX_IOPORTA_PORT (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORT_OFFSET) +#define PIC32MX_IOPORTA_PORTCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET) +#define PIC32MX_IOPORTA_PORTSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET) +#define PIC32MX_IOPORTA_PORTINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET) +#define PIC32MX_IOPORTA_LAT (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LAT_OFFSET) +#define PIC32MX_IOPORTA_LATCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET) +#define PIC32MX_IOPORTA_LATSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET) +#define PIC32MX_IOPORTA_LATINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET) +#define PIC32MX_IOPORTA_ODC (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODC_OFFSET) +#define PIC32MX_IOPORTA_ODCCLR (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET) +#define PIC32MX_IOPORTA_ODCSET (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) +#define PIC32MX_IOPORTA_ODCINV (PIC32MX_IOPORTA_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) + +#define PIC32MX_IOPORTB_TRIS (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) +#define PIC32MX_IOPORTB_TRISCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) +#define PIC32MX_IOPORTB_TRISSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) +#define PIC32MX_IOPORTB_TRISINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET) +#define PIC32MX_IOPORTB_PORT (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORT_OFFSET) +#define PIC32MX_IOPORTB_PORTCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET) +#define PIC32MX_IOPORTB_PORTSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET) +#define PIC32MX_IOPORTB_PORTINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET) +#define PIC32MX_IOPORTB_LAT (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LAT_OFFSET) +#define PIC32MX_IOPORTB_LATCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET) +#define PIC32MX_IOPORTB_LATSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET) +#define PIC32MX_IOPORTB_LATINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET) +#define PIC32MX_IOPORTB_ODC (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODC_OFFSET) +#define PIC32MX_IOPORTB_ODCCLR (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET) +#define PIC32MX_IOPORTB_ODCSET (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) +#define PIC32MX_IOPORTB_ODCINV (PIC32MX_IOPORTB_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) + +#define PIC32MX_IOPORTC_TRIS (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) +#define PIC32MX_IOPORTC_TRISCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) +#define PIC32MX_IOPORTC_TRISSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) +#define PIC32MX_IOPORTC_TRISINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET) +#define PIC32MX_IOPORTC_PORT (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORT_OFFSET) +#define PIC32MX_IOPORTC_PORTCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET) +#define PIC32MX_IOPORTC_PORTSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET) +#define PIC32MX_IOPORTC_PORTINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET) +#define PIC32MX_IOPORTC_LAT (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LAT_OFFSET) +#define PIC32MX_IOPORTC_LATCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET) +#define PIC32MX_IOPORTC_LATSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET) +#define PIC32MX_IOPORTC_LATINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET) +#define PIC32MX_IOPORTC_ODC (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODC_OFFSET) +#define PIC32MX_IOPORTC_ODCCLR (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET) +#define PIC32MX_IOPORTC_ODCSET (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) +#define PIC32MX_IOPORTC_ODCINV (PIC32MX_IOPORTC_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) + +#define PIC32MX_IOPORTD_TRIS (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) +#define PIC32MX_IOPORTD_TRISCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) +#define PIC32MX_IOPORTD_TRISSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) +#define PIC32MX_IOPORTD_TRISINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET) +#define PIC32MX_IOPORTD_PORT (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORT_OFFSET) +#define PIC32MX_IOPORTD_PORTCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET) +#define PIC32MX_IOPORTD_PORTSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET) +#define PIC32MX_IOPORTD_PORTINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET) +#define PIC32MX_IOPORTD_LAT (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LAT_OFFSET) +#define PIC32MX_IOPORTD_LATCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET) +#define PIC32MX_IOPORTD_LATSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET) +#define PIC32MX_IOPORTD_LATINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET) +#define PIC32MX_IOPORTD_ODC (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODC_OFFSET) +#define PIC32MX_IOPORTD_ODCCLR (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET) +#define PIC32MX_IOPORTD_ODCSET (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) +#define PIC32MX_IOPORTD_ODCINV (PIC32MX_IOPORTD_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) + +#define PIC32MX_IOPORTE_TRIS (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) +#define PIC32MX_IOPORTE_TRISCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) +#define PIC32MX_IOPORTE_TRISSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) +#define PIC32MX_IOPORTE_TRISINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET) +#define PIC32MX_IOPORTE_PORT (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORT_OFFSET) +#define PIC32MX_IOPORTE_PORTCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET) +#define PIC32MX_IOPORTE_PORTSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET) +#define PIC32MX_IOPORTE_PORTINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET) +#define PIC32MX_IOPORTE_LAT (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LAT_OFFSET) +#define PIC32MX_IOPORTE_LATCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET) +#define PIC32MX_IOPORTE_LATSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET) +#define PIC32MX_IOPORTE_LATINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET) +#define PIC32MX_IOPORTE_ODC (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODC_OFFSET) +#define PIC32MX_IOPORTE_ODCCLR (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET) +#define PIC32MX_IOPORTE_ODCSET (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) +#define PIC32MX_IOPORTE_ODCINV (PIC32MX_IOPORTE_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) + +#define PIC32MX_IOPORTF_TRIS (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) +#define PIC32MX_IOPORTF_TRISCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) +#define PIC32MX_IOPORTF_TRISSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) +#define PIC32MX_IOPORTF_TRISINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET) +#define PIC32MX_IOPORTF_PORT (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORT_OFFSET) +#define PIC32MX_IOPORTF_PORTCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET) +#define PIC32MX_IOPORTF_PORTSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET) +#define PIC32MX_IOPORTF_PORTINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET) +#define PIC32MX_IOPORTF_LAT (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LAT_OFFSET) +#define PIC32MX_IOPORTF_LATCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET) +#define PIC32MX_IOPORTF_LATSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET) +#define PIC32MX_IOPORTF_LATINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET) +#define PIC32MX_IOPORTF_ODC (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODC_OFFSET) +#define PIC32MX_IOPORTF_ODCCLR (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET) +#define PIC32MX_IOPORTF_ODCSET (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) +#define PIC32MX_IOPORTF_ODCINV (PIC32MX_IOPORTF_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) + +#define PIC32MX_IOPORTG_TRIS (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRIS_OFFSET) +#define PIC32MX_IOPORTG_TRISCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRISCLR_OFFSET) +#define PIC32MX_IOPORTG_TRISSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRISSET_OFFSET) +#define PIC32MX_IOPORTG_TRISINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_TRISINV_OFFSET) +#define PIC32MX_IOPORTG_PORT (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORT_OFFSET) +#define PIC32MX_IOPORTG_PORTCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORTCLR_OFFSET) +#define PIC32MX_IOPORTG_PORTSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORTSET_OFFSET) +#define PIC32MX_IOPORTG_PORTINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_PORTINV_OFFSET) +#define PIC32MX_IOPORTG_LAT (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LAT_OFFSET) +#define PIC32MX_IOPORTG_LATCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LATCLR_OFFSET) +#define PIC32MX_IOPORTG_LATSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LATSET_OFFSET) +#define PIC32MX_IOPORTG_LATINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_LATINV_OFFSET) +#define PIC32MX_IOPORTG_ODC (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODC_OFFSET) +#define PIC32MX_IOPORTG_ODCCLR (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCCLR_OFFSET) +#define PIC32MX_IOPORTG_ODCSET (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCSET_OFFSET) +#define PIC32MX_IOPORTG_ODCINV (PIC32MX_IOPORTG_K1BASE+PIC32MX_IOPORT_ODCINV_OFFSET) + +#define PIC32MX_IOPORT_CNCON (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCON_OFFSET) +#define PIC32MX_IOPORT_CNCONCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONCLR_OFFSET) +#define PIC32MX_IOPORT_CNCONSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONSET_OFFSET) +#define PIC32MX_IOPORT_CNCONINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNCONINV_OFFSET) +#define PIC32MX_IOPORT_CNEN (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNEN_OFFSET) +#define PIC32MX_IOPORT_CNENCLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENCLR_OFFSET) +#define PIC32MX_IOPORT_CNENSET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENSET_OFFSET) +#define PIC32MX_IOPORT_CNENINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNENINV_OFFSET) +#define PIC32MX_IOPORT_CNPUE (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUE_OFFSET) +#define PIC32MX_IOPORT_CNPUECLR (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUECLR_OFFSET) +#define PIC32MX_IOPORT_CNPUESET (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUESET_OFFSET) +#define PIC32MX_IOPORT_CNPUEINV (PIC32MX_IOPORTCN_K1BASE+PIC32MX_IOPORT_CNPUEINV_OFFSET) + +/* Register Bit-Field Definitions ***********************************************************/ + +/* Tri-state register */ + +#define IOPORT_TRIS(n) (1 << (n)) /* Bits 0-15: 1: Input 0: Output */ + +/* Port register */ + +#define IOPORT_PORT(n) (1 << (n)) /* Bits 0-15: Pin value */ + +/* Port data latch register */ + +#define IOPORT_LAT(n) (1 << (n)) /* Bits 0-15: Port latch value */ + +/* Open drain control register */ + +#define IOPORT_ODC(n) (1 << (n)) /* Bits 0-15: 1: OD output enabled, 0: Disabled */ + +/* Interrupt-on-change control register */ + +#define IOPORT_CNCON_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ +#define IOPORT_CNCON_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */ +#define IOPORT_CNCON_ON (1 << 15) /* Bit 15: Change notice module enable */ + +/* Input change notification interrupt enable */ + +#define IOPORT_CNEN(n) (1 << (n)) /* Bits 0-18/21: Port pin input change notice enabled */ + +/* Input change notification pull-up enable */ + +#define IOPORT_CNPUE(n) (1 << (n)) /* Bits 0-18/21: Port pin pull-up enabled */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_IOPORT_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-memorymap.h b/arch/mips/src/pic32mx/pic32mx-memorymap.h index 5d8ddddb5b..90ba267f4a 100755 --- a/arch/mips/src/pic32mx/pic32mx-memorymap.h +++ b/arch/mips/src/pic32mx/pic32mx-memorymap.h @@ -176,24 +176,24 @@ /* Port Register Base Addresses */ -#define PIC32MX_PORTA 0 -#define PIC32MX_PORTB 1 -#define PIC32MX_PORTC 2 -#define PIC32MX_PORTD 3 -#define PIC32MX_PORTE 4 -#define PIC32MX_PORTF 5 -#define PIC32MX_PORTG 6 -#define PIC32MX_PORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x20*(n)) +#define PIC32MX_IOPORTA 0 +#define PIC32MX_IOPORTB 1 +#define PIC32MX_IOPORTC 2 +#define PIC32MX_IOPORTD 3 +#define PIC32MX_IOPORTE 4 +#define PIC32MX_IOPORTF 5 +#define PIC32MX_IOPORTG 6 +#define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x40*(n)) -#define PIC32MX_PORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000) -#define PIC32MX_PORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040) -#define PIC32MX_PORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080) -#define PIC32MX_PORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0) -#define PIC32MX_PORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100) -#define PIC32MX_PORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140) -#define PIC32MX_PORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180) +#define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000) +#define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040) +#define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080) +#define PIC32MX_IOPORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0) +#define PIC32MX_IOPORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100) +#define PIC32MX_IOPORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140) +#define PIC32MX_IOPORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180) -#define PIC32MX_CNCON_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0) +#define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0) /**************************************************************************** * Public Types diff --git a/arch/mips/src/pic32mx/pic32mx-uart.h b/arch/mips/src/pic32mx/pic32mx-uart.h new file mode 100755 index 0000000000..672752c87b --- /dev/null +++ b/arch/mips/src/pic32mx/pic32mx-uart.h @@ -0,0 +1,200 @@ +/************************************************************************************ + * arch/mips/src/pic32mx/pic32mx-uart.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_UART_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_UART_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "pic32mx-memorymap.h" + +/************************************************************************************ + * Pre-Processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define PIC32MX_UART_MODE_OFFSET 0x0000 /* UARTx mode register */ +#define PIC32MX_UART_MODECLR_OFFSET 0x0004 /* UARTx mode clear register */ +#define PIC32MX_UART_MODESET_OFFSET 0x0008 /* UARTx mode set register */ +#define PIC32MX_UART_MODEINV_OFFSET 0x000c /* UARTx mode invert register */ +#define PIC32MX_UART_STA_OFFSET 0x0010 /* UARTx status and control register */ +#define PIC32MX_UART_STACLR_OFFSET 0x0014 /* UARTx status and control clear register */ +#define PIC32MX_UART_STASET_OFFSET 0x0018 /* UARTx status and control set register */ +#define PIC32MX_UART_STAINV_OFFSET 0x001c /* UARTx status and control invert register */ +#define PIC32MX_UART_TXREG_OFFSET 0x0020 /* UARTx transmit register */ +#define PIC32MX_UART_RXREG_OFFSET 0x0030 /* UARTx receive register */ +#define PIC32MX_UART_BRG_OFFSET 0x0040 /* UARTx baud rate register */ +#define PIC32MX_UART_BRGCLR_OFFSET 0x0044 /* UARTx baud rate clear register */ +#define PIC32MX_UART_BRGSET_OFFSET 0x0048 /* UARTx baud rate set register */ +#define PIC32MX_UART_BRGINV_OFFSET 0x004c /* UARTx baud rate invert register */ + +/* Register Addresses ****************************************************************/ + +#define PIC32MX_UART1_MODE (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODE_OFFSET) +#define PIC32MX_UART1_MODECLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODECLR_OFFSET) +#define PIC32MX_UART1_MODESET (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODESET_OFFSET) +#define PIC32MX_UART1_MODEINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODEINV_OFFSET) +#define PIC32MX_UART1_STA (PIC32MX_UART1_K1BASE+PIC32MX_UART_STA_OFFSET) +#define PIC32MX_UART1_STACLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_STACLR_OFFSET) +#define PIC32MX_UART1_STASET (PIC32MX_UART1_K1BASE+PIC32MX_UART_STASET_OFFSET) +#define PIC32MX_UART1_STAINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_STAINV_OFFSET) +#define PIC32MX_UART1_TXREG (PIC32MX_UART1_K1BASE+PIC32MX_UART_TXREG_OFFSET) +#define PIC32MX_UART1_RXREG (PIC32MX_UART1_K1BASE+PIC32MX_UART_RXREG_OFFSET) +#define PIC32MX_UART1_BRG (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRG_OFFSET) +#define PIC32MX_UART1_BRGCLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGCLR_OFFSET) +#define PIC32MX_UART1_BRGSET (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGSET_OFFSET) +#define PIC32MX_UART1_BRGINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGINV_OFFSET) + +#define PIC32MX_UART2_MODE (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODE_OFFSET) +#define PIC32MX_UART2_MODECLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODECLR_OFFSET) +#define PIC32MX_UART2_MODESET (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODESET_OFFSET) +#define PIC32MX_UART2_MODEINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODEINV_OFFSET) +#define PIC32MX_UART2_STA (PIC32MX_UART2_K1BASE+PIC32MX_UART_STA_OFFSET) +#define PIC32MX_UART2_STACLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_STACLR_OFFSET) +#define PIC32MX_UART2_STASET (PIC32MX_UART2_K1BASE+PIC32MX_UART_STASET_OFFSET) +#define PIC32MX_UART2_STAINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_STAINV_OFFSET) +#define PIC32MX_UART2_TXREG (PIC32MX_UART2_K1BASE+PIC32MX_UART_TXREG_OFFSET) +#define PIC32MX_UART2_RXREG (PIC32MX_UART2_K1BASE+PIC32MX_UART_RXREG_OFFSET) +#define PIC32MX_UART2_BRG (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRG_OFFSET) +#define PIC32MX_UART2_BRGCLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGCLR_OFFSET) +#define PIC32MX_UART2_BRGSET (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGSET_OFFSET) +#define PIC32MX_UART2_BRGINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGINV_OFFSET) + +/* Register Bit-Field Definitions ****************************************************/ + +/* UARTx mode register */ + +#define UART_MODE_STSEL (1 << 0) /* Bit 0: Stop selection 1=2 stop bits */ +#define UART_MODE_PDSEL_SHIFT (1) /* Bits: 1-2: Parity and data selection */ +#define UART_MODE_PDSEL_MASK (3 << UART_MODE_PDSEL_SHIFT) +# define UART_MODE_PDSEL_8NONE (0 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, no parity */ +# define UART_MODE_PDSEL_8EVEN (1 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, even parity */ +# define UART_MODE_PDSEL_8ODD (2 << UART_MODE_PDSEL_SHIFT) /* 8-bit data, odd parity */ +# define UART_MODE_PDSEL_9NONE (3 << UART_MODE_PDSEL_SHIFT) /* 9-bit data, no parity */ +#define UART_MODE_BRGH (1 << 3) /* Bit 3: High baud rate enable */ +#define UART_MODE_RXINV (1 << 4) /* Bit 4: Receive polarity inversion */ +#define UART_MODE_ABAUD (1 << 5) /* Bit 5: Auto-baud enable */ +#define UART_MODE_LPBACK (1 << 6) /* Bit 6: UARTx loopback mode select */ +#define UART_MODE_WAKE (1 << 7) /* Bit 7: Enable wake-up on start bit detect during sleep mode */ +#define UART_MODE_UEN_SHIFT (8) /* Bits: 8-9: UARTx enable */ +#define UART_MODE_UEN_MASK (3 << UART_MODE_UEN_SHIFT) +# define UART_MODE_UEN_PORT (0 << UART_MODE_UEN_SHIFT) /* UxCTS+UxRTS/UxBCLK=PORTx register */ +# define UART_MODE_UEN_ENR_CPORT (1 << UART_MODE_UEN_SHIFT) /* UxRTS=enabled; UxCTS=ORTx register */ +# define UART_MODE_UEN_ENCR (2 << UART_MODE_UEN_SHIFT) /* UxCTS+UxRTS=enabled */ +# define UART_MODE_UEN_CPORT (3 << UART_MODE_UEN_SHIFT) /* UxCTS=PORTx register */ +#define UART_MODE_RTSMD (1 << 11) /* Bit 11: Mode selection for ~UxRTS pin */ +#define UART_MODE_IREN (1 << 12) /* Bit 12: IrDA encoder and decoder enable */ +#define UART_MODE_SIDL (1 << 13) /* Bit 13: Stop in idle mode */ +#define UART_MODE_FRZ (1 << 14) /* Bit 14: Freeze in debug exception mode */ +#define UART_MODE_ON (1 << 15) /* Bit 15: UARTx enable */ + +/* UARTx status and control register */ + +#define UART_STA_URXDA (1 << 0) /* Bit 0: Receive buffer data available */ +#define UART_STA_OERR (1 << 1) /* Bit 1: Receive buffer overrun error status */ +#define UART_STA_FERR (1 << 2) /* Bit 2: Framing error status */ +#define UART_STA_PERR (1 << 3) /* Bit 3: Parity error status */ +#define UART_STA_RIDLE (1 << 4) /* Bit 4: Receiver idle */ +#define UART_STA_ADDEN (1 << 5) /* Bit 5: Address character detect */ +#define UART_STA_URXISEL_SHIFT (6) /* Bits: 6-7: Receive interrupt mode selection */ +#define UART_STA_URXISEL_MASK (3 << UART_STA_URXISEL_SHIFT) +#if CHIP_UARTFIFOD == 4 +# define UART_STA_URXISEL_RECVD (0 << UART_STA_URXISEL_SHIFT) /* Character received */ +# define UART_STA_URXISEL_RXB3 (2 << UART_STA_URXISEL_SHIFT) /* RX buffer 3/4 */ +# define UART_STA_URXISEL_RXBF (3 << UART_STA_URXISEL_SHIFT) /* RX buffer full */ +#elif CHIP_UARTFIFOD == 8 +# define UART_STA_URXISEL_RECVD (0 << UART_STA_URXISEL_SHIFT) /* Character received */ +# define UART_STA_URXISEL_RXB4 (1 << UART_STA_URXISEL_SHIFT) /* RX buffer 1/2 */ +# define UART_STA_URXISEL_RXB6 (2 << UART_STA_URXISEL_SHIFT) /* RX buffer 3/4 */ +#endif +#define UART_STA_TRMT (1 << 8) /* Bit 8: Transmit shift register is empty */ +#define UART_STA_UTXBF (1 << 9) /* Bit 9: Transmit buffer full status */ +#define UART_STA_UTXEN (1 << 10) /* Bit 10: Transmit enable */ +#define UART_STA_UTXBRK (1 << 11) /* Bit 11: Transmit break */ +#define UART_STA_URXEN (1 << 12) /* Bit 12: Receiver enable */ +#define UART_STA_UTXINV (1 << 13) /* Bit 13: Transmit polarity inversion */ +#define UART_STA_UTXISEL_SHIFT (14) /* Bits: 14-15: TX interrupt mode selection bi */ +#define UART_STA_UTXISEL_MASK (3 << UART_STA_UTXISEL_SHIFT) +# define UART_STA_UTXISEL_TXBNF (0 << UART_STA_UTXISEL_SHIFT) /* TX buffer not full */ +# define UART_STA_UTXISEL_DRAINED (1 << UART_STA_UTXISEL_SHIFT) /* All characters sent */ +# define UART_STA_UTXISEL_TXBE (2 << UART_STA_UTXISEL_SHIFT) /* TX buffer empty */ +#define UART_STA_ADDR_SHIFT (16) /* Bits:16-23: Automatic address mask */ +#define UART_STA_ADDR_MASK (0xff << UART_STA_ADDR_SHIFT) +#define UART_STA_ADM_EN (1 << 24) /* Bit 14: Automatic address detect mode enable */ + +/* UARTx transmit register */ + +#define UART_TXREG_MASK 0x1ff + +/* UARTx receive register */ + +#define UART_RXREG_MASK 0x1ff + +/* UARTx baud rate register */ + +#define UART_BRG_MASK 0xffff + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_UART_H */