Add support for M16C timer interrupt
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1505 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
a06bc37358
commit
5b7fcc12a2
@ -196,6 +196,8 @@
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# define NR_IRQS (_LAST_FIXED+28) /* Total number of supported IRQs */
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#endif
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/* Timer A0 is the system timer used by NuttX */
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#define M16C_SYSTIMER_IRQ M16C_TMRA0_IRQ
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/* IRQ Stack Frame Format. The M16C has a push down stack. The CPU performs
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@ -45,7 +45,8 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c \
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CHIP_ASRCS = m16c_vectors.S
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#CHIP_CSRCS = m16c_initialstate.c m16c_copystate.c m16c_lowputc.c m16c_irq.c \
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# m16c_timerisr.c m16c_serial.c m16c_dumpstate.c
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CHIP_CSRCS = m16c_initialstate.c m16c_copystate.c m16c_irq.c m16c_dumpstate.c
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CHIP_CSRCS = m16c_initialstate.c m16c_copystate.c m16c_irq.c \
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m16c_timerisr.c m16c_dumpstate.c
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ifneq ($(CONFIG_DISABLE_SIGNALS),y)
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CHIP_CSRCS += m16c_schedulesigaction.c m16c_sigdeliver.c
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@ -268,5 +268,4 @@ extern uint32 g_heapbase; /* Start of the heap */
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_SH_SRC_M16C_CHIP_H */
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227
arch/sh/src/m16c/m16c_timer.h
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227
arch/sh/src/m16c/m16c_timer.h
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@ -0,0 +1,227 @@
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/************************************************************************************
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* arch/sh/src/m16c/m16c_timer.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_SH_SRC_M16C_M16C_TIMER_H
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#define __ARCH_SH_SRC_M16C_M16C_TIMER_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Bit Definitions *********************************************************/
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#define M16C_TA0IC 0x00055 /* Timer A0 interrupt control */
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#define M16C_TA1IC 0x00056 /* Timer A1 interrupt control */
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#define M16C_TA2IC 0x00057 /* Timer A2 interrupt control */
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#define M16C_TA3IC 0x00058 /* Timer A3 interrupt control */
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#define M16C_TA4IC 0x00059 /* Timer A4 interrupt control */
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/* Count Start Flag Register (8-bit access) Register */
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#define TABSR_TA0S 0x01 /* Bit 0: Timer A0 count start */
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#define TABSR_TA1S 0x02 /* Bit 1: Timer A1 count start */
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#define TABSR_TA2S 0x04 /* Bit 2: Timer A2 count start */
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#define TABSR_TA3S 0x08 /* Bit 3: Timer A3 count start */
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#define TABSR_TA4S 0x10 /* Bit 4: Timer A4 count start */
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#define TABSR_TB0S 0x20 /* Bit 5: Timer B0 count start */
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#define TABSR_TB1S 0x40 /* Bit 6: Timer B1 count start */
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#define TABSR_TB2S 0x80 /* Bit 7: Timer B2 count start */
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/* Clock Prescaler Reset Flag Register */
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/* Bits 0-6: Not used */
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#define CPSRF_CPSR 0x80 /* Bit 7: 1=Prescaler is reset */
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/* On-Shot Start Flag Register (8-bit access) */
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#define ONSF_TA0OS 0x01 /* Bit 0: Timer A0 one shot start */
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#define ONSF_TA1OS 0x02 /* Bit 1: Timer A1 one shot start */
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#define ONSF_TA2OS 0x04 /* Bit 2: Timer A2 one shot start */
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#define ONSF_TA3OS 0x08 /* Bit 3: Timer A3 one shot start */
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#define ONSF_TA4OS 0x10 /* Bit 4: Timer A4 one shot start */
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/* Bit 5: Reserved */
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#define ONSF_TA0TG_MASK 0xc0 /* Bit 6-7: Timer A0 event trigger select bits */
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#define ONSF_TAOTG_INTAON 0x00 /* 00 : Input on TA0IN is selected */
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#define ONSF_TAOTG_TB2OVF 0x40 /* 01 : TB2 overflow is selected */
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#define ONSF_TAOTG_TB4OVF 0x80 /* 10 : TB4 overflow is selected */
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#define ONSF_TAOTG_TB1OVF 0xc0 /* 11 : TB1 overflow is selected */
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/* Trigger Select Register */
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#define TRGSR_TA1TG_MASK 0x03 /* Bit 0-1: Timer A1 event trigger select bits */
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#define TRGSR_TA1TG_INTAON 0x00 /* 00 : Input on TA1IN is selected */
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#define TRGSR_TA1TG_TB2OVF 0x01 /* 01 : TB2 overflow is selected */
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#define TRGSR_TA1TG_TB4OVF 0x02 /* 10 : TB4 overflow is selected */
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#define TRGSR_TA1TG_TB1OVF 0x03 /* 11 : TB1 overflow is selected */
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#define TRGSR_TA2TG_MASK 0x0c /* Bit 2-3: Timer A2 event trigger select bits */
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#define TRGSR_TA2TG_INTAON 0x00 /* 00 : Input on TA2IN is selected */
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#define TRGSR_TA2TG_TB2OVF 0x04 /* 01 : TB2 overflow is selected */
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#define TRGSR_TA2TG_TB4OVF 0x08 /* 10 : TB4 overflow is selected */
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#define TRGSR_TA2TG_TB1OVF 0x0c /* 11 : TB1 overflow is selected */
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#define TRGSR_TA3TG_MASK 0x30 /* Bit 4-5: Timer A3 event trigger select bits */
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#define TRGSR_TA3TG_INTAON 0x00 /* 00 : Input on TA3IN is selected */
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#define TRGSR_TA3TG_TB2OVF 0x10 /* 01 : TB2 overflow is selected */
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#define TRGSR_TA3TG_TB4OVF 0x20 /* 10 : TB4 overflow is selected */
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#define TRGSR_TA3TG_TB1OVF 0x30 /* 11 : TB1 overflow is selected */
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#define TRGSR_TA4TG_MASK 0xc0 /* Bit 6-7: Timer A4 event trigger select bits */
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#define TRGSR_TA4TG_INTAON 0x00 /* 00 : Input on TA4IN is selected */
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#define TRGSR_TA4TG_TB2OVF 0x40 /* 01 : TB2 overflow is selected */
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#define TRGSR_TA4TG_TB4OVF 0x80 /* 10 : TB4 overflow is selected */
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#define TRGSR_TA4TG_TB1OVF 0xc0 /* 11 : TB1 overflow is selected */
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/* Up-Down Flag Register */
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#define UDF_TA0UD 0x01 /* Bit 0: 1=Timer A0 up count */
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#define UDF_TA1UD 0x02 /* Bit 1: 1=Timer A1 up count */
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#define UDF_TA2UD 0x04 /* Bit 2: 1=Timer A2 up count */
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#define UDF_TA3UD 0x08 /* Bit 3: 1=Timer A3 up count */
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#define UDF_TA4UD 0x10 /* Bit 4: 1=Timer A4 up count */
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#define UDF_TA2P 0x20 /* Bit 5: Timer A2 two-phase pulse signal processing select */
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#define UDF_TA3P 0x40 /* Bit 5: Timer A3 two-phase pulse signal processing select */
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#define UDF_TA4P 0x80 /* Bit 5: Timer A4 two-phase pulse signal processing select */
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/* Timer A Registers (16-bit access), simple value range 0000-ffff
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* (except in PWM mode)
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*/
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/* Timer B Registers (16-bit access), simple value range 0000-ffff
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* (except in Pulse period/pulse width measurement mode)
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*/
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/* Timer A Mode Register (8-bit access) */
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#define TAnMR_TMOD_MASK 0x03 /* Bits 0-1: Operation mode select */
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#define TAnMR_TMOD_TIMER 0x00 /* 00 : Timer mode */
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#define TAnMR_TMOD_EVENT 0x01 /* 01 : Event counter mode */
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#define TAnMR_TMOD_ONESHOT 0x02 /* 10 : One-shot timer mode */
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#define TAnMR_TMOD_PWM 0x03 /* 11 : Pulse width modulation (PWM) mode */
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#define TAnMR_MR_MASK 0x3c /* Bits 2-5: Mode function values */
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/* Timer Mode: */
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#define TAnMR_MR_TMNOOUT 0x00 /* 0xx0 : No output */
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#define TAnMR_MR_TMOUT 0x04 /* 0xx1 : Pulse is output */
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#define TAnMR_MR_TMNOGATE 0x00 /* 00xx : Gate function not available */
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#define TAnMR_MR_TMTAINLO 0x10 /* 010x : Timer counts when TAiIN pin is L */
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#define TAnMR_MR_TMTAINHI 0x18 /* 011x : Timer counts when TAiIN pin is H */
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/* Event Counter Mode: */
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#define TAnMR_MR_EC2PHASE 0x10 /* 0100 : Settings required for 2-phase mode */
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#define TAnMR_MR_ECNOOUT 0x00 /* 0xx0 : No output */
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#define TAnMR_MR_ECOUT 0x04 /* 0xx1 : 1=Pulse is output */
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#define TAnMR_MR_ECFALLING 0x00 /* 0x0x : Count polarity falling edge */
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#define TAnMR_MR_ECRISING 0x08 /* 0x1x : Count polarity rising edge */
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#define TAnMR_MR_ECUDC 0x00 /* 00xx : Up/down switching on up/down content */
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#define TAnMR_MR_ECINP 0x10 /* 01xx : Up/down switching on TAnOUT input signal */
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/* One Shot Mode: */
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#define TAnMR_MR_OSNOOUT 0x00 /* 0xx0 : No output */
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#define TAnMR_MR_OSOUT 0x04 /* 0xx1 : Pulse is output */
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#define TAnMR_MR_OSFALLING 0x00 /* 0x0x : TAin falling edge */
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#define TAnMR_MR_OSRISING 0x08 /* 0x1x : TAin rising edge */
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#define TAnMR_MR_OSSFLAG 0x00 /* 00xx : Trigger select one-shot start flag */
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#define TAnMR_MR_OSSTRIG 0x10 /* 01xx : Trigger Selected by event/trigger select bits */
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/* PWM Mode: */
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#define TAnMR_MR_PMFALLING 0x00 /* xx00 : TAin falling edge */
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#define TAnMR_MR_PMRISING 0x08 /* xx10 : TAin rising edge */
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#define TAnMR_MR_PMSFLAG 0x00 /* x0x0 : Trigger select one-shot start flag */
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#define TAnMR_MR_PMTRIG 0x10 /* x1x0 : Trigger Selected by event/trigger select bits */
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#define TAnMR_MR_PM16BIT 0x00 /* 0xx0 : Functions as a 16-bit pulse width modulator */
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#define TAnMR_MR_PM8BIT 0x20 /* 1xx0 : Functions as an 8-bit pulse width modul */
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#define TAnMR_TCK_MASK 0xc0 /* Bits 6-7: Count source select */
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/* Timer Mode: */
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#define TAnMR_TCK_TMF1 0x00 /* 00: f1 or f2 */
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#define TAnMR_TCK_TMF8 0x40 /* 01: f8 */
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#define TAnMR_TCK_TMF32 0x80 /* 10: f32 */
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#define TAnMR_TCK_TMFC32 0xc0 /* 11: fc32 */
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/* Event Counter Mode: */
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#define TAnMR_TCK_ECRELOAD 0x00 /* x0: Reload count operation*/
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#define TAnMR_TCK_ECFRUN 0x40 /* x1: Free run count operation*/
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#define TAnMR_TCK_ECNORMAL 0x00 /* 0x: Normal processing operation */
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#define TAnMR_TCK_ECMUL4 0x80 /* 1x: Multiply-by-4 processing operation */
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/* One Shot Mode: */
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#define TAnMR_TCK_OSF1 0x00 /* 00: f1 or f2 */
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#define TAnMR_TCK_OSF8 0x40 /* 01: f8 */
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#define TAnMR_TCK_OSF32 0x80 /* 10: f32 */
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#define TAnMR_TCK_OSFC32 0xc0 /* 11: fc32 */
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/* PWM Mode: */
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#define TAnMR_TCK_PMF1 0x00 /* 00: f1 or f2 */
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#define TAnMR_TCK_PMF8 0x40 /* 01: f8 */
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#define TAnMR_TCK_PMF32 0x80 /* 10: f32 */
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#define TAnMR_TCK_PMFC32 0xc0 /* 11: fc32 */
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/* Timer B Mode Register (8-bit access) */
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#define TBnMR_TMOD_MASK 0x03 /* Bits 0-1: Operation mode select */
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#define TBnMR_TMOD_TIMER 0x00 /* 00 : Timer mode */
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#define TBnMR_TMOD_EVENT 0x01 /* 01 : Event counter mode */
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#define TBnMR_TMOD_PWM 0x02 /* 10 : Pulse period/pulse width measurement mode */
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#define TBnMR_MR_MASK 0x3c /* Bits 2-5: Mode function values */
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/* Timer Mode: */
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#define TBnMR_MR_TM 0x00 /* 0000 : Required bit settings for timer mode */
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/* Event Counter Mode: */
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#define TBnMR_MR_ECFALLING 0x00 /* 0000 : Counts external signal's falling edges */
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#define TBnMR_MR_ECRISING 0x04 /* 0001 : Counts external signal's rising edges */
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#define TBnMR_MR_ECXTFALL 0x00 /* 0010 : Counts external signal's falling and rising edges */
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/* Pulse period/pulse width measurement mode: */
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#define TBnMR_MR_PMFALLING 0x00 /* 0000 : Period between falling edge to falling edge */
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#define TBnMR_MR_PMRISING 0x08 /* 0001 : Period between rising edge to rising edge */
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#define TBnMR_MR_PMSVAL 0x00 /* 0010 : Width between edge(s) to edge(s) */
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#define TBnMR_TCK_MASK 0xc0 /* Bits 6-7: Count source select */
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/* Timer Mode: */
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#define TBnMR_TCK_TMF1 0x00 /* 00: f1 or f2 */
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#define TBnMR_TCK_TMF8 0x40 /* 01: f8 */
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#define TBnMR_TCK_TMF32 0x80 /* 10: f32 */
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#define TBnMR_TCK_TMFC32 0xc0 /* 11: fc32 */
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/* Event Counter Mode: */
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#define TBnMR_TCK_ECTBIN 0x00 /* 00: Input from TBnIN pin */
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#define TBnMR_TCK_ECTBOVF 0x80 /* 10: TBj overflow */
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/* Pulse period/pulse width measurement mode: */
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#define TBnMR_TCK_PMF1 0x00 /* 00: f1 or f2 */
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#define TBnMR_TCK_PMF8 0x40 /* 01: f8 */
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#define TBnMR_TCK_PMF32 0x80 /* 10: f32 */
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#define TBnMR_TCK_PMFC32 0xc0 /* 11: fc32 */
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/************************************************************************************
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* Global Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_SH_SRC_M16C_M16C_TIMER_H */
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183
arch/sh/src/m16c/m16c_timerisr.c
Normal file
183
arch/sh/src/m16c/m16c_timerisr.c
Normal file
@ -0,0 +1,183 @@
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/****************************************************************************
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* arch/sh/src/m16c/m16c_timerisr.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
|
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <time.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include "clock_internal.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "m16c_timer.h"
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/****************************************************************************
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* Preprocessor Definitions
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****************************************************************************/
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/* Configuration */
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#ifndef M16C_TA0_PRIO /* Timer A0 interrupt priority */
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# define M16C_TA0_PRIO 5
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#endif
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/* Determine the ideal preload value for the timer.
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*
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* For example, given a 20MHz input frequency and a desired 100 Hz, clock,
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* the ideal reload value would be:
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*
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* 20,000,000 / 100 = 200,000
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*
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* The ideal prescaler value would be the one, then that drops this to exactly
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* 66535:
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*
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* M16C_IDEAL_PRESCALER = 200,000 / 65535 = 3.05
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*
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* And any value greater than 3.05 would also work with less and less precision.
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* The following calculation will produce the ideal prescaler as the next integer
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* value above any fractional values:
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*/
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#define M16C_DIVISOR (65535 * CLK_TCK)
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#define M16C_IDEAL_PRESCALER \
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((M16C_XIN_FREQ + M16C_DIVISOR - 1) / M16C_DIVISOR)
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/* Now, given this idel prescaler value, pick between available choices: 1, 8, and 32 */
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#if M16C_IDEAL_PRESCALER > 8
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# define M16C_PRESCALE_VALUE 32
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# define M16C_PRESCALE_BITS TAnMR_TCK_TMF32
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#elif M16C_IDEL_PRESCALER > 1
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# define M16C_PRESCALE_VALUE 8
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# define M16C_PRESCALE_BITS TAnMR_TCK_TMF8
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#else
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# define M16C_PRESCALE_VALUE 1
|
||||
# define M16C_PRESCALE_BITS TAnMR_TCK_TMF1
|
||||
#endif
|
||||
|
||||
/* Timer 0 Mode Settings */
|
||||
|
||||
#define M16C_TA0MODE_CONFIG \
|
||||
(TAnMR_TMOD_TIMER|TAnMR_MR_TMNOOUT|TAnMR_MR_TMNOGATE|M16C_PRESCALE_BITS)
|
||||
|
||||
/* The actual reload value matching the selected prescaler value */
|
||||
|
||||
#define M16C_RELOAD_VALUE \
|
||||
((M16C_XIN_FREQ / M16C_PRESCALE_VALUE / CLK_TCK) - 1)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Type Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for various portions
|
||||
* of the systems.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_timerisr(int irq, uint32 *regs)
|
||||
{
|
||||
/* Process timer interrupt */
|
||||
|
||||
sched_process_timer();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timerinit
|
||||
*
|
||||
* Description:
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_timerinit(void)
|
||||
{
|
||||
/* Make sure that no timers are running and that all timer interrupts are
|
||||
* disabled.
|
||||
*/
|
||||
|
||||
putreg8(0, M16C_TABSR);
|
||||
putreg8(0, M16C_TA0IC);
|
||||
putreg8(0, M16C_TA1IC);
|
||||
putreg8(0, M16C_TA2IC);
|
||||
putreg8(0, M16C_TA3IC);
|
||||
putreg8(0, M16C_TA4IC);
|
||||
putreg8(0, M16C_TB0IC);
|
||||
putreg8(0, M16C_TB1IC);
|
||||
putreg8(0, M16C_TB2IC);
|
||||
|
||||
/* Set up timer 0 mode register for timer mode with the calculated prescaler value */
|
||||
|
||||
putreg8(M16C_TA0MODE_CONFIG, M16C_TA0MR);
|
||||
|
||||
/* Set the calculated reload value */
|
||||
|
||||
putreg16(M16C_RELOAD_VALUE, M16C_TA0);
|
||||
|
||||
/* Attach the interrupt handler */
|
||||
|
||||
irq_attach(M16C_SYSTIMER_IRQ, (xcpt_t)up_timerisr);
|
||||
|
||||
/* Enable timer interrupts */
|
||||
|
||||
putreg8(1, M16C_TA0IC);
|
||||
|
||||
/* Set the interrupt priority */
|
||||
|
||||
putreg8(M16C_TA0_PRIO, M16C_TA0IC);
|
||||
|
||||
/* Start the timer */
|
||||
|
||||
putreg8(TABSR_TA0S, M16C_TABSR);
|
||||
}
|
||||
@ -51,7 +51,7 @@
|
||||
|
||||
/* Xin Freq */
|
||||
|
||||
#define XIN_FREQ 20e6 /* 20MHz */
|
||||
#define M16C_XIN_FREQ 20000000 /* 20MHz */
|
||||
|
||||
/* Switches */
|
||||
|
||||
@ -67,10 +67,39 @@
|
||||
#define YLW_LED p7_4
|
||||
#define GRN_LED p7_2
|
||||
|
||||
#define RED_DDR pd8_0 // LED port direction register
|
||||
#define RED_DDR pd8_0 /* LED port direction register */
|
||||
#define YLW_DDR pd7_4
|
||||
#define GRN_DDR pd7_2
|
||||
|
||||
/* Define any of the following to specify interrupt priorities. A default
|
||||
* value of 5 will be used for any unspecified values
|
||||
*/
|
||||
|
||||
#undef M16C_INT3_PRIO /* INT3 interrupt priority */
|
||||
#undef M16C_INT5_PRIO /* INT5 interrupt priority */
|
||||
#undef M16C_INT4_PRIO /* INT4 interrupt priority */
|
||||
#undef M16C_BCN_PRIO /* Bus collision detection interrupt priority */
|
||||
#undef M16C_DM0_PRIO /* DMA0 interrupt priority */
|
||||
#undef M16C_DM1_PRIO /* DMA1 interrupt priority */
|
||||
#undef M16C_KUP_PRIO /* Key input interrupt priority */
|
||||
#undef M16C_AD_PRIO /* A-D conversion interrupt priority */
|
||||
#undef M16C_S2T_PRIO /* UART2 transmit interrupt priority */
|
||||
#undef M16C_S2R_PRIO /* UART2 receive interrupt priority */
|
||||
#undef M16C_S0T_PRIO /* UART0 transmit interrupt priority */
|
||||
#undef M16C_S0R_PRIO /* UART0 receive interrupt priority */
|
||||
#undef M16C_S1T_PRIO /* UART1 transmit interrupt priority */
|
||||
#undef M16C_S1R_PRIO /* UART1 receive interrupt priority */
|
||||
#define M16C_TA0_PRIO 5 /* Timer A0 interrupt priority */
|
||||
#undef M16C_TA1_PRIO /* Timer A1 interrupt priority */
|
||||
#undef M16C_TA2_PRIO /* Timer A2 interrupt priority */
|
||||
#undef M16C_TA3_PRIO /* Timer A3 interrupt priority */
|
||||
#undef M16C_TA4_PRIO /* Timer A4 interrupt priority */
|
||||
#undef M16C_TB0_PRIO /* Timer B0 interrupt priority */
|
||||
#undef M16C_TB1_PRIO /* Timer B1 interrupt priority */
|
||||
#undef M16C_TB2_PRIO /* Timer B2 interrupt priority */
|
||||
#undef M16C_INT0_PRIO /* INT0 interrupt priority */
|
||||
#undef M16C_INT1_PRIO /* INT1 interrupt priority */
|
||||
|
||||
/********************************************************************************/
|
||||
/* Macro Definitions */
|
||||
/********************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user