add support for LSE oscillator configuration; requires also initial support of PWR control block
This commit is contained in:
ziggurat29
parent
cc53b25dbd
commit
5bd7b7b54c
@ -115,7 +115,7 @@ CHIP_ASRCS =
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CHIP_CSRCS = stm32l4_allocateheap.c stm32l4_exti_gpio.c stm32l4_gpio.c
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CHIP_CSRCS += stm32l4_idle.c stm32l4_irq.c stm32l4_lowputc.c stm32l4_rcc.c
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CHIP_CSRCS += stm32l4_serial.c stm32l4_start.c stm32l4_waste.c
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CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c
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CHIP_CSRCS += stm32l4_spi.c stm32l4_i2c.c stm32l4_lse.c stm32l4_pwr.c
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ifneq ($(CONFIG_SCHED_TICKLESS),y)
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CHIP_CSRCS += stm32l4_timerisr.c
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108
arch/arm/src/stm32l4/stm32l4_lse.c
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108
arch/arm/src/stm32l4/stm32l4_lse.c
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@ -0,0 +1,108 @@
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/****************************************************************************
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* arch/arm/src/stm32l4/stm32l4_lse.c
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*
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* Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
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* Author: dev@ziggurat29.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "up_arch.h"
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#include "stm32l4_pwr.h"
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#include "stm32l4_rcc.h"
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#include "stm32l4_waste.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: stm32l4_rcc_enablelse
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*
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* Description:
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* Enable the External Low-Speed (LSE) oscillator.
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*
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* Todo:
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* Check for LSE good timeout and return with -1,
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*
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****************************************************************************/
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void stm32l4_rcc_enablelse(void)
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{
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bool bkpenabled;
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uint32_t regval;
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/* The LSE is in the RTC domain and write access is denied to this domain
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* after reset, you have to enable write access using DBP bit in the PWR CR
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* register before to configuring the LSE.
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*/
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bkpenabled = stm32l4_pwr_enablebkp(true);
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/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
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* the RCC BDCR register.
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*/
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regval = getreg32(STM32L4_RCC_BDCR);
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regval |= RCC_BDCR_LSEON|RCC_BDCR_LSEDRV_MIDHI;
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putreg32(regval,STM32L4_RCC_BDCR);
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/* Wait for the LSE clock to be ready */
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while (((regval = getreg32(STM32L4_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0)
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{
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up_waste();
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}
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/* Disable backup domain access if it was disabled on entry */
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if (!bkpenabled)
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{
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(void)stm32l4_pwr_enablebkp(false);
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}
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}
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174
arch/arm/src/stm32l4/stm32l4_pwr.c
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174
arch/arm/src/stm32l4/stm32l4_pwr.c
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@ -0,0 +1,174 @@
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/************************************************************************************
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* arch/arm/src/stm32l4/stm32l4_pwr.c
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
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* Authors: Uros Platise <uros.platise@isotel.eu>
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* Gregory Nutt <gnutt@nuttx.org>
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* dev@ziggurat29.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include "up_arch.h"
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#include "stm32l4_pwr.h"
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#include "stm32l4_rcc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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static inline uint16_t stm32l4_pwr_getreg(uint8_t offset)
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{
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return (uint16_t)getreg32(STM32L4_PWR_BASE + (uint32_t)offset);
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}
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static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value)
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{
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putreg32((uint32_t)value, STM32L4_PWR_BASE + (uint32_t)offset);
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}
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static inline void stm32l4_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits)
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{
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modifyreg32(STM32L4_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits);
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}
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: enableclk
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*
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* Description:
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* Enable/disable the clock to the power control peripheral. Enabling must be done
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* after the APB1 clock is validly configured, and prior to using any functionality
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* controlled by the PWR block (i.e. much of anything else provided by this module).
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*
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* Input Parameters:
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* enable - True: enable the clock to the Power control (PWR) block.
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*
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* Returned Value:
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* True: the PWR block was previously enabled.
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*
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************************************************************************************/
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bool stm32l4_pwr_enableclk(bool enable)
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{
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uint32_t regval;
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bool wasenabled;
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regval = getreg32(STM32L4_RCC_APB1ENR1);
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wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0);
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/* Power interface clock enable.
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*/
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if (wasenabled && !enable)
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{
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/* Disable power interface clock */
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regval &= ~RCC_APB1ENR1_PWREN;
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putreg32(STM32L4_RCC_APB1ENR1, regval);
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}
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else if (!wasenabled && enable)
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{
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/* Enable power interface clock */
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regval |= RCC_APB1ENR1_PWREN;
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putreg32(STM32L4_RCC_APB1ENR1, regval);
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}
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return wasenabled;
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}
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/************************************************************************************
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* Name: stm32l4_pwr_enablebkp
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*
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* Description:
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* Enables access to the backup domain (RTC registers, RTC backup data registers
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* and backup SRAM).
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*
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* Input Parameters:
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* writable - True: enable ability to write to backup domain registers
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*
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* Returned Value:
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* True: The backup domain was previously writable.
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*
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************************************************************************************/
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bool stm32l4_pwr_enablebkp(bool writable)
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{
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uint16_t regval;
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bool waswritable;
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/* Get the current state of the STM32 PWR control register */
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regval = stm32l4_pwr_getreg(STM32L4_PWR_CR1_OFFSET);
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waswritable = ((regval & PWR_CR1_DBP) != 0);
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/* Enable or disable the ability to write */
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if (waswritable && !writable)
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{
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/* Disable backup domain access */
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regval &= ~PWR_CR1_DBP;
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stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval);
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}
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else if (!waswritable && writable)
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{
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/* Enable backup domain access */
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regval |= PWR_CR1_DBP;
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stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval);
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/* Enable does not happen right away */
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up_udelay(4);
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}
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return waswritable;
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}
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@ -0,0 +1,111 @@
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/************************************************************************************
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* arch/arm/src/stm32l4/stm32l4_pwr.h
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*
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* Copyright (C) 2009, 2013, 2015 Gregory Nutt. All rights reserved.
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* Author: dev@ziggurat29.com
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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||||
* without specific prior written permission.
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||||
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H
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#define __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdbool.h>
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#include "chip.h"
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#include "chip/stm32l4_pwr.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: enableclk
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*
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* Description:
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* Enable/disable the clock to the power control peripheral. Enabling must be done
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* after the APB1 clock is validly configured, and prior to using any functionality
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* controlled by the PWR block (i.e. much of anything else provided by this module).
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*
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* Input Parameters:
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* enable - True: enable the clock to the Power control (PWR) block.
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*
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* Returned Value:
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* True: the PWR block was previously enabled.
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*
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************************************************************************************/
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bool stm32l4_pwr_enableclk(bool enable);
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/************************************************************************************
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* Name: stm32l4_pwr_enablebkp
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*
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* Description:
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* Enables access to the backup domain (RTC registers, RTC backup data registers
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* and backup SRAM).
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*
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* Input Parameters:
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* writable - True: enable ability to write to backup domain registers
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*
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* Returned Value:
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* True: The backup domain was previously writable.
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*
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************************************************************************************/
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bool stm32l4_pwr_enablebkp(bool writable);
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PWR_H */
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@ -621,14 +621,17 @@ static void stm32l4_stdclockconfig(void)
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{
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#warning todo: regulator voltage according to clock freq
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#if 0
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/* Select regulator voltage output Scale 1 mode to support system
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* frequencies up to 168 MHz.
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/* ensure Power control is enabled before modifying it
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*/
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regval = getreg32(STM32L4_RCC_APB1ENR);
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regval |= RCC_APB1ENR_PWREN;
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putreg32(regval, STM32L4_RCC_APB1ENR);
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/* Select regulator voltage output Scale 1 mode to support system
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* frequencies up to 168 MHz.
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*/
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regval = getreg32(STM32L4_PWR_CR);
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regval &= ~PWR_CR_VOS_MASK;
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regval |= PWR_CR_VOS_SCALE_1;
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@ -808,11 +811,26 @@ static void stm32l4_stdclockconfig(void)
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stm32l4_rcc_enablelsi();
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#endif
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#if defined(CONFIG_RTC_LSECLOCK)
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#if defined(STM32L4_USE_LSE)
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/* Low speed external clock source LSE
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*
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* TODO: There is another case where the LSE needs to
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* be enabled: if the MCO1 pin selects LSE as source.
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* XXX and other cases, like automatic trimming of MSI for USB use
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*/
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/* ensure Power control is enabled since it is indirectly required
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* to alter the LSE parameters.
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*/
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stm32l4_pwr_enableclk(true);
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/* XXX other LSE settings must be made before turning on the oscillator
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* and we need to ensure it is first off before doing so.
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*/
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/* turn on the LSE oscillator
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* XXX this will almost surely get moved since we also want to use
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* this for automatically trimming MSI, etc.
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*/
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stm32l4_rcc_enablelse();
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