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stm32u5: Architecture Support for STM32U5

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Architecture support for STMicroelectronics STMU585xx MCUs.  This is
based on corresponding code for STM32L5, but has been considerably
adjusted.  Tested with a B-U585I-IOT02A board and a simple NSH
configuration, but only running NuttX in the non-secure world with
TrustedFirmware-M.

Signed-off-by: Michael Jung <mijung@gmx.net>
This commit is contained in:
Michael Jung 2022-02-12 08:20:38 +01:00 committed by Xiang Xiao
parent 64130b4775
commit 5c1c939cdc
63 changed files with 24935 additions and 1 deletions
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21
arch/arm/Kconfig
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@ -411,7 +411,22 @@ config ARCH_CHIP_STM32L5
select ARM_HAVE_MPU_UNIFIED
select ARMV8M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M33).
STMicro STM32 L5 architectures (ARM Cortex-M33).
config ARCH_CHIP_STM32U5
bool "STMicro STM32 U5"
select ARCH_CORTEXM33
select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_SPI_BITORDER
select ARCH_HAVE_TICKLESS
select ARM_HAVE_MPU_UNIFIED
select ARMV8M_HAVE_STACKCHECK
select ARCH_HAVE_TRUSTZONE
---help---
STMicro STM32 U5 architectures (ARM Cortex-M33).
config ARCH_CHIP_STR71X
bool "STMicro STR71x"
@ -830,6 +845,7 @@ config ARCH_CHIP
default "stm32h7" if ARCH_CHIP_STM32H7
default "stm32l4" if ARCH_CHIP_STM32L4
default "stm32l5" if ARCH_CHIP_STM32L5
default "stm32u5" if ARCH_CHIP_STM32U5
default "str71x" if ARCH_CHIP_STR71X
default "tms570" if ARCH_CHIP_TMS570
default "xmc4" if ARCH_CHIP_XMC4
@ -1180,6 +1196,9 @@ endif
if ARCH_CHIP_STM32L5
source "arch/arm/src/stm32l5/Kconfig"
endif
if ARCH_CHIP_STM32U5
source "arch/arm/src/stm32u5/Kconfig"
endif
if ARCH_CHIP_STR71X
source "arch/arm/src/str71x/Kconfig"
endif

82
arch/arm/include/stm32u5/chip.h Normal file
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@ -0,0 +1,82 @@
/****************************************************************************
* arch/arm/include/stm32u5/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32U5_CHIP_H
#define __ARCH_ARM_INCLUDE_STM32U5_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
#if defined(CONFIG_STM32U5_STM32U585XX)
# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (64*1024) /* 64kB SRAM2 on AHB bus Matrix */
# define STM32_SRAM3_SIZE (512*1024) /* 512kB SRAM3 on AHB bus Matrix */
#else
# error "Unsupported STM32U5 chip"
#endif
#if defined(CONFIG_STM32U5_STM32U585XX)
# define STM32_NFSMC 1 /* Have FSMC memory controller */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */
# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NUART 2 /* UART 4-5 */
# define STM32_NUSART 3 /* USART 1-3 */
# define STM32_NLPUART 1 /* LPUART 1 */
# define STM32_QSPI 0 /* No QuadSPI1 */
# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2C 4 /* I2C1-4 */
# define STM32_NSWPMI 0 /* No SWPMI1 */
# define STM32_NUSBOTGFS 1 /* USB OTG FS */
# define STM32_NUSBFS 0 /* No USB FS */
# define STM32_NCAN 1 /* CAN1 */
# define STM32_NSAI 2 /* SAI1-2 */
# define STM32_NSDMMC 1 /* SDMMC interface */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */
# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */
# define STM32_NDAC 2 /* 12-bit DAC1-2 */
# define STM32_NCRC 1 /* CRC */
# define STM32_NCOMP 2 /* Comparators */
# define STM32_NOPAMP 2 /* Operational Amplifiers */
#endif /* CONFIG_STM32U5_STM32U585XX */
/* NVIC priority levels *****************************************************/
/* 16 Programmable interrupt levels */
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#endif /* __ARCH_ARM_INCLUDE_STM32U5_CHIP_H */

40
arch/arm/include/stm32u5/irq.h Normal file
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@ -0,0 +1,40 @@
/****************************************************************************
* arch/arm/include/stm32u5/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_STM32U5_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32U5_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_STM32U5_STM32U585XX)
# include <arch/stm32u5/stm32u585xx_irq.h>
#else
# error "Unsupported STM32U5 chip"
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32U5_IRQ_H */

95
arch/arm/include/stm32u5/stm32_irq.h Normal file
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@ -0,0 +1,95 @@
/****************************************************************************
* arch/arm/include/stm32u5/stm32_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directed but, rather,
* only indirectly by the chip type specific header files
* (e.g. stm32u585xx_irq.h)
*/
#ifndef __ARCH_ARM_INCLUDE_STM32U5_STM32_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32U5_STM32_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers.
* The IRQ number corresponds vector number and hence map directly to bits
* in the NVIC. This does, however, waste several words of memory in the
* IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16).
* These definitions are chip-specific
*/
#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32U5_STM32_IRQ_H */

194
arch/arm/include/stm32u5/stm32u585xx_irq.h Normal file
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@ -0,0 +1,194 @@
/****************************************************************************
* arch/arm/include/stm32u5/stm32u585xx_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_STM32U5_STM32U585XX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32U5_STM32U585XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/stm32u5/stm32_irq.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
* memory in the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in the file nuttx/arch/arm/include/stm32u5/stm32_irq.h, which is
* included above.
*
* External interrupts (vectors >= 16)
*
* These interrupt vectors were implemented based on RM0456 Table 153
* (STM32U575/585 vector table) and should work for STM32U575xx and
* STL32U585xx.
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD_PVM (STM32_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */
#define STM32_IRQ_RTC (STM32_IRQ_FIRST + 2) /* 2: RTC global interrupts */
#define STM32_IRQ_RTC_S (STM32_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */
#define STM32_IRQ_TAMP (STM32_IRQ_FIRST + 4) /* 4: Tamper global interrupt */
#define STM32_IRQ_RAMCFG (STM32_IRQ_FIRST + 5) /* 5: RAM configuration global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */
#define STM32_IRQ_FLASH_S (STM32_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */
#define STM32_IRQ_GTZC (STM32_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 9) /* 9: RCC global interrupt */
#define STM32_IRQ_RCC_S (STM32_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */
#define STM32_IRQ_EXTI5 (STM32_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */
#define STM32_IRQ_EXTI6 (STM32_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */
#define STM32_IRQ_EXTI7 (STM32_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */
#define STM32_IRQ_EXTI8 (STM32_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */
#define STM32_IRQ_EXTI9 (STM32_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */
#define STM32_IRQ_EXTI10 (STM32_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */
#define STM32_IRQ_EXTI11 (STM32_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */
#define STM32_IRQ_EXTI12 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */
#define STM32_IRQ_EXTI13 (STM32_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */
#define STM32_IRQ_EXTI14 (STM32_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */
#define STM32_IRQ_EXTI15 (STM32_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */
#define STM32_IRQ_IWDG (STM32_IRQ_FIRST + 27) /* 27: Independent watchdog interrupt */
#define STM32_IRQ_SAES (STM32_IRQ_FIRST + 28) /* 28: Secure AES */
#define STM32_IRQ_GPDMA1_CH0 (STM32_IRQ_FIRST + 29) /* 29: GPDMA1 Channel 0 global interrupt */
#define STM32_IRQ_GPDMA1_CH1 (STM32_IRQ_FIRST + 30) /* 30: GPDMA1 Channel 1 global interrupt */
#define STM32_IRQ_GPDMA1_CH2 (STM32_IRQ_FIRST + 31) /* 31: GPDMA1 Channel 2 global interrupt */
#define STM32_IRQ_GPDMA1_CH3 (STM32_IRQ_FIRST + 32) /* 32: GPDMA1 Channel 3 global interrupt */
#define STM32_IRQ_GPDMA1_CH4 (STM32_IRQ_FIRST + 33) /* 33: GPDMA1 Channel 4 global interrupt */
#define STM32_IRQ_GPDMA1_CH5 (STM32_IRQ_FIRST + 34) /* 34: GPDMA1 Channel 5 global interrupt */
#define STM32_IRQ_GPDMA1_CH6 (STM32_IRQ_FIRST + 35) /* 35: GPDMA1 Channel 6 global interrupt */
#define STM32_IRQ_GPDMA1_CH7 (STM32_IRQ_FIRST + 36) /* 36: GPDMA1 Channel 7 global interrupt */
#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 37) /* 37: ADC1 (14 bits) global interrupt */
#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST + 38) /* 38: DAC1 global interrupt */
#define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1 Interrupt 0 */
#define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1 Interrupt 1 */
#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */
#define STM32_IRQ_TIM1_TERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 transition error */
#define STM32_IRQ_TIM1_IERR (STM32_IRQ_FIRST + 41) /* 41: TIM1 index error */
#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */
#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */
#define STM32_IRQ_TIM1_DIR (STM32_IRQ_FIRST + 43) /* 43: TIM1 direction change interrupt */
#define STM32_IRQ_TIM1_IDX (STM32_IRQ_FIRST + 43) /* 43: TIM1 index */
#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */
#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */
#define STM32_IRQ_TIM8_TERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 transition error */
#define STM32_IRQ_TIM8_IERR (STM32_IRQ_FIRST + 51) /* 51: TIM8 index error */
#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */
#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */
#define STM32_IRQ_TIM8_DIR (STM32_IRQ_FIRST + 53) /* 53: TIM8 direction change interrupt */
#define STM32_IRQ_TIM8_IDX (STM32_IRQ_FIRST + 53) /* 53: TIM8 index */
#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */
#define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */
#define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */
#define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */
#define STM32_IRQ_I2C2_ER (STM32_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 61) /* 61: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 62) /* 62: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 63) /* 63: USART3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 64) /* 64: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 65) /* 65: UART5 global interrupt */
#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */
#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */
#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */
#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */
#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */
#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */
#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */
#define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS global interrupt */
#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 74) /* 74: CRS global interrupt */
#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 75) /* 75: FMC global interrupt */
#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */
#define STM32_PWER_S3WU (STM32_IRQ_FIRST + 77) /* 77: PWR wakeup from Stop 3 interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST + 79) /* 79: SDMMC2 global interrupt */
#define STM32_IRQ_GPDMA1_CH8 (STM32_IRQ_FIRST + 80) /* 80: GPDMA1 Channel 8 interrupt */
#define STM32_IRQ_GPDMA1_CH9 (STM32_IRQ_FIRST + 81) /* 81: GPDMA1 Channel 9 interrupt */
#define STM32_IRQ_GPDMA1_CH10 (STM32_IRQ_FIRST + 82) /* 82: GPDMA1 Channel 10 interrupt */
#define STM32_IRQ_GPDMA1_CH11 (STM32_IRQ_FIRST + 83) /* 83: GPDMA1 Channel 11 interrupt */
#define STM32_IRQ_GPDMA1_CH12 (STM32_IRQ_FIRST + 84) /* 84: GPDMA1 Channel 12 interrupt */
#define STM32_IRQ_GPDMA1_CH13 (STM32_IRQ_FIRST + 85) /* 85: GPDMA1 Channel 13 interrupt */
#define STM32_IRQ_GPDMA1_CH14 (STM32_IRQ_FIRST + 86) /* 86: GPDMA1 Channel 14 interrupt */
#define STM32_IRQ_GPDMA1_CH15 (STM32_IRQ_FIRST + 87) /* 87: GPDMA1 Channel 15 interrupt */
#define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */
#define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 92) /* 92: TSC global interrupt */
#define STM32_IRQ_AES (STM32_IRQ_FIRST + 93) /* 93: AES global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 94) /* 94: RNG global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 95) /* 95: FPU global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 96) /* 96: HASH global interrupt */
#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 97) /* 97: PKA global interrupt */
#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */
#define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */
#define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */
#define STM32_IRQ_MDF1_FLT0 (STM32_IRQ_FIRST + 102) /* 102: MDF1 filter 0 global interrupt */
#define STM32_IRQ_MDF1_FLT1 (STM32_IRQ_FIRST + 103) /* 103: MDF1 filter 1 global interrupt */
#define STM32_IRQ_MDF1_FLT2 (STM32_IRQ_FIRST + 104) /* 104: MDF1 filter 2 global interrupt */
#define STM32_IRQ_MDF1_FLT3 (STM32_IRQ_FIRST + 105) /* 105: MDF1 filter 3 global interrupt */
#define STM32_IRQ_UCPD1 (STM32_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */
#define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */
#define STM32_IRQ_OTFDEC1 (STM32_IRQ_FIRST + 108) /* 108: OTFDEC1 secure global interrupt */
#define STM32_IRQ_OTFDEC2 (STM32_IRQ_FIRST + 109) /* 109: OTFDEC2 secure global interrupt */
#define STM32_IRQ_LPTIM4 (STM32_IRQ_FIRST + 110) /* 110: LPTIM4 global interrupt */
#define STM32_IRQ_DCACHE1 (STM32_IRQ_FIRST + 111) /* 111: Data cache global interrupt */
#define STM32_IRQ_ADF1_FLT0 (STM32_IRQ_FIRST + 112) /* 112: ADF1 filter 0 global interrupt */
#define STM32_IRQ_ADC4 (STM32_IRQ_FIRST + 113) /* 113: ADC4 (12 bits) global interrupt */
#define STM32_IRQ_LPDMA1_CH0 (STM32_IRQ_FIRST + 114) /* 114: LPDMA1 SmartRun channel 0 global interrupt */
#define STM32_IRQ_LPDMA1_CH1 (STM32_IRQ_FIRST + 115) /* 115: LPDMA1 SmartRun channel 1 global interrupt */
#define STM32_IRQ_LPDMA1_CH2 (STM32_IRQ_FIRST + 116) /* 116: LPDMA1 SmartRun channel 2 global interrupt */
#define STM32_IRQ_LPDMA1_CH3 (STM32_IRQ_FIRST + 117) /* 117: LPDMA1 SmartRun channel 3 global interrupt */
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 118) /* 118: DMA2D global interrupt */
#define STM32_IRQ_DCMI_PSSI (STM32_IRQ_FIRST + 119) /* 119: DCMI/PSSI global interrupt */
#define STM32_IRQ_OCTOSPI2 (STM32_IRQ_FIRST + 120) /* 120: OCTOSPI2 global interrupt */
#define STM32_IRQ_MDF1_FLT4 (STM32_IRQ_FIRST + 121) /* 121: MDF1 filter 4 global interrupt */
#define STM32_IRQ_MDF1_FLT5 (STM32_IRQ_FIRST + 122) /* 122: MDF1 filter 5 global interrupt */
#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 123) /* 123: CORDIC interrupt */
#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 124) /* 124: FMAC interrupt */
#if defined(CONFIG_STM32U5_STM32U585XX)
# define STM32_IRQ_NEXTINTS 125
#else
# error "Unsupported STM32U5 chip"
#endif
/* (EXTI interrupts do not use IRQ numbers) */
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
#endif /* __ARCH_ARM_INCLUDE_STM32U5_STM32U585XX_IRQ_H */

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##############################################################################
# arch/arm/src/stm32u5/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
##############################################################################
# The start-up, "head", file. Only common vectors are support so there
# isn't one.
HEAD_ASRC =
# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
CMN_UASRCS =
CMN_UCSRCS =
CMN_ASRCS = arm_saveusercontext.S arm_fullcontextrestore.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
CMN_CSRCS = arm_assert.c arm_blocktask.c arm_copyfullstate.c arm_createstack.c
CMN_CSRCS += arm_doirq.c arm_exit.c arm_hardfault.c arm_initialize.c
CMN_CSRCS += arm_initialstate.c arm_interruptcontext.c arm_mdelay.c arm_memfault.c
CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c
CMN_CSRCS += arm_releasepending.c arm_releasestack.c arm_reprioritizertr.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c arm_stackframe.c
CMN_CSRCS += arm_svcall.c arm_systemreset.c arm_trigger_irq.c arm_udelay.c
CMN_CSRCS += arm_unblocktask.c arm_usestack.c arm_vfork.c arm_switchcontext.c
CMN_CSRCS += arm_puts.c
# Configuration-dependent common files
ifeq ($(CONFIG_ARMV8M_STACKCHECK),y)
CMN_CSRCS += arm_stackcheck.c
endif
ifeq ($(CONFIG_ARMV8M_LAZYFPU),y)
CMN_ASRCS += arm_lazyexception.S
else
CMN_ASRCS += arm_exception.S
endif
CMN_CSRCS += arm_vectors.c
ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += arm_fpu.S
CMN_CSRCS += arm_copyarmstate.c
endif
ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += arm_ramvec_initialize.c arm_ramvec_attach.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += arm_mpu.c arm_task_start.c arm_pthread_start.c
CMN_CSRCS += arm_pthread_exit.c
CMN_CSRCS += arm_signal_dispatch.c
CMN_UASRCS += arm_signal_handler.S
endif
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += arm_checkstack.c
endif
# Required STM32U5 files
CHIP_ASRCS =
CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c
CHIP_CSRCS += stm32_serial.c stm32_start.c stm32_waste.c stm32_uid.c
CHIP_CSRCS += stm32_spi.c stm32_lse.c stm32_lsi.c
CHIP_CSRCS += stm32_pwr.c stm32_tim.c stm32_flash.c stm32_timerisr.c
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += stm32_idle.c
endif
ifeq ($(CONFIG_TIMER),y)
CHIP_CSRCS += stm32_tim_lowerhalf.c
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y)
CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y)
CHIP_CSRCS += stm32_dumpgpio.c
endif
# Required chip type specific files
ifeq ($(CONFIG_STM32U5_STM32U585XX),y)
CHIP_CSRCS += stm32u585xx_rcc.c
endif

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This is a port of NuttX to the STM32U5 Family
Used development board is the B-U585I-IOT02A
Most code is copied and adapted from the STM32L5 port.
The only supported STM32U5 family currently is:
-----------------------------------------------------------------
| NuttX config | Manual | Chips
| STM32U5 | RM0456 | STM32U575xx and STM32U585xx
------------------------------------------------------------------
TODO list
---------
Extensive testing. Only initial sniff tests have been done.
A prober TODO list should be generated.
References
----------
[RM0456] STMicroelectronics, STM32U575/585 Arm(R)-based 32-bit MCUs, Rev 2

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/****************************************************************************
* arch/arm/src/stm32u5/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_CHIP_H
#define __ARCH_ARM_SRC_STM32U5_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the memory map and the chip definitions file. Other chip hardware
* files should then include this file for the proper setup.
*/
#include <arch/irq.h>
#include <arch/stm32u5/chip.h>
#include "hardware/stm32_pinmap.h"
#include "hardware/stm32_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If the common ARMv8-M vector handling logic is used, then it expects the
* following definition in this file that provides the number of supported
* external interrupts which, for this architecture, is provided in the
* arch/stm32u5/chip.h header file.
*/
#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
#endif /* __ARCH_ARM_SRC_STM32U5_CHIP_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_exti.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_EXTI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */
#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */
#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */
#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */
#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */
#define STM32_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */
#define STM32_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */
#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */
#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */
#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */
#define STM32_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */
#define STM32_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */
#define STM32_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */
#define STM32_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */
#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */
#define STM32_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */
#define STM32_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */
#define STM32_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */
#define STM32_EXTI_LOCKR_OFFSET 0x0070 /* Lock */
#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */
#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */
#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */
#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */
/* Register Addresses *******************************************************/
#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET)
#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET)
#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET)
#define STM32_EXTI_RPR1 (STM32_EXTI_BASE + STM32_EXTI_RPR1_OFFSET)
#define STM32_EXTI_FPR1 (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET)
#define STM32_EXTI_SECCFGR1 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR1_OFFSET)
#define STM32_EXTI_PRIVCFGR1 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR1_OFFSET)
#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET)
#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET)
#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET)
#define STM32_EXTI_RPR2 (STM32_EXTI_BASE + STM32_EXTI_RPR2_OFFSET)
#define STM32_EXTI_FPR2 (STM32_EXTI_BASE + STM32_EXTI_FPR2_OFFSET)
#define STM32_EXTI_SECCFGR2 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR2_OFFSET)
#define STM32_EXTI_PRIVCFGR2 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR2_OFFSET)
#define STM32_EXTI_EXTICR1 (STM32_EXTI_BASE + STM32_EXTI_EXTICR1_OFFSET)
#define STM32_EXTI_EXTICR2 (STM32_EXTI_BASE + STM32_EXTI_EXTICR2_OFFSET)
#define STM32_EXTI_EXTICR3 (STM32_EXTI_BASE + STM32_EXTI_EXTICR3_OFFSET)
#define STM32_EXTI_EXTICR4 (STM32_EXTI_BASE + STM32_EXTI_EXTICR4_OFFSET)
#define STM32_EXTI_LOCKR (STM32_EXTI_BASE + STM32_EXTI_LOCKR_OFFSET)
#define STM32_EXTI_IMR1 (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET)
#define STM32_EXTI_EMR1 (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET)
#define STM32_EXTI_IMR2 (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET)
#define STM32_EXTI_EMR2 (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* EXTI lines > 15 are associated with internal devices: */
#define EXTI1_PVD (1 << 16) /* EXTI line 16: PVD output */
#define EXTI1_RTC (1 << 17) /* EXTI line 17: RTC */
#define EXTI1_RTC_SECURE (1 << 18) /* EXTI line 18: RTC secure */
#define EXTI1_TAMP (1 << 19) /* EXTI line 19: TAMP */
#define EXTI1_TAMP_SECURE (1 << 20) /* EXTI line 20: TAMP secure */
#define EXTI1_COMP1 (1 << 21) /* EXTI line 21: COMP1 output */
#define EXTI1_COMP2 (1 << 22) /* EXTI line 22: COMP2 output */
#define EXTI1_I2C1 (1 << 23) /* EXTI line 23: I2C1 wakeup */
#define EXTI1_I2C2 (1 << 24) /* EXTI line 24: I2C2 wakeup */
#define EXTI1_I2C3 (1 << 25) /* EXTI line 25: I2C3 wakeup */
#define EXTI1_USART1 (1 << 26) /* EXTI line 26: USART1 wakeup */
#define EXTI1_USART2 (1 << 27) /* EXTI line 27: USART2 wakeup */
#define EXTI1_USART3 (1 << 28) /* EXTI line 28: USART3 wakeup */
#define EXTI1_USART4 (1 << 29) /* EXTI line 29: USART4 wakeup */
#define EXTI1_USART5 (1 << 30) /* EXTI line 30: USART5 wakeup */
#define EXTI1_LPUART1 (1 << 31) /* EXTI line 31: LPUART1 wakeup */
#define EXTI2_LPTIM1 (1 << 0) /* EXTI line 32: LPTIM1 */
#define EXTI2_LPTIM2 (1 << 1) /* EXTI line 33: LPTIM2 */
#define EXTI2_USBFS (1 << 2) /* EXTI line 34: USB FS wakeup */
#define EXTI2_PVM1 (1 << 3) /* EXTI line 35: PVM1 wakeup */
#define EXTI2_PVM2 (1 << 4) /* EXTI line 36: PVM2 wakeup */
#define EXTI2_PVM3 (1 << 5) /* EXTI line 37: PVM3 wakeup */
#define EXTI2_PVM4 (1 << 6) /* EXTI line 38: PVM4 wakeup */
#define EXTI2_RSVD (1 << 7) /* EXTI line 39: reserved */
#define EXTI2_I2C4 (1 << 8) /* EXTI line 40: I2C4 wakeup */
#define EXTI2_UCPD1 (1 << 9) /* EXTI line 41: UCPD1 wakeup */
#define EXTI2_LPTIM3 (1 << 10) /* EXTI line 42: LPTIM3 wakeup */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_EXTI_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Flash size is known from the chip selection:
*
* When CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT is set the
* CONFIG_STM32U5_FLASH_CONFIG_x selects the default FLASH size based on
* the chip part number. This value can be overridden with
* CONFIG_STM32U5_FLASH_OVERRIDE_x
*
* Parts STM32U585 and STM32U575 have 2048Kb of FLASH
*/
#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) && \
!defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) && \
!defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) && \
!defined(CONFIG_STM32U5_FLASH_CONFIG_C) && \
!defined(CONFIG_STM32U5_FLASH_CONFIG_E)
# define CONFIG_STM32U5_FLASH_OVERRIDE_E
# warning "Flash size not defined defaulting to 512KiB (E)"
#endif
/* Override of the Flash has been chosen */
#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT)
# undef CONFIG_STM32U5_FLASH_CONFIG_C
# undef CONFIG_STM32U5_FLASH_CONFIG_E
# if defined(CONFIG_STM32U5_FLASH_OVERRIDE_C)
# define CONFIG_STM32U5_FLASH_CONFIG_C
# elif defined(CONFIG_STM32U5_FLASH_OVERRIDE_E)
# define CONFIG_STM32U5_FLASH_CONFIG_E
# endif
#endif
/* Define the valid configuration */
#if defined(CONFIG_STM32U5_FLASH_CONFIG_I) /* 2048 kB */
# define STM32_FLASH_NPAGES 256
# define STM32_FLASH_PAGESIZE 8192
#else
# error "unknown flash configuration!"
#endif
#ifdef STM32_FLASH_PAGESIZE
# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
#endif
/* Register Offsets *********************************************************/
#define STM32_FLASH_ACR_OFFSET 0x0000
#define STM32_FLASH_NSKEYR_OFFSET 0x0008
#define STM32_FLASH_SECKEYR_OFFSET 0x000c
#define STM32_FLASH_OPTKEYR_OFFSET 0x0010
#define STM32_FLASH_PDKEY1R_OFFSET 0x0018
#define STM32_FLASH_PDKEY2R_OFFSET 0x001c
#define STM32_FLASH_NSSR_OFFSET 0x0020
#define STM32_FLASH_SECSR_OFFSET 0x0024
#define STM32_FLASH_NSCR_OFFSET 0x0028
#define STM32_FLASH_SECCR_OFFSET 0x002c
#define STM32_FLASH_ECCR_OFFSET 0x0030
#define STM32_FLASH_OPSR_OFFSET 0x0034
#define STM32_FLASH_OPTR_OFFSET 0x0040
#define STM32_FLASH_NSBOOTADDR0R_OFFSET 0x0044
#define STM32_FLASH_NSBOOTADDR1R_OFFSET 0x0048
#define STM32_FLASH_SECBOOTADDR0R_OFFSET 0x004c
#define STM32_FLASH_SECWM1R1_OFFSET 0x0050
#define STM32_FLASH_SECWM1R2_OFFSET 0x0054
#define STM32_FLASH_WRP1AR_OFFSET 0x0058
#define STM32_FLASH_WRP1BR_OFFSET 0x005c
#define STM32_FLASH_SECWM2R1_OFFSET 0x0060
#define STM32_FLASH_SECWM2R2_OFFSET 0x0064
#define STM32_FLASH_WRP2AR_OFFSET 0x0068
#define STM32_FLASH_WRP2BR_OFFSET 0x006c
#define STM32_FLASH_OEM1KEYR1_OFFSET 0x0070
#define STM32_FLASH_OEM1KEYR2_OFFSET 0x0074
#define STM32_FLASH_OEM2KEYR1_OFFSET 0x0078
#define STM32_FLASH_OEM2KEYR2_OFFSET 0x007c
#define STM32_FLASH_SECBB1R1_OFFSET 0x0080
#define STM32_FLASH_SECBB1R2_OFFSET 0x0084
#define STM32_FLASH_SECBB1R3_OFFSET 0x0088
#define STM32_FLASH_SECBB1R4_OFFSET 0x008c
#define STM32_FLASH_SECBB2R1_OFFSET 0x00a0
#define STM32_FLASH_SECBB2R2_OFFSET 0x00a4
#define STM32_FLASH_SECBB2R3_OFFSET 0x00a8
#define STM32_FLASH_SECBB2R4_OFFSET 0x00ac
#define STM32_FLASH_SECHDPCR_OFFSET 0x00c0
#define STM32_FLASH_PRIVCFGR_OFFSET 0x00c4
#define STM32_FLASH_PRIVBB1R1_OFFSET 0x00d0
#define STM32_FLASH_PRIVBB1R2_OFFSET 0x00d4
#define STM32_FLASH_PRIVBB1R3_OFFSET 0x00d8
#define STM32_FLASH_PRIVBB1R4_OFFSET 0x00dc
#define STM32_FLASH_PRIVBB2R1_OFFSET 0x00f0
#define STM32_FLASH_PRIVBB2R2_OFFSET 0x00f4
#define STM32_FLASH_PRIVBB2R3_OFFSET 0x00f8
#define STM32_FLASH_PRIVBB2R4_OFFSET 0x00fc
/* Register Addresses *******************************************************/
#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET)
#define STM32_FLASH_NSKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSKEYR_OFFSET)
#define STM32_FLASH_SECKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECKEYR_OFFSET)
#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET)
#define STM32_FLASH_PDKEY1R (STM32_FLASHIF_BASE + STM32_FLASH_PDKEY1R_OFFSET)
#define STM32_FLASH_PDKEY2R (STM32_FLASHIF_BASE + STM32_FLASH_PDKEY2R_OFFSET)
#define STM32_FLASH_NSSR (STM32_FLASHIF_BASE + STM32_FLASH_NSSR_OFFSET)
#define STM32_FLASH_SECSR (STM32_FLASHIF_BASE + STM32_FLASH_SECSR_OFFSET)
#define STM32_FLASH_NSCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCR_OFFSET)
#define STM32_FLASH_SECCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCR_OFFSET)
#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE + STM32_FLASH_ECCR_OFFSET)
#define STM32_FLASH_OPSR (STM32_FLASHIF_BASE + STM32_FLASH_OPSR_OFFSET)
#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE + STM32_FLASH_OPTR_OFFSET)
#define STM32_FLASH_NSBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR0R_OFFSET)
#define STM32_FLASH_NSBOOTADDR1R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR1R_OFFSET)
#define STM32_FLASH_SECBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTADDR0R_OFFSET)
#define STM32_FLASH_SECWM1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R1_OFFSET)
#define STM32_FLASH_SECWM1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R2_OFFSET)
#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1AR_OFFSET)
#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1BR_OFFSET)
#define STM32_FLASH_SECWM2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R1_OFFSET)
#define STM32_FLASH_SECWM2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R2_OFFSET)
#define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2AR_OFFSET)
#define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2BR_OFFSET)
#define STM32_FLASH_OEM1KEYR1 (STM32_FLASHIF_BASE + STM32_FLASH_OEM1KEYR1_OFFSET)
#define STM32_FLASH_OEM1KEYR2 (STM32_FLASHIF_BASE + STM32_FLASH_OEM1KEYR2_OFFSET)
#define STM32_FLASH_OEM2KEYR1 (STM32_FLASHIF_BASE + STM32_FLASH_OEM2KEYR1_OFFSET)
#define STM32_FLASH_OEM2KEYR2 (STM32_FLASHIF_BASE + STM32_FLASH_OEM2KEYR2_OFFSET)
#define STM32_FLASH_SECBB1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R1_OFFSET)
#define STM32_FLASH_SECBB1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R2_OFFSET)
#define STM32_FLASH_SECBB1R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R3_OFFSET)
#define STM32_FLASH_SECBB1R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R4_OFFSET)
#define STM32_FLASH_SECBB2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R1_OFFSET)
#define STM32_FLASH_SECBB2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R2_OFFSET)
#define STM32_FLASH_SECBB2R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R3_OFFSET)
#define STM32_FLASH_SECBB2R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R4_OFFSET)
#define STM32_FLASH_SECHDPCR (STM32_FLASHIF_BASE + STM32_FLASH_SECHDPCR_OFFSET)
#define STM32_FLASH_PRIVCFGR (STM32_FLASHIF_BASE + STM32_FLASH_PRIVCFGR_OFFSET)
#define STM32_FLASH_PRIVBB1R1 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R1_OFFSET)
#define STM32_FLASH_PRIVBB1R2 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R2_OFFSET)
#define STM32_FLASH_PRIVBB1R3 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R3_OFFSET)
#define STM32_FLASH_PRIVBB1R4 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB1R4_OFFSET)
#define STM32_FLASH_PRIVBB2R1 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R1_OFFSET)
#define STM32_FLASH_PRIVBB2R2 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R2_OFFSET)
#define STM32_FLASH_PRIVBB2R3 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R3_OFFSET)
#define STM32_FLASH_PRIVBB2R4 (STM32_FLASHIF_BASE + STM32_FLASH_PRIVBB2R4_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* Flash Access Control Register (ACR) */
#define FLASH_ACR_LATENCY_SHIFT (0)
#define FLASH_ACR_LATENCY_MASK (0xF << FLASH_ACR_LATENCY_SHIFT)
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* Latency */
# define FLASH_ACR_LATENCY_0 ( 0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */
# define FLASH_ACR_LATENCY_1 ( 1 << FLASH_ACR_LATENCY_SHIFT) /* 0001: One wait state */
# define FLASH_ACR_LATENCY_2 ( 2 << FLASH_ACR_LATENCY_SHIFT) /* 0010: Two wait states */
# define FLASH_ACR_LATENCY_3 ( 3 << FLASH_ACR_LATENCY_SHIFT) /* 0011: Three wait states */
# define FLASH_ACR_LATENCY_4 ( 4 << FLASH_ACR_LATENCY_SHIFT) /* 0100: Four wait states */
# define FLASH_ACR_LATENCY_5 ( 5 << FLASH_ACR_LATENCY_SHIFT) /* 0101: Five wait states */
# define FLASH_ACR_LATENCY_6 ( 6 << FLASH_ACR_LATENCY_SHIFT) /* 0110: Six wait states */
# define FLASH_ACR_LATENCY_7 ( 7 << FLASH_ACR_LATENCY_SHIFT) /* 0111: Seven wait state */
# define FLASH_ACR_LATENCY_8 ( 8 << FLASH_ACR_LATENCY_SHIFT) /* 1000: Eight wait states */
# define FLASH_ACR_LATENCY_9 ( 9 << FLASH_ACR_LATENCY_SHIFT) /* 1001: Nine wait states */
# define FLASH_ACR_LATENCY_10 (10 << FLASH_ACR_LATENCY_SHIFT) /* 1010: Ten wait states */
# define FLASH_ACR_LATENCY_11 (11 << FLASH_ACR_LATENCY_SHIFT) /* 1011: Eleven wait states */
# define FLASH_ACR_LATENCY_12 (12 << FLASH_ACR_LATENCY_SHIFT) /* 1100: Twelve wait states */
# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait state */
# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen states */
# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */
#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */
#define FLASH_ACR_LPRM (1 << 11) /* Bit 11: Low-power read mode */
#define FLASH_ACR_PDREQ1 (1 << 12) /* Bit 12: Bank 1 power-down mode request */
#define FLASH_ACR_PDREQ2 (1 << 13) /* Bit 13: Bank 2 power-down mode request */
#define FLASH_ACR_SLEEP_PD (1 << 14) /* Bit 14: Flash mode during Sleep */
/* Flash non-secure status register (NSSR) */
#define FLASH_NSSR_EOP (1 << 0) /* Bit 0: Non-secure end of operation */
#define FLASH_NSSR_OPERR (1 << 1) /* Bit 1: Non-secure peration error */
#define FLASH_NSSR_PROGERR (1 << 3) /* Bit 3: Non-secure programming error */
#define FLASH_NSSR_WRPERR (1 << 4) /* Bit 4: Non-secure write protection error */
#define FLASH_NSSR_PGAERR (1 << 5) /* Bit 5: Non-secure rogramming alignment error */
#define FLASH_NSSR_SIZERR (1 << 6) /* Bit 6: Non-secure size error */
#define FLASH_NSSR_PGSERR (1 << 7) /* Bit 7: Non-secure programming sequence error */
#define FLASH_NSSR_OPTWERR (1 << 13) /* Bit 13: Option write error */
#define FLASH_NSSR_BSY (1 << 16) /* Bit 16: Non-secure busy */
#define FLASH_NSSR_WDW (1 << 17) /* Bit 17: Non-secure wait data to write */
#define FLASH_NSSR_OEM1LOCK (1 << 18) /* Bit 18: OEM1 lock */
#define FLASH_NSSR_OEM2LOCK (1 << 19) /* Bit 19: OEM2 lock */
#define FLASH_NSSR_PD1 (1 << 20) /* Bit 20: Bank 1 in power-down mode */
#define FLASH_NSSR_PD2 (1 << 21) /* Bit 21: Bank 2 in power-down mode */
/* Flash non-secure control register (NSCR) */
#define FLASH_NSCR_PG (1 << 0) /* Bit 0 : Non-secure programming */
#define FLASH_NSCR_PER (1 << 1) /* Bit 1 : Non-secure page Erase */
#define FLASH_NSCR_MER1 (1 << 2) /* Bit 2 : Non-secure bank 1 mass erase */
#define FLASH_NSCR_PNB_SHIFT (3) /* Bits 3-9: Non-secure page number selection */
#define FLASH_NSCR_PNB_MASK (0x7F << FLASH_NSCR_PNB_SHIFT)
#define FLASH_NSCR_PNB(n) ((n) << FLASH_NSCR_PNB_SHIFT) /* Page n, n = 0..127 */
#define FLASH_NSCR_BKER (1 << 11) /* Bit 11: Non-secure bank selection for page erase */
#define FLASH_NSCR_BWR (1 << 14) /* Bit 14: Non-secure burst write programming mode */
#define FLASH_NSCR_MER2 (1 << 15) /* Bit 15: Non-secure bank 2 mass erase */
#define FLASH_NSCR_STRT (1 << 16) /* Bit 16: Non-secure start */
#define FLASH_NSCR_OPTSTRT (1 << 17) /* Bit 17: Options modification start */
#define FLASH_NSCR_EOPIE (1 << 24) /* Bit 24: Non-secure end of operation interrupt enable */
#define FLASH_NSCR_ERRIE (1 << 25) /* Bit 25: Non-secure error interrupt enable */
#define FLASH_NSCR_OBL_LAUNCH (1 << 27) /* Bit 27: Force the option byte loading */
#define FLASH_NSCR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */
#define FLASH_NSCR_LOCK (1 << 31) /* Bit 31: Non-secure lock */
/* Flash option register (OPTR) */
#define FLASH_OPTR_RDP_SHIFT 0 /* Bits 0-7: Readout protection level */
#define FLASH_OPTR_RDP_MASK (0xff << FLASH_OPTR_RDP_SHIFT)
#define FLASH_OPTR_RDP_LEVEL_0 (0xaa << FLASH_OPTR_RDP_SHIFT) /* 0xAA: Level 0 (readout protection not active) */
#define FLASH_OPTR_RDP_LEVEL_0_5 (0x55 << FLASH_OPTR_RDP_SHIFT) /* 0x55: Level 0.5 (readout protection not active, only non-secure debug access is possible) */
#define FLASH_OPTR_RDP_LEVEL_1 (0x11 << FLASH_OPTR_RDP_SHIFT) /* Others: Level 1 (memories readout protection active) */
#define FLASH_OPTR_RDP_LEVEL_2 (0xCC << FLASH_OPTR_RDP_SHIFT) /* 0xCC: Level 2 (chip readout protection active) */
#define FLASH_OPTR_BOR_LEVEL_SHIFT 8 /* Bits 8-10: BOR reset level */
#define FLASH_OPTR_BOR_LEVEL_MASK (7 << FLASH_OPTR_BOR_LEVEL_SHIFT)
#define FLASH_OPTR_BOR_LEVEL_0 (0 << FLASH_OPTR_BOR_LEVEL_SHIFT) /* 000: BOR level 0 (reset level threshold around 1.7V) */
#define FLASH_OPTR_BOR_LEVEL_1 (1 << FLASH_OPTR_BOR_LEVEL_SHIFT) /* 001: BOR level 1 (reset level threshold around 2.0V) */
#define FLASH_OPTR_BOR_LEVEL_2 (2 << FLASH_OPTR_BOR_LEVEL_SHIFT) /* 010: BOR level 2 (reset level threshold around 2.2V) */
#define FLASH_OPTR_BOR_LEVEL_3 (3 << FLASH_OPTR_BOR_LEVEL_SHIFT) /* 011: BOR level 3 (reset level threshold around 2.5V) */
#define FLASH_OPTR_BOR_LEVEL_4 (4 << FLASH_OPTR_BOR_LEVEL_SHIFT) /* 100: BOR level 4 (reset level threshold around 2.8V) */
#define FLASH_OPTR_NRST_STOP (1 << 12) /* Bit 12: Reset generation in Stop mode */
#define FLASH_OPTR_NRST_STDBY (1 << 13) /* Bit 13: Reset generation in Standby mode */
#define FLASH_OPTR_NRST_SHDW (1 << 14) /* Bit 14: Reset generation in Shutdown mode */
#define FLASH_OPTR_SRAM1345_RST (1 << 15) /* Bit 15: SRAM1, SRAM3, SRAM4 and SRAM4 erase upon system reset */
#define FLASH_OPTR_IWDG_SW (1 << 16) /* Bit 16: Independent watchdog selection */
#define FLASH_OPTR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */
#define FLASH_OPTR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/
#define FLASH_OPTR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
#define FLASH_OPTR_SWAP_BANK (1 << 20) /* Bit 20: Swap banks */
#define FLASH_OPTR_DUALBANK (1 << 21) /* Bit 21: Dual bank on 1-Mbyte flash memory devices */
#define FLASH_OPTR_BKPRAM_ECC (1 << 22) /* Bit 22: Backup RAM ECC detection and correction enable */
#define FLASH_OPTR_SRAM3_ECC (1 << 23) /* Bit 23: SRAM3 ECC detection and correction enable */
#define FLASH_OPTR_SRAM2_ECC (1 << 24) /* Bit 24: SRAM2 ECC detection and correction enable */
#define FLASH_OPTR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */
#define FLASH_OPTR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */
#define FLASH_OPTR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */
#define FLASH_OPTR_PA15_PUPEN (1 << 28) /* Bit 28: PA15 pull-up enable */
#define FLASH_OPTR_IO_VDD_HSLV (1 << 29) /* Bit 29: High-speed IO at low V_DD voltage configuration bit */
#define FLASH_OPTR_IO_VDDIO2_HSLV (1 << 30) /* Bit 30: High-speed IO at low V_DDIO2 voltage configuration bit */
#define FLASH_OPTR_TZEN (1 << 31) /* Bit 31: Global TrustZone security enable */
#if 0
/* Flash ECC Register (ECCR) */
#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-18: ECC fail address */
#define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT)
#define FLASH_ECCR_BK_ECC (1 << 21) /* Bit 21: ECC fail bank */
#define FLASH_ECCR_SYSF_ECC (1 << 22) /* Bit 22: System Flash ECC fail */
#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */
#define FLASH_ECCR_ECCC2 (1 << 28) /* Bit 28: ECC2 correction */
#define FLASH_ECCR_ECCD2 (1 << 29) /* Bit 29: ECC2 detection */
#define FLASH_ECCR_ECCC (1 << 30) /* Bit 30: ECC correction */
#define FLASH_ECCR_ECCD (1 << 31) /* Bit 31: ECC detection */
#define FLASH_OPTR_BORLEV_SHIFT (8) /* Bits 8-10: BOR reset Level */
#define FLASH_OPTR_BORLEV_MASK (7 << FLASH_OPTR_BORLEV_SHIFT)
#define FLASH_OPTR_VBOR0 (0 << FLASH_OPTR_BORLEV_SHIFT) /* 000: BOR Level 0 (1.7 V) */
#define FLASH_OPTR_VBOR1 (1 << FLASH_OPTR_BORLEV_SHIFT) /* 001: BOR Level 1 (2.0 V) */
#define FLASH_OPTR_VBOR2 (2 << FLASH_OPTR_BORLEV_SHIFT) /* 010: BOR Level 2 (2.2 V) */
#define FLASH_OPTR_VBOR3 (3 << FLASH_OPTR_BORLEV_SHIFT) /* 011: BOR Level 3 (2.5 V) */
#define FLASH_OPTR_VBOR4 (4 << FLASH_OPTR_BORLEV_SHIFT) /* 100: BOR Level 4 (2.8 V) */
#define FLASH_OPTR_RDP_SHIFT (0) /* Bits 0-7: Read Protection Level */
#define FLASH_OPTR_RDP_MASK (0xFF << FLASH_OPTR_RDP_SHIFT)
#define FLASH_OPTR_RDP_NONE (0xAA << FLASH_OPTR_RDP_SHIFT)
#define FLASH_OPTR_RDP_NSDBG (0x55 << FLASH_OPTR_RDP_SHIFT)
#define FLASH_OPTR_RDP_CHIP (0xCC << FLASH_OPTR_RDP_SHIFT) /* WARNING, CANNOT BE REVERSED !! */
#endif
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_FLASH_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/stm32u5/chip.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */
#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */
#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */
#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */
#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */
#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */
#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */
#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */
#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */
#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */
#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */
#define STM32_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */
/* Register Addresses *******************************************************/
#if STM32_NPORTS > 0
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32_NPORTS > 1
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32_NPORTS > 2
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32_NPORTS > 3
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32_NPORTS > 4
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32_NPORTS > 5
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32_NPORTS > 6
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32_NPORTS > 7
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32_NPORTS > 8
# define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET)
# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE + STM32_GPIO_PUPDR_OFFSET)
# define STM32_GPIOI_IDR (STM32_GPIOI_BASE + STM32_GPIO_IDR_OFFSET)
# define STM32_GPIOI_ODR (STM32_GPIOI_BASE + STM32_GPIO_ODR_OFFSET)
# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE + STM32_GPIO_BSRR_OFFSET)
# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE + STM32_GPIO_LCKR_OFFSET)
# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE + STM32_GPIO_AFRL_OFFSET)
# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE + STM32_GPIO_AFRH_OFFSET)
# define STM32_GPIOI_BRR (STM32_GPIOI_BASE + STM32_GPIO_BRR_OFFSET)
# define STM32_GPIOI_SECCFGR (STM32_GPIOI_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* GPIO port mode register */
#define GPIO_MODER_INPUT (0) /* Input */
#define GPIO_MODER_OUTPUT (1) /* General purpose output mode */
#define GPIO_MODER_ALT (2) /* Alternate mode */
#define GPIO_MODER_ANALOG (3) /* Analog mode */
#define GPIO_MODER_SHIFT(n) ((n) << 1)
#define GPIO_MODER_MASK(n) (3 << GPIO_MODER_SHIFT(n))
#define GPIO_MODER0_SHIFT (0)
#define GPIO_MODER0_MASK (3 << GPIO_MODER0_SHIFT)
#define GPIO_MODER1_SHIFT (2)
#define GPIO_MODER1_MASK (3 << GPIO_MODER1_SHIFT)
#define GPIO_MODER2_SHIFT (4)
#define GPIO_MODER2_MASK (3 << GPIO_MODER2_SHIFT)
#define GPIO_MODER3_SHIFT (6)
#define GPIO_MODER3_MASK (3 << GPIO_MODER3_SHIFT)
#define GPIO_MODER4_SHIFT (8)
#define GPIO_MODER4_MASK (3 << GPIO_MODER4_SHIFT)
#define GPIO_MODER5_SHIFT (10)
#define GPIO_MODER5_MASK (3 << GPIO_MODER5_SHIFT)
#define GPIO_MODER6_SHIFT (12)
#define GPIO_MODER6_MASK (3 << GPIO_MODER6_SHIFT)
#define GPIO_MODER7_SHIFT (14)
#define GPIO_MODER7_MASK (3 << GPIO_MODER7_SHIFT)
#define GPIO_MODER8_SHIFT (16)
#define GPIO_MODER8_MASK (3 << GPIO_MODER8_SHIFT)
#define GPIO_MODER9_SHIFT (18)
#define GPIO_MODER9_MASK (3 << GPIO_MODER9_SHIFT)
#define GPIO_MODER10_SHIFT (20)
#define GPIO_MODER10_MASK (3 << GPIO_MODER10_SHIFT)
#define GPIO_MODER11_SHIFT (22)
#define GPIO_MODER11_MASK (3 << GPIO_MODER11_SHIFT)
#define GPIO_MODER12_SHIFT (24)
#define GPIO_MODER12_MASK (3 << GPIO_MODER12_SHIFT)
#define GPIO_MODER13_SHIFT (26)
#define GPIO_MODER13_MASK (3 << GPIO_MODER13_SHIFT)
#define GPIO_MODER14_SHIFT (28)
#define GPIO_MODER14_MASK (3 << GPIO_MODER14_SHIFT)
#define GPIO_MODER15_SHIFT (30)
#define GPIO_MODER15_MASK (3 << GPIO_MODER15_SHIFT)
/* GPIO port output type register */
#define GPIO_OTYPER_OD(n) (1 << (n)) /* 1=Output open-drain */
#define GPIO_OTYPER_PP(n) (0) /* 0=Output push-pull */
/* GPIO port output speed register */
#define GPIO_OSPEED_2MHZ (0) /* 2 MHz Low speed */
#define GPIO_OSPEED_25MHZ (1) /* 25 MHz Medium speed */
#define GPIO_OSPEED_50MHZ (2) /* 50 MHz High speed */
#define GPIO_OSPEED_100MHZ (3) /* 100 MHz Very High speed on 30 pF (80 MHz Output max speed on 15 pF) */
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
#define GPIO_OSPEED0_SHIFT (0)
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED0_SHIFT)
#define GPIO_OSPEED1_SHIFT (2)
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED1_SHIFT)
#define GPIO_OSPEED2_SHIFT (4)
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED2_SHIFT)
#define GPIO_OSPEED3_SHIFT (6)
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED3_SHIFT)
#define GPIO_OSPEED4_SHIFT (8)
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED4_SHIFT)
#define GPIO_OSPEED5_SHIFT (10)
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED5_SHIFT)
#define GPIO_OSPEED6_SHIFT (12)
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED6_SHIFT)
#define GPIO_OSPEED7_SHIFT (14)
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED7_SHIFT)
#define GPIO_OSPEED8_SHIFT (16)
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED8_SHIFT)
#define GPIO_OSPEED9_SHIFT (18)
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED9_SHIFT)
#define GPIO_OSPEED10_SHIFT (20)
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED10_SHIFT)
#define GPIO_OSPEED11_SHIFT (22)
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED11_SHIFT)
#define GPIO_OSPEED12_SHIFT (24)
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED12_SHIFT)
#define GPIO_OSPEED13_SHIFT (26)
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED13_SHIFT)
#define GPIO_OSPEED14_SHIFT (28)
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED14_SHIFT)
#define GPIO_OSPEED15_SHIFT (30)
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED15_SHIFT)
/* GPIO port pull-up/pull-down register */
#define GPIO_PUPDR_NONE (0) /* No pull-up, pull-down */
#define GPIO_PUPDR_PULLUP (1) /* Pull-up */
#define GPIO_PUPDR_PULLDOWN (2) /* Pull-down */
#define GPIO_PUPDR_SHIFT(n) ((n) << 1)
#define GPIO_PUPDR_MASK(n) (3 << GPIO_PUPDR_SHIFT(n))
#define GPIO_PUPDR0_SHIFT (0)
#define GPIO_PUPDR0_MASK (3 << GPIO_PUPDR0_SHIFT)
#define GPIO_PUPDR1_SHIFT (2)
#define GPIO_PUPDR1_MASK (3 << GPIO_PUPDR1_SHIFT)
#define GPIO_PUPDR2_SHIFT (4)
#define GPIO_PUPDR2_MASK (3 << GPIO_PUPDR2_SHIFT)
#define GPIO_PUPDR3_SHIFT (6)
#define GPIO_PUPDR3_MASK (3 << GPIO_PUPDR3_SHIFT)
#define GPIO_PUPDR4_SHIFT (8)
#define GPIO_PUPDR4_MASK (3 << GPIO_PUPDR4_SHIFT)
#define GPIO_PUPDR5_SHIFT (10)
#define GPIO_PUPDR5_MASK (3 << GPIO_PUPDR5_SHIFT)
#define GPIO_PUPDR6_SHIFT (12)
#define GPIO_PUPDR6_MASK (3 << GPIO_PUPDR6_SHIFT)
#define GPIO_PUPDR7_SHIFT (14)
#define GPIO_PUPDR7_MASK (3 << GPIO_PUPDR7_SHIFT)
#define GPIO_PUPDR8_SHIFT (16)
#define GPIO_PUPDR8_MASK (3 << GPIO_PUPDR8_SHIFT)
#define GPIO_PUPDR9_SHIFT (18)
#define GPIO_PUPDR9_MASK (3 << GPIO_PUPDR9_SHIFT)
#define GPIO_PUPDR10_SHIFT (20)
#define GPIO_PUPDR10_MASK (3 << GPIO_PUPDR10_SHIFT)
#define GPIO_PUPDR11_SHIFT (22)
#define GPIO_PUPDR11_MASK (3 << GPIO_PUPDR11_SHIFT)
#define GPIO_PUPDR12_SHIFT (24)
#define GPIO_PUPDR12_MASK (3 << GPIO_PUPDR12_SHIFT)
#define GPIO_PUPDR13_SHIFT (26)
#define GPIO_PUPDR13_MASK (3 << GPIO_PUPDR13_SHIFT)
#define GPIO_PUPDR14_SHIFT (28)
#define GPIO_PUPDR14_MASK (3 << GPIO_PUPDR14_SHIFT)
#define GPIO_PUPDR15_SHIFT (30)
#define GPIO_PUPDR15_MASK (3 << GPIO_PUPDR15_SHIFT)
/* GPIO port input data register */
#define GPIO_IDR(n) (1 << (n))
/* GPIO port output data register */
#define GPIO_ODR(n) (1 << (n))
/* GPIO port bit set/reset register */
#define GPIO_BSRR_SET(n) (1 << (n))
#define GPIO_BSRR_RESET(n) (1 << ((n)+16))
/* GPIO port configuration lock register */
#define GPIO_LCKR(n) (1 << (n))
#define GPIO_LCKK (1 << 16) /* Lock key */
/* GPIO alternate function low/high register */
#define GPIO_AFR_SHIFT(n) ((n) << 2)
#define GPIO_AFR_MASK(n) (15 << GPIO_AFR_SHIFT(n))
#define GPIO_AFRL0_SHIFT (0)
#define GPIO_AFRL0_MASK (15 << GPIO_AFRL0_SHIFT)
#define GPIO_AFRL1_SHIFT (4)
#define GPIO_AFRL1_MASK (15 << GPIO_AFRL1_SHIFT)
#define GPIO_AFRL2_SHIFT (8)
#define GPIO_AFRL2_MASK (15 << GPIO_AFRL2_SHIFT)
#define GPIO_AFRL3_SHIFT (12)
#define GPIO_AFRL3_MASK (15 << GPIO_AFRL3_SHIFT)
#define GPIO_AFRL4_SHIFT (16)
#define GPIO_AFRL4_MASK (15 << GPIO_AFRL4_SHIFT)
#define GPIO_AFRL5_SHIFT (20)
#define GPIO_AFRL5_MASK (15 << GPIO_AFRL5_SHIFT)
#define GPIO_AFRL6_SHIFT (24)
#define GPIO_AFRL6_MASK (15 << GPIO_AFRL6_SHIFT)
#define GPIO_AFRL7_SHIFT (28)
#define GPIO_AFRL7_MASK (15 << GPIO_AFRL7_SHIFT)
#define GPIO_AFRH8_SHIFT (0)
#define GPIO_AFRH8_MASK (15 << GPIO_AFRH8_SHIFT)
#define GPIO_AFRH9_SHIFT (4)
#define GPIO_AFRH9_MASK (15 << GPIO_AFRH9_SHIFT)
#define GPIO_AFRH10_SHIFT (8)
#define GPIO_AFRH10_MASK (15 << GPIO_AFRH10_SHIFT)
#define GPIO_AFRH11_SHIFT (12)
#define GPIO_AFRH11_MASK (15 << GPIO_AFRH11_SHIFT)
#define GPIO_AFRH12_SHIFT (16)
#define GPIO_AFRH12_MASK (15 << GPIO_AFRH12_SHIFT)
#define GPIO_AFRH13_SHIFT (20)
#define GPIO_AFRH13_MASK (15 << GPIO_AFRH13_SHIFT)
#define GPIO_AFRH14_SHIFT (24)
#define GPIO_AFRH14_MASK (15 << GPIO_AFRH14_SHIFT)
#define GPIO_AFRH15_SHIFT (28)
#define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT)
/* GPIO port bit reset register */
#define GPIO_BRR_SET(n) (1 << (n))
/* GPIO port secure configuration register */
#define GPIO_SECCFGR_SET(n) (1 << (n))
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_GPIO_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32U5_STM32_MEMORYMAP_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* STM32U5XXX Address Blocks ************************************************/
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */
# define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */
# define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
# define STM32_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */
#define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define STM32_REGION_MASK 0xF0000000
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_SRAM_BASE)
#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_FMC_BANK1)
/* Code Base Addresses ******************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */
#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */
#define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */
#define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k SRAM3 */
/* System Memory Addresses **************************************************/
#define STM32_SYSMEM_UID 0x0BFA0700 /* The 96-bit unique device identifier */
#define STM32_SYSMEM_FSIZE 0x0BFA07A0 /* Size of Flash memory in Kbytes. */
#define STM32_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */
/* Peripheral Base Addresses ************************************************/
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40012bff: APB1 */
#define STM32_APB2_BASE 0x40012c00 /* 0x40012c00-0x4001ffff: APB2 */
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x4201ffff: AHB1 */
#define STM32_AHB2_BASE 0x42020000 /* 0x42020000-0x460003ff: AHB2 */
#define STM32_APB3_BASE 0x46000400 /* 0x46000400-0x4601ffff: APB2 */
#define STM32_AHB3_BASE 0x46020000 /* 0x46020000-0x4fffffff: AHB3 */
/* APB1 Base Addresses ******************************************************/
#define STM32_TIM2_BASE 0x40000000
#define STM32_TIM3_BASE 0x40000400
#define STM32_TIM4_BASE 0x40000800
#define STM32_TIM5_BASE 0x40000c00
#define STM32_TIM6_BASE 0x40001000
#define STM32_TIM7_BASE 0x40001400
#define STM32_WWDG_BASE 0x40002c00
#define STM32_IWDG_BASE 0x40003000
#define STM32_SPI2_BASE 0x40003800
#define STM32_USART2_BASE 0x40004400
#define STM32_USART3_BASE 0x40004800
#define STM32_UART4_BASE 0x40004c00
#define STM32_UART5_BASE 0x40005000
#define STM32_I2C1_BASE 0x40005400
#define STM32_I2C2_BASE 0x40005800
#define STM32_CRS_BASE 0x40006000
#define STM32_I2C4_BASE 0x40008400
#define STM32_LPTIM2_BASE 0x40009400
#define STM32_FDCAN1_BASE 0x4000a400
#define STM32_FDCAN_RAM_BASE 0x4000ac00
#define STM32_UCPD1_BASE 0x4000dc00
/* APB2 Base Addresses ******************************************************/
#define STM32_TIM1_BASE 0x40012c00
#define STM32_SPI1_BASE 0x40013000
#define STM32_TIM8_BASE 0x40013400
#define STM32_USART1_BASE 0x40013800
#define STM32_TIM15_BASE 0x40014000
#define STM32_TIM16_BASE 0x40014400
#define STM32_TIM17_BASE 0x40014800
#define STM32_SAI1_BASE 0x40015400
#define STM32_SAI2_BASE 0x40015800
/* AHB1 Base Addresses ******************************************************/
#define STM32_GPDMA1_BASE 0x40020000
#define STM32_CORDIC_BASE 0x40021000
#define STM32_FMAC_BASE 0x40021400
#define STM32_FLASHIF_BASE 0x40022000
#define STM32_CRC_BASE 0x40023000
#define STM32_TSC_BASE 0x40024000
#define STM32_MDF1_BASE 0x40025000
#define STM32_RAMCFG_BASE 0x40026000
#define STM32_DMA2D_BASE 0x4002b000
#define STM32_ICACHE_BASE 0x40030400
#define STM32_DCACHE1_BASE 0x40031400
#define STM32_GTZC1_TZSC_BASE 0x40032400
#define STM32_GTZC1_TZIC_BASE 0x40032800
#define STM32_GTZC1_MPCBB1_BASE 0x40032c00
#define STM32_GTZC1_MPCBB2_BASE 0x40033000
#define STM32_GTZC1_MPCBB3_BASE 0x40033400
#define STM32_BKPSRAM_BASE 0x40036400
/* AHB2 Base Addresses ******************************************************/
#define STM32_GPIOA_BASE 0x42020000
#define STM32_GPIOB_BASE 0x42020400
#define STM32_GPIOC_BASE 0x42020800
#define STM32_GPIOD_BASE 0x42020c00
#define STM32_GPIOE_BASE 0x42021000
#define STM32_GPIOF_BASE 0x42021400
#define STM32_GPIOG_BASE 0x42021800
#define STM32_GPIOH_BASE 0x42021c00
#define STM32_GPIOI_BASE 0x42022000
#define STM32_ADC1_BASE 0x42028000
#define STM32_DCMI_BASE 0x4202c000
#define STM32_PSSI_BASE 0x4202c400
#define STM32_OTG_FS_BASE 0x42040000
#define STM32_AES_BASE 0x420c0000
#define STM32_HASH_BASE 0x420c0400
#define STM32_RNG_BASE 0x420c0800
#define STM32_SAES_BASE 0x420c0c00
#define STM32_PKA_BASE 0x420c2000
#define STM32_OCTOSPIM_BASE 0x420c4000
#define STM32_OTFDEC1_BASE 0x420c5000
#define STM32_OTFDEC2_BASE 0x420c5400
#define STM32_SDMMC1_BASE 0x420c8000
#define STM32_DLYBSD1_BASE 0x420c8400
#define STM32_DLYBSD2_BASE 0x420c8800
#define STM32_SDMMC2_BASE 0x420c8c00
#define STM32_DLYBOS1_BASE 0x420cf000
#define STM32_DLYBOS2_BASE 0x420cf400
#define STM32_FSMC_BASE 0x420d0400
#define STM32_OCTOSPI1_BASE 0x420d1400
#define STM32_OCTOSPI2_BASE 0x420d2400
/* APB3 Base Addresses ******************************************************/
#define STM32_SYSCFG_BASE 0x46000400
#define STM32_SPI3_BASE 0x46002000
#define STM32_LPUART1_BASE 0x46002400
#define STM32_I2C3_BASE 0x46002c00
#define STM32_LPTIM1_BASE 0x46004400
#define STM32_LPTIM3_BASE 0x46004800
#define STM32_LPTIM4_BASE 0x46004c00
#define STM32_OPAMP_BASE 0x46005000
#define STM32_COMP_BASE 0x46005400
#define STM32_VREFBUF_BASE 0x46007400
#define STM32_RTC_BASE 0x46007800
#define STM32_TAMP_BASE 0x46007c00
/* AHB3 Base Addresses ******************************************************/
#define STM32_LPGPIO1_BASE 0x46020000
#define STM32_PWR_BASE 0x46020800
#define STM32_RCC_BASE 0x46020c00
#define STM32_ADC4_BASE 0x46021000
#define STM32_DAC1_BASE 0x46021800
#define STM32_EXTI_BASE 0x46022000
#define STM32_GTZC2_TZSC_BASE 0x46023000
#define STM32_GTZC2_TZIC_BASE 0x46023400
#define STM32_GTZC2_MPCBB4_BASE 0x46023800
#define STM32_ADF1_BASE 0x46024000
#define STM32_LPDMA1_BASE 0x46025000
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_MEMORYMAP_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PINMAP_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_pinmap.h"
#else
# error "Unsupported STM32U5 pin map"
#endif
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PINMAP_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_PWR_CR1_OFFSET 0x0000 /* PWR control register 1 */
#define STM32_PWR_CR2_OFFSET 0x0004 /* PWR control register 2 */
#define STM32_PWR_CR3_OFFSET 0x0008 /* PWR control register 3 */
#define STM32_PWR_VOSR_OFFSET 0x000c /* PWR voltage scaling register */
#define STM32_PWR_SVMCR_OFFSET 0x0010 /* PWR supply voltage monitoring control register */
#define STM32_PWR_WUCR1_OFFSET 0x0014 /* PWR wakeup control register 1 */
#define STM32_PWR_WUCR2_OFFSET 0x0018 /* PWR wakeup control register 2 */
#define STM32_PWR_WUCR3_OFFSET 0x001c /* PWR wakeup control register 3 */
#define STM32_PWR_BDCR1_OFFSET 0x0020 /* PWR Backup domain control register 1 */
#define STM32_PWR_BDCR2_OFFSET 0x0024 /* PWR Backup domain control register 2 */
#define STM32_PWR_DBPR_OFFSET 0x0028 /* PWR disable Backup domain register */
#define STM32_PWR_UCPDR_OFFSET 0x002c /* PWR USB Type-C and Power Delivery register */
#define STM32_PWR_SECCFGR_OFFSET 0x0030 /* PWR security configuration register */
#define STM32_PWR_PRIVCFGR_OFFSET 0x0034 /* PWR privilege control register */
#define STM32_PWR_SR_OFFSET 0x0038 /* PWR status register */
#define STM32_PWR_SVMSR_OFFSET 0x003c /* PWR supply voltage monitoring register */
#define STM32_PWR_BDSR_OFFSET 0x0040 /* PWR Backup domain status register */
#define STM32_PWR_WUSR_OFFSET 0x0044 /* PWR wakeup status register */
#define STM32_PWR_WUSCR_OFFSET 0x0048 /* PWR wakeup status clear register */
#define STM32_PWR_APCR_OFFSET 0x004c /* PWR apply pull configuration register */
#define STM32_PWR_PUCRA_OFFSET 0x0050 /* PWR Port A pull-up control register */
#define STM32_PWR_PDCRA_OFFSET 0x0054 /* PWR Port A pull-down control register */
#define STM32_PWR_PUCRB_OFFSET 0x0058 /* PWR Port B pull-up control register */
#define STM32_PWR_PDCRB_OFFSET 0x005C /* PWR Port B pull-down control register */
#define STM32_PWR_PUCRC_OFFSET 0x0060 /* PWR Port C pull-up control register */
#define STM32_PWR_PDCRC_OFFSET 0x0064 /* PWR Port C pull-down control register */
#define STM32_PWR_PUCRD_OFFSET 0x0068 /* PWR Port D pull-up control register */
#define STM32_PWR_PDCRD_OFFSET 0x006C /* PWR Port D pull-down control register */
#define STM32_PWR_PUCRE_OFFSET 0x0070 /* PWR Port E pull-up control register */
#define STM32_PWR_PDCRE_OFFSET 0x0074 /* PWR Port E pull-down control register */
#define STM32_PWR_PUCRF_OFFSET 0x0078 /* PWR Port F pull-up control register */
#define STM32_PWR_PDCRF_OFFSET 0x007C /* PWR Port F pull-down control register */
#define STM32_PWR_PUCRG_OFFSET 0x0080 /* PWR Port G pull-up control register */
#define STM32_PWR_PDCRG_OFFSET 0x0084 /* PWR Port G pull-down control register */
#define STM32_PWR_PUCRH_OFFSET 0x0088 /* PWR Port H pull-up control register */
#define STM32_PWR_PDCRH_OFFSET 0x008C /* PWR Port H pull-down control register */
#define STM32_PWR_PUCRI_OFFSET 0x0090 /* PWR Port I pull-up control register */
#define STM32_PWR_PDCRI_OFFSET 0x0094 /* PWR Port I pull-down control register */
/* Register Addresses *******************************************************/
#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET)
#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET)
#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET)
#define STM32_PWR_VOSR (STM32_PWR_BASE + STM32_PWR_VOSR_OFFSET)
#define STM32_PWR_SVMCR (STM32_PWR_BASE + STM32_PWR_SVMCR_OFFSET)
#define STM32_PWR_WUCR1 (STM32_PWR_BASE + STM32_PWR_WUCR1_OFFSET)
#define STM32_PWR_WUCR2 (STM32_PWR_BASE + STM32_PWR_WUCR2_OFFSET)
#define STM32_PWR_WUCR3 (STM32_PWR_BASE + STM32_PWR_WUCR3_OFFSET)
#define STM32_PWR_BDCR1 (STM32_PWR_BASE + STM32_PWR_BDCR1_OFFSET)
#define STM32_PWR_BDCR2 (STM32_PWR_BASE + STM32_PWR_BDCR2_OFFSET)
#define STM32_PWR_DBPR (STM32_PWR_BASE + STM32_PWR_DBPR_OFFSET)
#define STM32_PWR_UCPDR (STM32_PWR_BASE + STM32_PWR_UCPDR_OFFSET)
#define STM32_PWR_SECCFGR (STM32_PWR_BASE + STM32_PWR_SECCFGR_OFFSET)
#define STM32_PWR_PRIVCFGR (STM32_PWR_BASE + STM32_PWR_PRIVCFGR_OFFSET)
#define STM32_PWR_SR (STM32_PWR_BASE + STM32_PWR_SR_OFFSET)
#define STM32_PWR_SVMSR (STM32_PWR_BASE + STM32_PWR_SVMSR_OFFSET)
#define STM32_PWR_BDSR (STM32_PWR_BASE + STM32_PWR_BDSR_OFFSET)
#define STM32_PWR_WUSR (STM32_PWR_BASE + STM32_PWR_WUSR_OFFSET)
#define STM32_PWR_WUSCR (STM32_PWR_BASE + STM32_PWR_WUSCR_OFFSET)
#define STM32_PWR_APCR (STM32_PWR_BASE + STM32_PWR_APCR_OFFSET)
#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET)
#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET)
#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET)
#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET)
#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET)
#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET)
#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET)
#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET)
#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET)
#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET)
#define STM32_PWR_PUCRF (STM32_PWR_BASE + STM32_PWR_PUCRF_OFFSET)
#define STM32_PWR_PDCRF (STM32_PWR_BASE + STM32_PWR_PDCRF_OFFSET)
#define STM32_PWR_PUCRG (STM32_PWR_BASE + STM32_PWR_PUCRG_OFFSET)
#define STM32_PWR_PDCRG (STM32_PWR_BASE + STM32_PWR_PDCRG_OFFSET)
#define STM32_PWR_PUCRH (STM32_PWR_BASE + STM32_PWR_PUCRH_OFFSET)
#define STM32_PWR_PDCRH (STM32_PWR_BASE + STM32_PWR_PDCRH_OFFSET)
#define STM32_PWR_PUCRI (STM32_PWR_BASE + STM32_PWR_PUCRI_OFFSET)
#define STM32_PWR_PDCRI (STM32_PWR_BASE + STM32_PWR_PDCRI_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* PWR control register 1 */
#define PWR_CR1_LPMS_SHIFT 0
#define PWR_CR1_LPMS_MASK (7 << PWR_CR1_LPMS_SHIFT) /* Bits 0-2: Low-power mode selection */
# define PWR_CR1_LPMS_STOP0 (0 << PWR_CR1_LPMS_SHIFT) /* 000: Stop 0 mode */
# define PWR_CR1_LPMS_STOP1 (1 << PWR_CR1_LPMS_SHIFT) /* 001: Stop 1 mode */
# define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */
# define PWR_CR1_LPMS_STOP3 (3 << PWR_CR1_LPMS_SHIFT) /* 011: Stop 3 mode */
# define PWR_CR1_LPMS_STANDBY (4 << PWR_CR1_LPMS_SHIFT) /* 10x: Standby mode */
# define PWR_CR1_LPMS_SHUTDOWN (6 << PWR_CR1_LPMS_SHIFT) /* 11x: Shutdown mode */
#define PWR_CR1_RRSB1 (1 << 5) /* Bit 5: SRAM2 page 1 retention in Stop 3 and Standby mode */
#define PWR_CR1_RRSB2 (1 << 6) /* Bit 6: SRAM2 page 2 retention in Stop 3 and Standby mode */
#define PWR_CR1_ULPMEN (1 << 7) /* Bit 7: BOR ultra-low power mode */
#define PWR_CR1_SRAM1PD (1 << 8) /* Bit 8: SRAM1 power down */
#define PWR_CR1_SRAM2PD (1 << 9) /* Bit 9: SRAM2 power down */
#define PWR_CR1_SRAM3PD (1 << 10) /* Bit 10: SRAM3 power down */
#define PWR_CR1_SRAM4PD (1 << 11) /* Bit 11: SRAM4 power down */
/* PWR control register 2 */
#define PWR_CR2_SRAM1PDS1 (1 << 0) /* Bit 0: SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM1PDS2 (1 << 1) /* Bit 1: SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM1PDS3 (1 << 2) /* Bit 2: SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM2PDS1 (1 << 4) /* Bit 4: SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM2PDS2 (1 << 5) /* Bit 5: SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM4PDS (1 << 6) /* Bit 6: SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_ICRAMPDS (1 << 8) /* Bit 8: ICACHE SRAM power-down Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_DC1RAMPDS (1 << 9) /* Bit 9: DCACHE1 SRAM power-down Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_DMA2DRAMPDS (1 << 10) /* Bit 10: DMA2D SRAM power-down Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_PRAMPDS (1 << 11) /* Bit 11: FMAC, FDCAN and USB peripherals SRAM power-down Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_PKARAMPDS (1 << 12) /* Bit 12: PKA SRAM power-down Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM4FWU (1 << 13) /* Bit 13: SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes */
#define PWR_CR2_FLASHFWU (1 << 14) /* Bit 14: Flash memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes */
#define PWR_CR2_SRAM3PDS1 (1 << 16) /* Bit 16: SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM3PDS2 (1 << 17) /* Bit 17: SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM3PDS3 (1 << 18) /* Bit 18: SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM3PDS4 (1 << 19) /* Bit 19: SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM3PDS5 (1 << 20) /* Bit 20: SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM3PDS6 (1 << 21) /* Bit 21: SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM3PDS7 (1 << 22) /* Bit 22: SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRAM3PDS8 (1 << 23) /* Bit 23: SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3) */
#define PWR_CR2_SRDRUN (1 << 31) /* Bit 31: SmartRun domain in Run mode */
/* PWR control register 3 */
#define PWR_CR3_REGSEL (1 << 1) /* Bit 1: Regulator selection */
#define PWR_CR3_REGSEL_LDO 0
#define PWR_CR3_REGSEL_SMPS PWR_CR3_REGSEL
#define PWR_CR3_FSTEN (1 << 2) /* Bit 2: Fast soft start */
/* PWR voltage scaling register */
#define PWR_VOSR_BOOSTRDY (1 << 14) /* Bit 14: EPOD booster ready */
#define PWR_VOSR_VOSRDY (1 << 15) /* Bit 15: Ready bit for V_CORE voltage scaling output selection */
#define PWR_VOSR_VOS_SHIFT 16
#define PWR_VOSR_VOS_MASK (3 << PWR_VOSR_VOS_SHIFT) /* Bits 16-17: Voltage scaling range selection */
#define PWR_VOSR_VOS_RANGE4 (0 << PWR_VOSR_VOS_SHIFT) /* 00: Range 4 (lowest power) */
#define PWR_VOSR_VOS_RANGE3 (1 << PWR_VOSR_VOS_SHIFT) /* 01: Range 3 */
#define PWR_VOSR_VOS_RANGE2 (2 << PWR_VOSR_VOS_SHIFT) /* 10: Range 2 */
#define PWR_VOSR_VOS_RANGE1 (3 << PWR_VOSR_VOS_SHIFT) /* 11: Range 1 (highest frequency) */
#define PWR_VOSR_BOOSTEN (1 << 18) /* Bit 18: EPOD booster enable */
/* PWR Disable backup domain register */
#define PWR_DBPR_DBP (1 << 0) /* Bit 0: Disable Backup domain write protection. */
/* PWR Supply voltage monitoring status register */
#define PWR_SVMSR_REGS (1 << 1) /* Bit 1: Regulator selection */
#define PWR_SVMSR_REGS_LDO 0 /* 0: LDO selected */
#define PWR_SVMSR_REGS_SMPS PWR_SVMSR_REGS /* 1: SMPS selected */
#define PWR_SVMSR_PVDO (1 << 4) /* Bit 4: Programmable voltage detector output */
#define PWR_SVMSR_ACTVOSRDY (1 << 15) /* Bit 15: Voltage level ready for currenty used VOS */
#define PWR_SVMSR_ACTVOS_SHIFT 16
#define PWR_SVMSR_ACTVOS_MASK (3 << PWR_SVMSR_ACTVOS_SHIFT) /* Bits 16-17: VOS currently applied to V_CORE */
#define PWR_SVMSR_ACTVOS_RANGE4 (0 << PWR_SVMSR_ACTVOS_SHIFT) /* 00: Range 4 (lowest power) */
#define PWR_SVMSR_ACTVOS_RANGE3 (1 << PWR_SVMSR_ACTVOS_SHIFT) /* 01: Range 3 */
#define PWR_SVMSR_ACTVOS_RANGE2 (2 << PWR_SVMSR_ACTVOS_SHIFT) /* 10: Range 2 */
#define PWR_SVMSR_ACTVOS_RANGE1 (3 << PWR_SVMSR_ACTVOS_SHIFT) /* 11: Range 1 (highest frequency) */
#define PWR_SVMSR_VDDUSBRDY (1 << 24) /* Bit 24: V_DDUSB ready */
#define PWR_SVMSR_VDDIO2RDY (1 << 25) /* Bit 25: V_DDIO2 ready */
#define PWR_SVMSR_VDDA1RDY (1 << 26) /* Bit 26: V_DDA is equal or above ~1.6V */
#define PWR_SVMSR_VDDA2RDY (1 << 27) /* Bit 27: V_DDA is equal or above ~1.8V */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_PWR_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_spi.h"
#else
# error "Unsupported STM32 U5 sub family"
#endif
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_SPI_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_syscfg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_SYSCFG_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_SYSCFG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_syscfg.h"
#else
# error "Unsupported STM32U5 chip"
#endif
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_SYSCFG_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_UART_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */
#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */
#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */
#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */
#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */
#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */
#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */
#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */
#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */
#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */
#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */
#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */
#define STM32_USART_AUTOCR_OFFSET 0x0030 /* Autonomous mode control register */
/* Register Addresses *******************************************************/
#if STM32_NUSART > 0
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 1
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 2
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET)
# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET)
# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET)
# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET)
# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET)
# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET)
# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 3
# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32_NUSART > 4
# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET)
# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET)
# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET)
# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET)
# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET)
# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET)
# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET)
# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET)
# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET)
# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* Control register 1 */
#define USART_CR1_UE (1 << 0) /* Bit 0: USART Enable */
#define USART_CR1_UESM (1 << 1) /* Bit 1: USART Enable in Stop mode */
#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */
#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */
#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */
#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */
#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */
#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */
#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */
#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */
#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */
#define USART_CR1_M0 (1 << 12) /* Bit 12: Word length */
#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */
#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */
#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */
#define USART_CR1_DEDT_SHIFT (16) /* Bits 16..20 DE deactivation delay */
#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT)
#define USART_CR1_DEAT_SHIFT (21) /* Bits 21..25 DE activation delay */
#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT)
#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */
#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of block interrupt enable */
#define USART_CR1_M1 (1 << 28) /* Bit 28: Word length */
#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE| \
USART_CR1_TCIE|USART_CR1_TXEIE| \
USART_CR1_PEIE|USART_CR1_CMIE| \
USART_CR1_RTOIE|USART_CR1_EOBIE)
/* Control register 2 */
#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: 7-bit/4-bit Address Detection */
#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */
#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */
#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */
#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */
#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */
#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */
#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT)
# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */
#define USART_CR2_SWAP (1 << 15) /* Bit 15: Swap TX/RX pins */
#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */
#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */
#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */
#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */
#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto Baud rate enable */
#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Autobaud rate mode*/
#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT)
#define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* 00: Start bit */
#define USART_CR2_ABRMOD_EDGES (1 << USART_CR2_ABRMOD_SHIFT) /* 01: Falling-to-falling edge -> frame must start with 10xxxxxx */
#define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 10: 0x7F */
#define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 11: 0x55 */
#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */
#define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */
#define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT)
/* Control register 3 */
#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */
#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */
#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */
#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */
#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */
#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */
#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */
#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */
#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */
#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */
#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */
#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method Enable */
#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */
#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA disable on Reception error */
#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver Enable mode */
#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver Enable polarity selection */
#define USART_CR3_SCARCNT2_SHIFT (17) /* Bits 17-19: Smart card auto retry count */
#define USART_CR3_SCARCNT2_MASK (7 << USART_CR3_SCARCNT2_SHIFT)
#define USART_CR3_WUS_SHIFT (20) /* Bits 20-21: Wakeup from Stop mode interrupt flag selection */
#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT)
#define USART_CR3_WUS_ADDRESS (0 << USART_CR3_WUS_SHIFT) /* 00: WUF active on address match */
#define USART_CR3_WUS_START (2 << USART_CR3_WUS_SHIFT) /* 10: WUF active on Start bit detection */
#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* 11: WUF active on RXNE */
#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */
/* Baud Rate Register */
#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */
#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT)
#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */
#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT)
/* Guard time and prescaler register */
#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */
#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT)
#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */
#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT)
/* Receiver timeout register */
/* Request Register */
#define USART_CR1_SBRKQ (1 << 1) /* Bit 1: Send Break */
/* Interrupt and Status register */
#define USART_ISR_PE (1 << 0) /* Bit 0: Parity Error */
#define USART_ISR_FE (1 << 1) /* Bit 1: Framing Error */
#define USART_ISR_NF (1 << 2) /* Bit 2: Noise Error Flag */
#define USART_ISR_ORE (1 << 3) /* Bit 3: OverRun Error */
#define USART_ISR_IDLE (1 << 4) /* Bit 4: IDLE line detected */
#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */
#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission Complete */
#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */
#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN Break Detection Flag */
#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS Interrupt Flag */
#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS Flag */
#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout Flag */
#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block Flag */
#define USART_ISR_UDR (1 << 13) /* Bit 13: SPI slave underrun error flag */
#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate Error */
#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate Flag */
#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy Flag */
#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match Flag */
#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break Flag */
#define USART_ISR_RWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */
#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode Flag */
#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge Flag */
#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge Flag */
/* ICR */
#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */
#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */
#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected clear flag */
#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */
#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */
#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete clear flag */
#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */
#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS clear flag */
#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */
#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */
#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */
#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */
/* Receive Data register */
#define USART_RDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_RDR_MASK (0xff << USART_RDR_SHIFT)
/* Transmit Data register */
#define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */
#define USART_TDR_MASK (0xff << USART_TDR_SHIFT)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32_UART_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32u585xx_dbgmcu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_DBGMCU_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_DBGMCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Addresses *******************************************************/
#define STM32_DBGMCU_IDCODE 0xe0044000 /* MCU identifier */
#define STM32_DBGMCU_CR 0xe0044004 /* MCU debug */
#define STM32_DBGMCU_APB1_FZ 0xe0044008 /* Debug MCU APB1 freeze register */
#define STM32_DBGMCU_APB1_FZ2 0xe004400c /* Debug MCU APB1 freeze register 2 */
#define STM32_DBGMCU_APB2_FZ 0xe0044010 /* Debug MCU APB2 freeze register */
/* Register Bitfield Definitions ********************************************/
/* MCU identifier */
#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
/* MCU debug */
#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Allows debug in Stop mode */
#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Allows debug in Standby mode */
#define DBGMCU_CR_TRACEIOEN (1 << 4) /* Bit 4: Trace pin enable */
#define DBGMCU_CR_TRACEEN (1 << 5) /* Bit 5: Trace port and clock enable */
#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignment */
#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT)
#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
#define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
#define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
#define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
/* Debug MCU APB1 freeze register */
#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */
#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */
#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */
#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */
#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */
#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */
#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */
#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
#define DBGMCU_APB1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 stopper when core is halted */
/* Debug MCU APB1 freeze register 2 */
#define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopped when core is halted */
#define DBGMCU_APB1_FZ2_LPTIM3STOP (1 << 6) /* Bit 6: LPTIM3 stopped when core is halted */
#define DBGMCU_APB1_FZ2_I2C4STOP (1 << 1) /* Bit 1: I2C4 stopped when core is halted */
/* Debug MCU APB2 freeze register */
#define DBGMCU_APB2_TIM1STOP (1 << 11) /* Bit 11: TIM1 stopped when core is halted */
#define DBGMCU_APB2_TIM8STOP (1 << 13) /* Bit 13: TIM8 stopped when core is halted */
#define DBGMCU_APB2_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */
#define DBGMCU_APB2_TIM16STOP (1 << 17) /* Bit 17: TIM16 stopped when core is halted */
#define DBGMCU_APB2_TIM17STOP (1 << 18) /* Bit 18: TIM17 stopped when core is halted */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XXDBGMCU_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32u585xx_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SPI_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_STM32U5_STM32U585XX)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Maximum allowed speed as per data sheet for all SPIs */
# define STM32_SPI_CLK_MAX 160000000UL
/* Register Offsets *********************************************************/
#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI/I2S Control Register 1 */
#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 */
#define STM32_SPI_CFG1_OFFSET 0x0008 /* SPI configuration register 1 */
#define STM32_SPI_CFG2_OFFSET 0x000C /* SPI configuration register 2 */
#define STM32_SPI_IER_OFFSET 0x0010 /* SPI/I2S interrupt enable register */
#define STM32_SPI_SR_OFFSET 0x0014 /* SPI/I2S status register */
#define STM32_SPI_IFCR_OFFSET 0x0018 /* SPI/I2S interrupt/status flags clear register */
#define STM32_SPI_TXDR_OFFSET 0x0020 /* SPI/I2S transmit data register */
#define STM32_SPI_RXDR_OFFSET 0x0030 /* SPI/I2S receive data register */
#define STM32_SPI_CRCPOLY_OFFSET 0x0040 /* SPI/I2S SPI polynominal register */
#define STM32_SPI_TXCRC_OFFSET 0x0044 /* SPI/I2S SPI transmitter CRC register */
#define STM32_SPI_RXCRC_OFFSET 0x0048 /* SPI/I2S SPI receiver CRC register */
#define STM32_SPI_UDRDR_OFFSET 0x004C /* SPI/I2S SPI underrun data register */
/* Register Addresses *******************************************************/
#if STM32_NSPI > 0
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET)
# define STM32_SPI1_CFG2 (STM32_SPI1_BASE+STM32_SPI_CFG2_OFFSET)
# define STM32_SPI1_IER (STM32_SPI1_BASE+STM32_SPI_IER_OFFSET)
# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
# define STM32_SPI1_IFCR (STM32_SPI1_BASE+STM32_SPI_IFCR_OFFSET)
# define STM32_SPI1_TXDR (STM32_SPI1_BASE+STM32_SPI_TXDR_OFFSET)
# define STM32_SPI1_RXDR (STM32_SPI1_BASE+STM32_SPI_RXDR_OFFSET)
# define STM32_SPI1_CRCPOLY (STM32_SPI1_BASE+STM32_SPI_CRCPOLY_OFFSET)
# define STM32_SPI1_TXCRC (STM32_SPI1_BASE+STM32_SPI_TXCRC_OFFSET)
# define STM32_SPI1_RXCRC (STM32_SPI1_BASE+STM32_SPI_RXCRC_OFFSET)
# define STM32_SPI1_UDRDR (STM32_SPI1_BASE+STM32_SPI_UDRDR_OFFSET)
#endif
#if STM32_NSPI > 1
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET)
# define STM32_SPI2_CFG2 (STM32_SPI2_BASE+STM32_SPI_CFG2_OFFSET)
# define STM32_SPI2_IER (STM32_SPI2_BASE+STM32_SPI_IER_OFFSET)
# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
# define STM32_SPI2_IFCR (STM32_SPI2_BASE+STM32_SPI_IFCR_OFFSET)
# define STM32_SPI2_TXDR (STM32_SPI2_BASE+STM32_SPI_TXDR_OFFSET)
# define STM32_SPI2_RXDR (STM32_SPI2_BASE+STM32_SPI_RXDR_OFFSET)
# define STM32_SPI2_CRCPOLY (STM32_SPI2_BASE+STM32_SPI_CRCPOLY_OFFSET)
# define STM32_SPI2_TXCRC (STM32_SPI2_BASE+STM32_SPI_TXCRC_OFFSET)
# define STM32_SPI2_RXCRC (STM32_SPI2_BASE+STM32_SPI_RXCRC_OFFSET)
# define STM32_SPI2_UDRDR (STM32_SPI2_BASE+STM32_SPI_UDRDR_OFFSET)
#endif
#if STM32_NSPI > 2
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET)
# define STM32_SPI3_CFG2 (STM32_SPI3_BASE+STM32_SPI_CFG2_OFFSET)
# define STM32_SPI3_IER (STM32_SPI3_BASE+STM32_SPI_IER_OFFSET)
# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
# define STM32_SPI3_IFCR (STM32_SPI3_BASE+STM32_SPI_IFCR_OFFSET)
# define STM32_SPI3_TXDR (STM32_SPI3_BASE+STM32_SPI_TXDR_OFFSET)
# define STM32_SPI3_RXDR (STM32_SPI3_BASE+STM32_SPI_RXDR_OFFSET)
# define STM32_SPI3_CRCPOLY (STM32_SPI3_BASE+STM32_SPI_CRCPOLY_OFFSET)
# define STM32_SPI3_TXCRC (STM32_SPI3_BASE+STM32_SPI_TXCRC_OFFSET)
# define STM32_SPI3_RXCRC (STM32_SPI3_BASE+STM32_SPI_RXCRC_OFFSET)
# define STM32_SPI3_UDRDR (STM32_SPI3_BASE+STM32_SPI_UDRDR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* SPI Control Register 1 */
#define SPI_CR1_SPE (1 << 0) /* Bit 0: SPI Enable */
/* Bits 1-7: Reserved */
#define SPI_CR1_MASRX (1 << 8) /* Bit 8: */
#define SPI_CR1_CSTART (1 << 9) /* Bit 9: master transfer start */
#define SPI_CR1_CSUSP (1 << 10) /* Bit 10: master suspend request */
#define SPI_CR1_HDDIR (1 << 11) /* Bit 11: RX/TX direction at Half-duplex mode */
#define SPI_CR1_SSI (1 << 12) /* Bit 12: Internal slave select */
#define SPI_CR1_CRC33_17 (1 << 13) /* Bit 13: 32-bit CRC polynominal configuration */
#define SPI_CR1_RCRCINI (1 << 14) /* Bit 14: CRC calculation initialization pattern control for receiver */
#define SPI_CR1_TCRCINI (1 << 15) /* Bit 15: CRC calculation initialization pattern control for transmitter */
#define SPI_CR1_IOLOCK (1 << 16) /* Bit 16: locking the AF configuration of associated IOs */
/* Bits 17-31: Reserved */
/* SPI Control Register 2 */
#define SPI_CR2_TSIZE_SHIFT (0) /* Bits 0-15 */
#define SPI_CR2_TSIZE_MASK (0xff << SPI_CR2_TSIZE_SHIFT)
#define SPI_CR2_TSER_SHIFT (16) /* Bits 16-31 */
#define SPI_CR2_TSER_MASK (0xff << SPI_CR2_TSER_SHIFT)
/* SPI configuration register 1 */
#define SPI_CFG1_DSIZE_SHIFT (0) /* Bits 0-4: number of bits in at single SPI data frame */
#define SPI_CFG1_DSIZE_VAL(n) ((n-1) << SPI_CFG1_DSIZE_SHIFT)
#define SPI_CFG1_DSIZE_MASK (0x1f << SPI_CFG1_DSIZE_SHIFT)
/* 00000 - 00010 - not used */
# define SPI_CFG1_DSIZE_4BIT (3 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_5BIT (4 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_6BIT (5 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_7BIT (6 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_8BIT (7 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_9BIT (8 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_10BIT (9 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_11BIT (10 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_12BIT (11 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_13BIT (12 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_14BIT (13 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_15BIT (14 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_16BIT (15 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_17BIT (16 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_18BIT (17 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_19BIT (18 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_20BIT (19 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_21BIT (20 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_22BIT (21 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_23BIT (22 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_24BIT (23 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_25BIT (24 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_26BIT (25 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_27BIT (26 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_28BIT (27 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_29BIT (28 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_30BIT (29 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_31BIT (30 << SPI_CFG1_DSIZE_SHIFT)
# define SPI_CFG1_DSIZE_32BIT (31 << SPI_CFG1_DSIZE_SHIFT)
#define SPI_CFG1_FTHLV_SHIFT (5) /* Bits 5-8: FIFO threshold level */
#define SPI_CFG1_FTHLV_MASK (0xf << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_1DATA (0 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_2DATA (1 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_3DATA (2 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_4DATA (3 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_5DATA (4 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_6DATA (5 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_7DATA (6 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_8DATA (7 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_9DATA (8 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_10DATA (9 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_11DATA (10 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_12DATA (11 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_13DATA (12 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_14DATA (13 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_15DATA (14 << SPI_CFG1_FTHLV_SHIFT)
# define SPI_CFG1_FTHLV_16DATA (15 << SPI_CFG1_FTHLV_SHIFT)
#define SPI_CFG1_UDRCFG_SHIFT (9) /* Bits 9-10: behavior of slave transmitter at underrun condition */
#define SPI_CFG1_UDRCFG_MASK (0x3 << SPI_CFG1_UDRCFG_SHIFT)
# define SPI_CFG1_UDRCFG_CONST (0 << SPI_CFG1_UDRCFG_SHIFT)
# define SPI_CFG1_UDRCFG_LASTRX (1 << SPI_CFG1_UDRCFG_SHIFT)
# define SPI_CFG1_UDRCFG_LASTTX (2 << SPI_CFG1_UDRCFG_SHIFT)
/* 11: Reserved */
#define SPI_CFG1_UDRDET_SHIFT (11) /* Bits 11-12: detection of underrun condition at slave transmitter */
#define SPI_CFG1_UDRDET_MASK (0x3 << SPI_CFG1_UDRDET_SHIFT)
# define SPI_CFG1_UDRDET_BEG (0 << SPI_CFG1_UDRDET_SHIFT)
# define SPI_CFG1_UDRDET_END (1 << SPI_CFG1_UDRDET_SHIFT)
# define SPI_CFG1_UDRDET_SS (2 << SPI_CFG1_UDRDET_SHIFT)
/* 11: Reserved */
/* Bit 13: Reserved */
#define SPI_CFG1_RXDMAEN (1 << 14) /* Bit 14: RX-DMA stream enable */
#define SPI_CFG1_TXDMAEN (1 << 15) /* Bit 15: TX-DMA stream enable */
#define SPI_CFG1_CRCSIZE_SHIFT (16) /* Bits 16-20: length of CRC frame to be transacted and compared */
#define SPI_CFG1_CRCSIZE_VAL(n) ((n-1) << SPI_CFG1_CRCSIZE_SHIFT)
#define SPI_CFG1_CRCSIZE_MASK (0x1f << SPI_CFG1_CRCSIZE_SHIFT)
/* 00000-00010: Reserved */
# define SPI_CFG1_CRCSIZE_4BIT (3 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_5BIT (4 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_6BIT (5 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_7BIT (6 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_8BIT (7 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_9BIT (8 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_10BIT (9 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_11BIT (10 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_12BIT (11 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_13BIT (12 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_14BIT (13 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_15BIT (14 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_16BIT (15 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_17BIT (16 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_18BIT (17 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_19BIT (18 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_20BIT (19 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_21BIT (20 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_22BIT (21 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_23BIT (22 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_24BIT (23 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_25BIT (24 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_26BIT (25 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_27BIT (26 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_28BIT (27 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_29BIT (28 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_30BIT (29 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_31BIT (30 << SPI_CFG1_CRCSIZE_SHIFT)
# define SPI_CFG1_CRCSIZE_32BIT (31 << SPI_CFG1_CRCSIZE_SHIFT)
/* Bit 21: Reserved */
#define SPI_CFG1_CRCEN (1 << 22) /* Bit 22: hardware CRC computation enable */
/* Bits 23-27: Reserved */
#define SPI_CFG1_MBR_SHIFT (28) /* Bits 28-30: master baud rate */
#define SPI_CFG1_MBR_MASK (0x7 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd2 (0 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd4 (1 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd8 (2 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd16 (3 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd32 (4 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd64 (5 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd128 (6 << SPI_CFG1_MBR_SHIFT)
# define SPI_CFG1_MBR_FPCLKd256 (7 << SPI_CFG1_MBR_SHIFT)
/* Bit 31: Reserved */
/* SPI configuration register 2 */
#define SPI_CFG2_MSSI_SHIFT (0) /* Bits 0-3:master SS idleness */
#define SPI_CFG2_MSSI_MASK (0xf << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_0CLK (0 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_1CLK (1 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_2CLK (2 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_3CLK (3 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_4CLK (4 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_5CLK (5 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_6CLK (6 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_7CLK (7 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_8CLK (8 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_9CLK (9 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_10CLK (10 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_11CLK (11 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_12CLK (12 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_13CLK (13 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_14CLK (14 << SPI_CFG2_MSSI_SHIFT)
# define SPI_CFG2_MSSI_15CLK (15 << SPI_CFG2_MSSI_SHIFT)
#define SPI_CFG2_MIDI_SHIFT (4) /* Bits 4-7: master Inter-Data idleness */
#define SPI_CFG2_MIDI_MASK (0xf << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_0CLK (0 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_1CLK (1 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_2CLK (2 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_3CLK (3 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_4CLK (4 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_5CLK (5 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_6CLK (6 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_7CLK (7 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_8CLK (8 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_9CLK (9 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_10CLK (10 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_11CLK (11 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_12CLK (12 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_13CLK (13 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_14CLK (14 << SPI_CFG2_MIDI_SHIFT)
# define SPI_CFG2_MIDI_15CLK (15 << SPI_CFG2_MIDI_SHIFT)
/* Bits 8-14: Reserved */
#define SPI_CFG2_IOSWP (1 << 15) /* Bit 15: swap functionality of MISO and MOSI pins */
/* Bit 16: Reserved */
#define SPI_CFG2_COMM_SHIFT (17) /* Bits 17-18: SPI communication mode */
#define SPI_CFG2_COMM_MASK (0x3 << SPI_CFG2_COMM_SHIFT)
# define SPI_CFG2_COMM_FULL (0 << SPI_CFG2_COMM_SHIFT)
# define SPI_CFG2_COMM_STX (1 << SPI_CFG2_COMM_SHIFT)
# define SPI_CFG2_COMM_SRX (2 << SPI_CFG2_COMM_SHIFT)
# define SPI_CFG2_COMM_HALF (3 << SPI_CFG2_COMM_SHIFT)
#define SPI_CFG2_SP_SHIFT (19) /* Bits 19-21: serial protocol */
#define SPI_CFG2_SP_MASK (0x7 << SPI_CFG2_SP_SHIFT)
# define SPI_CFG2_SP_MOTOROLA (0 << SPI_CFG2_SP_SHIFT)
# define SPI_CFG2_SP_TI (1 << SPI_CFG2_SP_SHIFT)
/* 010-111: Reserved */
#define SPI_CFG2_MASTER (1 << 22) /* Bit 22: SPI master */
#define SPI_CFG2_LSBFRST (1 << 23) /* Bit 23: data frame format */
#define SPI_CFG2_CPHA (1 << 24) /* Bit 24: clock phase */
#define SPI_CFG2_CPOL (1 << 25) /* Bit 25: clock polarity */
#define SPI_CFG2_SSM (1 << 26) /* Bit 26: software management of SS signal input */
/* Bit 27: Reserved */
#define SPI_CFG2_SSIOP (1 << 28) /* Bit 28: SS input/output polarity */
#define SPI_CFG2_SSOE (1 << 29) /* Bit 29: SS output enable */
#define SPI_CFG2_SSOM (1 << 30) /* Bit 30: SS output management in master mode */
#define SPI_CFG2_AFCNTR (1 << 31) /* Bit 31: alternate function GPIOs control */
/* SPI/I2S status register */
#define SPI_SR_RXP (1 << 0) /* Bit 0: Rx-packet available */
#define SPI_SR_TXP (1 << 1) /* Bit 1: Tx-packet space available */
#define SPI_SR_DXP (1 << 2) /* Bit 2: duplex packet */
#define SPI_SR_EOT (1 << 3) /* Bit 3: end of transfer */
#define SPI_SR_TXTF (1 << 4) /* Bit 4: transmission transfer filled */
#define SPI_SR_UDR (1 << 5) /* Bit 5: underrun at slave transmission mode */
#define SPI_SR_OVR (1 << 6) /* Bit 6: overrun */
#define SPI_SR_CRCE (1 << 7) /* Bit 7: CRC error */
#define SPI_SR_TIFRE (1 << 8) /* Bit 8: TI frame format error */
#define SPI_SR_MODF (1 << 9) /* Bit 9: mode fault */
#define SPI_SR_TSERF (1 << 10) /* Bit 10: additional number of SPI data to be transacted was reload */
#define SPI_SR_SUSP (1 << 11) /* Bit 11: suspend */
#define SPI_SR_TXC (1 << 12) /* Bit 12: TxFIFO transmission complete */
#define SPI_SR_RXPLVL_SHIFT (13) /* Bits 13-14: RxFIFO packing level */
#define SPI_SR_RXPLVL_MASK (1 << SPI_SR_RXPLVL_SHIFT)
#define SPI_SR_RXWNE (1 << 15) /* Bit 15: RxFIFO word not empty */
#define SPI_SR_CTSIZE_SHIFT (16) /* Bits 16-31: number of data frames remaining in current TSIZE session */
#define SPI_SR_CTSIZE_MASK (1 << SPI_SR_CTSIZE_SHIFT)
/* SPI/I2S interrupt/status flags interrupt enable register */
#define SPI_IER_RXPIE (1 << 0) /* Bit 0: RXP Interrupt enable */
#define SPI_IER_TXPIE (1 << 1) /* Bit 1: TXP interrupt enable */
#define SPI_IER_DXPIE (1 << 2) /* Bit 2: DXP interrupt enable */
#define SPI_IER_EOTIE (1 << 3) /* Bit 3: EOT, SUSP and TXC interrupt enable */
#define SPI_IER_TXTFIE (1 << 4) /* Bit 4: TXTFIE interrupt enable */
#define SPI_IER_UDRIE (1 << 5) /* Bit 5: UDR interrupt enable */
#define SPI_IER_OVRIE (1 << 6) /* Bit 6: OVR interrupt enable */
#define SPI_IER_CRCEIE (1 << 7) /* Bit 7: CRC error interrupt enable */
#define SPI_IER_TIFREIE (1 << 8) /* Bit 8: TIFRE interrupt enable */
#define SPI_IER_MODFIE (1 << 9) /* Bit 9: mode fault interrupt enable */
#define SPI_IER_TSERFIE (1 << 10) /* Bit 10: additional number of transactions
* reload interrupt enable */
/* SPI/I2S interrupt/status flags clear register */
/* Bits 0-2: Reserved */
#define SPI_IFCR_EOTC (1 << 3) /* Bit 3: end of transfer flag clear */
#define SPI_IFCR_TXTFC (1 << 4) /* Bit 4: transmission Transfer Flilled flag clear */
#define SPI_IFCR_UDRC (1 << 5) /* Bit 5: underrun flag clear */
#define SPI_IFCR_OVRC (1 << 6) /* Bit 6: overrun flag clear */
#define SPI_IFCR_CRCEC (1 << 7) /* Bit 7: CRC error flag clear */
#define SPI_IFCR_TIFREC (1 << 8) /* Bit 8: TI frame format error flag clear */
#define SPI_IFCR_MODFC (1 << 9) /* Bit 9: mode fault flag clear */
#define SPI_IFCR_TSERFC (1 << 10) /* Bit 10: TSERF flag clear*/
#define SPI_IFCR_SUSPC (1 << 11) /* Bit 11: suspend flag clear */
/* Bits 12-31: Reserved */
/* SPI/I2S transmit data register */
#define SPI_TXDR_TXDR_SHIFT (0) /* Bits 0-15: transmit data register */
#define SPI_TXDR_TXDR_MASK (0xffff << SPI_TXDR_TXDR_SHIFT)
/* Bits 16-31: write ignored */
/* SPI/I2S receive data register */
#define SPI_RXDR_RXDR_SHIFT (0) /* Bits 0-15: receive data register */
#define SPI_RXDR_RXDR_MASK (0xffff << SPI_RXDR_RXDR_SHIFT)
/* Bits 16-31: read zero */
/* SPI/I2S SPI polynominal register */
#define SPI_CRCPOLY_CRCPOLY_SHIFT (0) /* Bits 0-15: CRC polynominal register */
#define SPI_CRCPOLY_CRCPOLY_MASK (0xffff << SPI_CRCPOLY_CRCPOLY_SHIFT)
/* Bits 16-31: write ignored */
/* SPI/I2S SPI transmitter CRC register */
#define SPI_TXCRC_TXCRC_SHIFT (0) /* Bits 0-15: CRC register for transmitter */
#define SPI_TXCRC_TXCRC_MASK (0xffff << SPI_TXCRC_TXCRC_SHIFT)
/* Bits 16-31: write ignored */
/* SPI/I2S SPI receiver CRC register */
#define SPI_RXCRC_RXCRC_SHIFT (0) /* Bits 0-15: CRC register for receiver */
#define SPI_RXCRC_RXCRC_MASK (0xffff << SPI_RXCRC_RXCRC_SHIFT)
/* Bits 16-31: read zero */
/* SPI/I2S SPI underrun data register */
#define SPI_UDRDR_UDRDR_SHIFT (0) /* Bits 0-15: data at slave underrun condition*/
#define SPI_UDRDR_UDRDR_MASK (0xffff << SPI_UDRDR_UDRDR_SHIFT)
/* Bits 16-31: read zero */
#endif /* CONFIG_STM32U5_STM32U585XX */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SPI_H */

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/****************************************************************************
* arch/arm/src/stm32u5/hardware/stm32u585xx_syscfg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SYSCFG_H
#define __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SYSCFG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define STM32U5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */
#define STM32U5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */
#define STM32U5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */
#define STM32U5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */
#define STM32U5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */
#define STM32U5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */
#define STM32U5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */
#define STM32U5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */
#define STM32U5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */
#define STM32U5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */
#define STM32U5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */
/* Register Addresses *******************************************************/
#define STM32U5_SYSCFG_SECCFGR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SECCFGR_OFFSET)
#define STM32U5_SYSCFG_CFGR1 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR1_OFFSET)
#define STM32U5_SYSCFG_FPUIMR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_FPUIMR_OFFSET)
#define STM32U5_SYSCFG_CNSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CNSLCKR_OFFSET)
#define STM32U5_SYSCFG_CSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CSLCKR_OFFSET)
#define STM32U5_SYSCFG_CFGR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR2_OFFSET)
#define STM32U5_SYSCFG_SCSR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SCSR_OFFSET)
#define STM32U5_SYSCFG_SKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SKR_OFFSET)
#define STM32U5_SYSCFG_SWPR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR_OFFSET)
#define STM32U5_SYSCFG_SWPR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR2_OFFSET)
#define STM32U5_SYSCFG_RSSCMDR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_RSSCMDR_OFFSET)
/* Register Bitfield Definitions ********************************************/
/* SYSCFG secure configuration register */
#define SYSCFG_SECCFGR_SYSCFGSEC (1 << 0) /* SYSCFG clock control security */
#define SYSCFG_SECCFGR_CLASSBSEC (1 << 1) /* ClassB security */
#define SYSCFG_SECCFGR_SRAM2SEC (1 << 2) /* SRAM2 security */
#define SYSCFG_SECCFGR_FPUSEC (1 << 3) /* FPU security */
/* SYSCFG configuration register 1 */
#define SYSCFG_CFGR1_BOOSTEN (1 << 8) /* Bit 8: I/O analog switch voltage booster enable (use when vdd is low) */
#define SYSCFG_CFGR1_ANASWVDD (1 << 9) /* Bit 9: GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_I2C_PB6_FMP (1 << 16) /* Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6 */
#define SYSCFG_CFGR1_I2C_PB7_FMP (1 << 17) /* Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7 */
#define SYSCFG_CFGR1_I2C_PB8_FMP (1 << 18) /* Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8 */
#define SYSCFG_CFGR1_I2C_PB9_FMP (1 << 19) /* Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9 */
#define SYSCFG_CFGR1_I2C1_FMP (1 << 20) /* Bit 20: I2C1 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C2_FMP (1 << 21) /* Bit 21: I2C2 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C3_FMP (1 << 22) /* Bit 22: I2C3 Fast-mode Plus (Fm+) driving capability activation */
#define SYSCFG_CFGR1_I2C4_FMP (1 << 23) /* Bit 23: I2C4 Fast-mode Plus (Fm+) driving capability activation */
/* SYSCFG FPU interrupt mask register */
#define SYSCFG_FPUIMR_IE0 (1 << 0) /* Bit 0: FPU Invalid operation interrupt enable */
#define SYSCFG_FPUIMR_IE1 (1 << 1) /* Bit 1: FPU Divide-by-zero interrupt enable */
#define SYSCFG_FPUIMR_IE2 (1 << 2) /* Bit 2: FPU Underflow interrupt enable */
#define SYSCFG_FPUIMR_IE3 (1 << 3) /* Bit 3: FPU Overflow interrupt enable */
#define SYSCFG_FPUIMR_IE4 (1 << 4) /* Bit 4: FPU Input abnormal interrupt enable */
#define SYSCFG_FPUIMR_IE5 (1 << 5) /* Bit 5: FPU Inexact interrupt enable */
/* SYSCFG CPU non-secure lock register */
#define SYSCFG_CNSLCKR_LOCKNSVTOR (1 << 0) /* Bit 0: VTOR_NS register lock */
#define SYSCFG_CNSLCKR_LOCKNSMPU (1 << 1) /* Bit 1: Non-seucre MPU registers lock */
/* SYSCFG CPU secure lock register */
#define SYSCFG_CSLCKR_LOCKSVTAIRCR (1 << 0) /* Bit 0: VTOR_S register and AIRCR register bits lock */
#define SYSCFG_CSLCKR_LOCKSMPU (1 << 1) /* Bit 1: Secure MPU registers lock */
#define SYSCFG_CSLCKR_LOCKSAU (1 << 2) /* Bit 2: SAU registers lock */
/* SYSCFG configuration register 2 */
#define SYSCFG_CFGR2_CLL (1 << 0) /* Bit 0: Cortex-M33 LOCKUP (hardfault) output enable */
#define SYSCFG_CFGR2_SPL (1 << 1) /* Bit 1: SRAM2 parity lock */
#define SYSCFG_CFGR2_PVDL (1 << 2) /* Bit 2: PVD lock enable */
#define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock */
#define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */
/* SYSCFG SRAM2 control and status register */
#define SYSCFG_SCSR_SRAM2ER (1 << 0) /* Bit 0: SRAM2 Erase */
#define SYSCFG_SCSR_SRAM2BSY (1 << 1) /* Bit 1: SRAM2 busy in erase operation */
/* SYSCFG SRAM2 key register */
#define SYSCFG_SKR_SHIFT 0
#define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT)
/* SYSCFG SRAM2 write protection register 1 and 2: There is one bit per SRAM2
* page (0 to 31 and 32 to 63, respectively).
*/
/* SYSCFG RSS command register */
#define SYSCFG_RSSCMDR_SHIFT 0
#define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT)
#endif /* CONFIG_STM32U5_STM32U585XX */
#endif /* __ARCH_ARM_SRC_STM32U5_HARDWARE_STM32U585XX_SYSCFG_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_H
#define __ARCH_ARM_SRC_STM32U5_STM32_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
/* Peripherals **************************************************************/
#include "chip.h"
#include "stm32_dbgmcu.h"
#include "stm32_flash.h"
#include "stm32_gpio.h"
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#include "stm32_spi.h"
#include "stm32_tim.h"
#include "stm32_uart.h"
#include "stm32_lowputc.h"
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <nuttx/userspace.h>
#include <arch/board/board.h>
#include "chip.h"
#include "mpu.h"
#include "arm_arch.h"
#include "arm_internal.h"
#include "stm32_mpuinit.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Internal SRAM is available in all members of the STM32U5 family. The
* following definitions must be provided to specify the size and
* location of internal (system) SRAM1 and SRAM2:
*
* SRAM1_START 0x20000000
* SRAM1_END
* SRAM2_START 0x10000000
* SRAM2_END
*
* In addition to internal SRAM, memory may also be available through the
* FSMC. In order to use FSMC SRAM, the following additional things need to
* be present in the NuttX configuration file:
*
* CONFIG_STM32U5_FSMC=y : Enables the FSMC
* CONFIG_STM32U5_FSMC_SRAM=y : Indicates that SRAM is available via the
* FSMC (as opposed to an LCD or FLASH).
* CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
* address space
* CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
* address space
* CONFIG_MM_REGIONS : Must be set to a large enough value to
* include the additional regions.
*/
#ifndef CONFIG_STM32U5_FSMC
# undef CONFIG_STM32U5_FSMC_SRAM
#endif
/* STM32U5[7,8]6xx have 128 Kib in two banks, both accessible to DMA:
*
* 1) 96 KiB of System SRAM beginning at address 0x2000:0000 - 0x2001:8000
* 2) 32 KiB of System SRAM beginning at address 0x1000:0000 - 0x1000:8000
*
* STM32U596xx have 320 Kib in two banks, both accessible to DMA:
*
* 1) 256 KiB of System SRAM beginning at address 0x2000:0000 - 0x2004:0000
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
*
* STM32U5Rxxx have 640 Kib in three banks:
*
* 1) 192 KiB of System SRAM beginning at address 0x2000:0000 - 0x2003:0000
* 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000
* 3) 384 KiB of System SRAM beginning at address 0x2004:0000 - 0x200A:0000
*
* In addition, external FSMC SRAM may be available.
*/
/* Set the range of system SRAM */
#define SRAM1_START STM32_SRAM_BASE
#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE)
/* Set the range of SRAM2 as well, requires a second memory region */
#define SRAM2_START STM32_SRAM2_BASE
#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE)
/* Set the range of SRAM3, requiring a third memory region */
#ifdef STM32_SRAM3_SIZE
# define SRAM3_START STM32_SRAM3_BASE
# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE)
#endif
/* Some sanity checking. If multiple memory regions are defined, verify
* that CONFIG_MM_REGIONS is set to match the number of memory regions
* that we have been asked to add to the heap.
*/
#if CONFIG_MM_REGIONS < defined(CONFIG_STM32U5_SRAM2_HEAP) + \
defined(CONFIG_STM32U5_SRAM3_HEAP) + \
defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1
# error "You need more memory manager regions to support selected heap components"
#endif
#if CONFIG_MM_REGIONS > defined(CONFIG_STM32U5_SRAM2_HEAP) + \
defined(CONFIG_STM32U5_SRAM3_HEAP) + \
defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1
# warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are"
#endif
/* If FSMC SRAM is going to be used as heap, then verify that the starting
* address and size of the external SRAM region has been provided in the
* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
*/
#ifdef CONFIG_STM32U5_FSMC_SRAM
# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
# error "CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
# undef CONFIG_STM32U5_FSMC_SRAM
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_heap_color
*
* Description:
* Set heap memory to a known, non-zero state to checking heap usage.
*
****************************************************************************/
#ifdef CONFIG_HEAP_COLORATION
static inline void up_heap_color(FAR void *start, size_t size)
{
memset(start, HEAP_COLOR, size);
}
#else
# define up_heap_color(start,size)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region. Size determined at link time.
* Kernel .bss region Size determined at link time.
* Kernel IDLE thread stack. Size given by CONFIG_IDLETHREAD_STACKSIZE.
* Padding for alignment
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
* Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
* User heap. Extends to the end of SRAM.
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
/* Colorize the heap for debug */
up_heap_color((FAR void *)ubase, usize);
/* Allow user-mode access to the user heap memory */
stm32_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;
/* Colorize the heap for debug */
up_heap_color(*heap_start, *heap_size);
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* (and protects) the kernel-space heap.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM1_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM1_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM1_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((SRAM1_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = SRAM1_END - usize;
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (FAR void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
/****************************************************************************
* Name: arm_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
#ifdef CONFIG_STM32U5_SRAM2_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the SRAM2 heap */
stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
/* Add the SRAM2 user heap region. */
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END - SRAM2_START);
#endif /* SRAM2 */
#ifdef CONFIG_STM32U5_SRAM3_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the SRAM3 heap */
stm32_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)SRAM3_START, SRAM3_END - SRAM3_START);
/* Add the SRAM3 user heap region. */
kumm_addregion((FAR void *)SRAM3_START, SRAM3_END - SRAM3_START);
#endif /* SRAM3 */
#ifdef CONFIG_STM32U5_FSMC_SRAM_HEAP
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the FSMC SRAM user heap memory */
stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
/* Colorize the heap for debug */
up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
/* Add the external FSMC SRAM user heap region. */
kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
}
#endif

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_dbgmcu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_DBGMCU_H
#define __ARCH_ARM_SRC_STM32U5_STM32_DBGMCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_dbgmcu.h"
#else
# error "Unsupported STM32U5 chip"
#endif
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_DBGMCU_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_dumpgpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Output debug info even if debug output is not selected. */
#undef CONFIG_DEBUG_INFO
#define CONFIG_DEBUG_INFO 1
#include <sys/types.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "arm_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_rcc.h"
#ifdef CONFIG_DEBUG_FEATURES
/****************************************************************************
* Private Data
****************************************************************************/
/* Port letters for prettier debug output */
static const char g_portchar[STM32_NPORTS] =
{
#if STM32_NPORTS > 11
# error "Additional support required for this number of GPIOs"
#elif STM32_NPORTS > 10
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K'
#elif STM32_NPORTS > 9
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J'
#elif STM32_NPORTS > 8
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I'
#elif STM32_NPORTS > 7
'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H'
#elif STM32_NPORTS > 6
'A', 'B', 'C', 'D', 'E', 'F', 'G'
#elif STM32_NPORTS > 5
'A', 'B', 'C', 'D', 'E', 'F'
#elif STM32_NPORTS > 4
'A', 'B', 'C', 'D', 'E'
#elif STM32_NPORTS > 3
'A', 'B', 'C', 'D'
#elif STM32_NPORTS > 2
'A', 'B', 'C'
#elif STM32_NPORTS > 1
'A', 'B'
#elif STM32_NPORTS > 0
'A'
#else
# error "Bad number of GPIOs"
#endif
};
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: stm32_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
*
****************************************************************************/
int stm32_dumpgpio(uint32_t pinset, const char *msg)
{
irqstate_t flags;
uint32_t base;
unsigned int port;
/* Get the base address associated with the GPIO port */
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
base = g_gpiobase[port];
/* The following requires exclusive access to the GPIO registers */
flags = enter_critical_section();
DEBUGASSERT(port < STM32_NPORTS);
_info("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
if ((getreg32(STM32_RCC_AHB2ENR1) & RCC_AHB2ENR1_GPIOEN(port)) != 0)
{
_info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n",
getreg32(base + STM32_GPIO_MODER_OFFSET),
getreg32(base + STM32_GPIO_OTYPER_OFFSET),
getreg32(base + STM32_GPIO_OSPEED_OFFSET),
getreg32(base + STM32_GPIO_PUPDR_OFFSET));
_info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n",
getreg32(base + STM32_GPIO_IDR_OFFSET),
getreg32(base + STM32_GPIO_ODR_OFFSET),
getreg32(base + STM32_GPIO_BSRR_OFFSET),
getreg32(base + STM32_GPIO_LCKR_OFFSET));
_info(" AFRH: %08x AFRL: %08x\n",
getreg32(base + STM32_GPIO_AFRH_OFFSET),
getreg32(base + STM32_GPIO_AFRL_OFFSET));
}
else
{
_info(" GPIO%c not enabled: AHB2ENR: %08x\n",
g_portchar[port], getreg32(STM32_RCC_AHB2ENR1));
}
leave_critical_section(flags);
return OK;
}
#endif /* CONFIG_DEBUG_FEATURES */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_exti.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_EXTI_H
#define __ARCH_ARM_SRC_STM32U5_STM32_EXTI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "hardware/stm32_exti.h"
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Input Parameters:
* pinset - GPIO pin configuration
* risingedge - Enables interrupt on rising edges
* fallingedge - Enables interrupt on falling edges
* event - Generate event when set
* func - When non-NULL, generate interrupt
* arg - Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) is returned on success, otherwise a negated errno value is
* returned to indicate the nature of the failure.
*
****************************************************************************/
int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
/****************************************************************************
* Name: stm32_exti_alarm
*
* Description:
* Sets/clears EXTI alarm interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg);
#endif
/****************************************************************************
* Name: stm32_exti_wakeup
*
* Description:
* Sets/clears EXTI wakeup interrupt.
*
* Input Parameters:
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure indicating the
* nature of the failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_PERIODIC
int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event,
xcpt_t func, void *arg);
#endif
/****************************************************************************
* Name: stm32_exti_comp
*
* Description:
* Sets/clears comparator based events and interrupt triggers.
*
* Input Parameters:
* - cmp: comparator
* - rising/falling edge: enables interrupt on rising/falling edges
* - event: generate event when set
* - func: when non-NULL, generate interrupt
* - arg: Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
#ifdef CONFIG_STM32U5_COMP
int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_EXTI_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_exti_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include "arm_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "stm32_exti.h"
/****************************************************************************
* Private Types
****************************************************************************/
struct gpio_callback_s
{
xcpt_t callback; /* Callback entry point */
void *arg; /* The argument that accompanies the callback */
};
/****************************************************************************
* Private Data
****************************************************************************/
/* Interrupt handlers attached to each EXTI */
static struct gpio_callback_s g_gpio_handlers[16];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Interrupt Service Routine - Dispatcher
****************************************************************************/
static int stm32_exti0_15_isr(int irq, void *context, FAR void *arg)
{
int ret = OK;
int exti;
exti = irq - STM32_IRQ_EXTI0;
DEBUGASSERT((exti >= 0) && (exti <= 15));
/* Clear the pending interrupt for both rising and falling edges. */
putreg32(0x0001 << exti, STM32_EXTI_RPR1);
putreg32(0x0001 << exti, STM32_EXTI_FPR1);
/* And dispatch the interrupt to the handler */
if (g_gpio_handlers[exti].callback != NULL)
{
xcpt_t callback = g_gpio_handlers[exti].callback;
void *cbarg = g_gpio_handlers[exti].arg;
ret = callback(irq, context, cbarg);
}
return ret;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Input Parameters:
* pinset - GPIO pin configuration
* risingedge - Enables interrupt on rising edges
* fallingedge - Enables interrupt on falling edges
* event - Generate event when set
* func - When non-NULL, generate interrupt
* arg - Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) is returned on success, otherwise a negated errno value is
* returned to indicate the nature of the failure.
*
****************************************************************************/
int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg)
{
uint32_t pin = pinset & GPIO_PIN_MASK;
uint32_t exti = 1 << pin;
int irq = STM32_IRQ_EXTI0 + pin;
g_gpio_handlers[pin].callback = func;
g_gpio_handlers[pin].arg = arg;
/* Install external interrupt handlers */
if (func)
{
irq_attach(irq, stm32_exti0_15_isr, NULL);
up_enable_irq(irq);
}
else
{
up_disable_irq(irq);
}
/* Configure GPIO, enable EXTI line enabled if event or interrupt is
* enabled.
*/
if (event || func)
{
pinset |= GPIO_EXTI;
}
stm32_configgpio(pinset);
/* Configure rising/falling edges */
modifyreg32(STM32_EXTI_RTSR1,
risingedge ? 0 : exti,
risingedge ? exti : 0);
modifyreg32(STM32_EXTI_FTSR1,
fallingedge ? 0 : exti,
fallingedge ? exti : 0);
/* Enable Events and Interrupts */
modifyreg32(STM32_EXTI_EMR1,
event ? 0 : exti,
event ? exti : 0);
modifyreg32(STM32_EXTI_IMR1,
func ? 0 : exti,
func ? exti : 0);
return OK;
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_flash.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* Provides standard flash access functions, to be used by the flash mtd
* driver. The interface is defined in the include/nuttx/progmem.h
*
* Notes about this implementation:
* - HSI16 is automatically turned ON by MCU, if not enabled beforehand
* - Only Standard Programming is supported, no Fast Programming.
* - Low Power Modes are not permitted during write/erase
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/progmem.h>
#include <semaphore.h>
#include <assert.h>
#include <debug.h>
#include <errno.h>
#include <string.h>
#include "stm32_rcc.h"
#include "stm32_waste.h"
#include "stm32_flash.h"
#include "arm_arch.h"
#if !(defined(CONFIG_STM32U5_STM32U585XX))
# error "Unrecognized STM32 chip"
#endif
#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT)
# warning "Flash Configuration has been overridden - make sure it is correct"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define FLASH_KEY1 0x45670123
#define FLASH_KEY2 0xCDEF89AB
#define OPTBYTES_KEY1 0x08192A3B
#define OPTBYTES_KEY2 0x4C5D6E7F
#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE
#define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4)
#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
#if FLASH_PAGE_SIZE == 2048
# define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */
#elif FLASH_PAGE_SIZE == 4096
# define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */
#elif FLASH_PAGE_SIZE == 8192
# define FLASH_PAGE_SHIFT (13) /* 2**13 = 8192B */
#else
# error Unsupported STM32_FLASH_PAGESIZE
#endif
#define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT)
#define FLASH_NSCR_PAGE_ERASE FLASH_NSCR_PER
#define FLASH_NSSR_WRITE_PROTECTION_ERROR FLASH_NSSR_WRPERR
/* All errors for Standard Programming, not for other operations. */
#define FLASH_NSSR_ALLERRS (FLASH_NSSR_PGSERR | FLASH_NSSR_SIZERR | \
FLASH_NSSR_PGAERR | FLASH_NSSR_WRPERR | \
FLASH_NSSR_PROGERR)
#ifndef MIN
# define MIN(a, b) ((a) < (b) ? (a) : (b))
#endif
/****************************************************************************
* Private Data
****************************************************************************/
static sem_t g_sem = SEM_INITIALIZER(1);
static uint32_t g_page_buffer[FLASH_PAGE_WORDS];
/****************************************************************************
* Private Functions
****************************************************************************/
static inline void sem_lock(void)
{
int ret;
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&g_sem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
}
static inline void sem_unlock(void)
{
nxsem_post(&g_sem);
}
static void flash_unlock(void)
{
while (getreg32(STM32_FLASH_NSSR) & FLASH_NSSR_BSY)
{
stm32_waste();
}
if (getreg32(STM32_FLASH_NSCR) & FLASH_NSCR_LOCK)
{
/* Unlock sequence */
putreg32(FLASH_KEY1, STM32_FLASH_NSKEYR);
putreg32(FLASH_KEY2, STM32_FLASH_NSKEYR);
}
}
static void flash_lock(void)
{
modifyreg32(STM32_FLASH_NSCR, 0, FLASH_NSCR_LOCK);
}
static void flash_optbytes_unlock(void)
{
flash_unlock();
if (getreg32(STM32_FLASH_NSCR) & FLASH_NSCR_OPTLOCK)
{
/* Unlock Option Bytes sequence */
putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR);
putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR);
}
}
static inline void flash_optbytes_lock(void)
{
/* We don't need to set OPTLOCK here as it is automatically
* set by MCU when flash_lock() sets LOCK.
*/
flash_lock();
}
static inline void flash_erase(size_t page)
{
finfo("erase page %u\n", page);
modifyreg32(STM32_FLASH_NSCR, 0, FLASH_NSCR_PAGE_ERASE);
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_PNB_MASK, FLASH_NSCR_PNB(page));
modifyreg32(STM32_FLASH_NSCR, 0, FLASH_NSCR_STRT);
while (getreg32(STM32_FLASH_NSSR) & FLASH_NSSR_BSY)
{
stm32_waste();
}
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_PAGE_ERASE, 0);
}
/****************************************************************************
* Public Functions
****************************************************************************/
void stm32_flash_unlock(void)
{
sem_lock();
flash_unlock();
sem_unlock();
}
void stm32_flash_lock(void)
{
sem_lock();
flash_lock();
sem_unlock();
}
/****************************************************************************
* Name: stm32_flash_user_optbytes
*
* Description:
* Modify the contents of the user option bytes (USR OPT) on the flash.
* This does not set OBL_LAUNCH so new options take effect only after
* next power reset.
*
* Input Parameters:
* clrbits - Bits in the option bytes to be cleared
* setbits - Bits in the option bytes to be set
*
* Returned Value:
* Option bytes after operation is completed
*
****************************************************************************/
uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits)
{
uint32_t regval;
/* To avoid accidents, do not allow setting RDP via this function.
* Remove these asserts if want to enable changing the protection level.
* WARNING: level 2 protection is permanent!
*/
DEBUGASSERT((clrbits & FLASH_OPTR_RDP_MASK) == 0);
DEBUGASSERT((setbits & FLASH_OPTR_RDP_MASK) == 0);
sem_lock();
flash_optbytes_unlock();
/* Modify Option Bytes in register. */
regval = getreg32(STM32_FLASH_OPTR);
finfo("Flash option bytes before: 0x%x\n", (unsigned)regval);
regval = (regval & ~clrbits) | setbits;
putreg32(regval, STM32_FLASH_OPTR);
finfo("Flash option bytes after: 0x%x\n", (unsigned)regval);
/* Start Option Bytes programming and wait for completion. */
modifyreg32(STM32_FLASH_NSCR, 0, FLASH_NSCR_OPTSTRT);
while (getreg32(STM32_FLASH_NSSR) & FLASH_NSSR_BSY)
{
stm32_waste();
}
flash_optbytes_lock();
sem_unlock();
return regval;
}
size_t up_progmem_pagesize(size_t page)
{
return STM32_FLASH_PAGESIZE;
}
size_t up_progmem_erasesize(size_t block)
{
return STM32_FLASH_PAGESIZE;
}
ssize_t up_progmem_getpage(size_t addr)
{
if (addr >= STM32_FLASH_BASE)
{
addr -= STM32_FLASH_BASE;
}
if (addr >= STM32_FLASH_SIZE)
{
return -EFAULT;
}
return addr / STM32_FLASH_PAGESIZE;
}
size_t up_progmem_getaddress(size_t page)
{
if (page >= STM32_FLASH_NPAGES)
{
return SIZE_MAX;
}
return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE;
}
size_t up_progmem_neraseblocks(void)
{
return STM32_FLASH_NPAGES;
}
bool up_progmem_isuniform(void)
{
return true;
}
ssize_t up_progmem_eraseblock(size_t block)
{
if (block >= STM32_FLASH_NPAGES)
{
return -EFAULT;
}
/* Erase single block */
sem_lock();
flash_unlock();
flash_erase(block);
flash_lock();
sem_unlock();
/* Verify */
if (up_progmem_ispageerased(block) == 0)
{
return up_progmem_erasesize(block);
}
else
{
return -EIO;
}
}
ssize_t up_progmem_ispageerased(size_t page)
{
size_t addr;
size_t count;
size_t bwritten = 0;
if (page >= STM32_FLASH_NPAGES)
{
return -EFAULT;
}
/* Verify */
for (addr = up_progmem_getaddress(page), count = up_progmem_pagesize(page);
count; count--, addr++)
{
if (getreg8(addr) != 0xff)
{
bwritten++;
}
}
return bwritten;
}
ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen)
{
uint32_t *dest;
const uint32_t *src;
size_t written;
size_t xfrsize;
size_t offset;
size_t page;
int i;
int ret = OK;
/* Check for valid address range. */
offset = addr;
if (addr >= STM32_FLASH_BASE)
{
offset -= STM32_FLASH_BASE;
}
if (offset + buflen > STM32_FLASH_SIZE)
{
return -EFAULT;
}
/* Get the page number corresponding to the flash offset and the byte
* offset into the page. Align write destination to page boundary.
*/
page = FLASH_BYTE2PAGE((uint32_t)offset);
offset &= FLASH_PAGE_MASK;
dest = (uint32_t *)((uint8_t *)addr - offset);
written = 0;
sem_lock();
/* Get flash ready and begin flashing. */
flash_unlock();
/* Loop until all of the data has been written */
while (buflen > 0)
{
/* How much can we write into this page? */
xfrsize = MIN((size_t)FLASH_PAGE_SIZE - offset, buflen);
/* Do we need to use the intermediate buffer? */
if (offset == 0 && xfrsize == FLASH_PAGE_SIZE)
{
/* No, we can take the data directly from the user buffer */
src = (const uint32_t *)buf;
}
else
{
/* Yes, copy data into global page buffer */
if (offset > 0)
{
memcpy(g_page_buffer, dest, offset);
}
memcpy((uint8_t *)g_page_buffer + offset, buf, xfrsize);
if (offset + xfrsize < FLASH_PAGE_SIZE)
{
memcpy((uint8_t *)g_page_buffer + offset + xfrsize,
(const uint8_t *)dest + offset + xfrsize,
FLASH_PAGE_SIZE - offset - xfrsize);
}
src = g_page_buffer;
}
/* Erase the page. Unlike most flash chips, STM32 is unable to
* write back existing data read from page without erase.
*/
flash_erase(page);
/* Write the page. Must be with double-words. */
modifyreg32(STM32_FLASH_NSCR, 0, FLASH_NSCR_PG);
for (i = 0; i < FLASH_PAGE_WORDS; i += 2)
{
*dest++ = *src++;
*dest++ = *src++;
while (getreg32(STM32_FLASH_NSSR) & FLASH_NSSR_BSY)
{
stm32_waste();
}
/* Verify */
if (getreg32(STM32_FLASH_NSSR) & FLASH_NSSR_WRITE_PROTECTION_ERROR)
{
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_PG, 0);
ret = -EROFS;
goto out;
}
if (getreg32(dest - 1) != *(src - 1) ||
getreg32(dest - 2) != *(src - 2))
{
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_PG, 0);
ret = -EIO;
goto out;
}
}
modifyreg32(STM32_FLASH_NSCR, FLASH_NSCR_PG, 0);
/* Adjust pointers and counts for the next time through the loop */
written += xfrsize;
addr += xfrsize;
dest = (uint32_t *)addr;
buf = (void *)((uintptr_t)buf + xfrsize);
buflen -= xfrsize;
page++;
}
out:
/* If there was an error, clear all error flags in status
* register (rc_w1 register so do this by writing the
* error bits).
*/
if (ret != OK)
{
ferr("flash write error: %d, status: 0x%x\n", ret,
(unsigned)getreg32(STM32_FLASH_NSSR));
modifyreg32(STM32_FLASH_NSSR, 0, FLASH_NSSR_ALLERRS);
}
flash_lock();
sem_unlock();
return (ret == OK) ? written : ret;
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_flash.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_FLASH_H
#define __ARCH_ARM_SRC_STM32U5_STM32_FLASH_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/stm32_flash.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void stm32_flash_lock(void);
void stm32_flash_unlock(void);
/****************************************************************************
* Name: stm32_flash_user_optbytes
*
* Description:
* Modify the contents of the user option bytes (USR OPT) on the flash.
* This does not set OBL_LAUNCH so new options take effect only after
* next power reset.
*
* Input Parameters:
* clrbits - Bits in the option bytes to be cleared
* setbits - Bits in the option bytes to be set
*
* Returned Value:
* Option bytes after operation is completed
*
****************************************************************************/
uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits);
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_FLASH_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_gpio.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include <arch/stm32u5/chip.h>
#include "arm_arch.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "hardware/stm32_syscfg.h"
/****************************************************************************
* Public Data
****************************************************************************/
/* Base addresses for each GPIO block */
const uint32_t g_gpiobase[STM32_NPORTS] =
{
#if STM32_NPORTS > 0
STM32_GPIOA_BASE,
#endif
#if STM32_NPORTS > 1
STM32_GPIOB_BASE,
#endif
#if STM32_NPORTS > 2
STM32_GPIOC_BASE,
#endif
#if STM32_NPORTS > 3
STM32_GPIOD_BASE,
#endif
#if STM32_NPORTS > 4
STM32_GPIOE_BASE,
#endif
#if STM32_NPORTS > 5
STM32_GPIOF_BASE,
#endif
#if STM32_NPORTS > 6
STM32_GPIOG_BASE,
#endif
#if STM32_NPORTS > 7
STM32_GPIOH_BASE,
#endif
#if STM32_NPORTS > 8
STM32_GPIOI_BASE,
#endif
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: stm32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
* no mutual exclusion is necessary.
*
****************************************************************************/
void stm32_gpioinit(void)
{
}
/****************************************************************************
* Name: stm32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port, or when pin is locked as ALT
* function.
*
* To-Do: Auto Power Enable
****************************************************************************/
int stm32_configgpio(uint32_t cfgset)
{
uintptr_t base;
uint32_t regval;
uint32_t setting;
unsigned int regoffset;
unsigned int port;
unsigned int pin;
unsigned int pos;
unsigned int pinmode;
irqstate_t flags;
/* Verify that this hardware supports the select GPIO port */
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port >= STM32_NPORTS)
{
return -EINVAL;
}
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number and select the port configuration register for that
* pin
*/
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Set up the mode register (and remember whether the pin mode) */
switch (cfgset & GPIO_MODE_MASK)
{
default:
case GPIO_INPUT: /* Input mode */
pinmode = GPIO_MODER_INPUT;
break;
case GPIO_OUTPUT: /* General purpose output mode */
/* Set the initial output value */
stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
pinmode = GPIO_MODER_OUTPUT;
break;
case GPIO_ALT: /* Alternate function mode */
pinmode = GPIO_MODER_ALT;
break;
case GPIO_ANALOG: /* Analog mode */
pinmode = GPIO_MODER_ANALOG;
break;
}
/* Interrupts must be disabled from here on out so that we have mutually
* exclusive access to all of the GPIO configuration registers.
*/
flags = enter_critical_section();
/* Now apply the configuration to the mode register */
regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
regval &= ~GPIO_MODER_MASK(pin);
regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_MODER_OFFSET);
/* Set up the pull-up/pull-down configuration (all but analog pins) */
setting = GPIO_PUPDR_NONE;
if (pinmode != GPIO_MODER_ANALOG)
{
switch (cfgset & GPIO_PUPD_MASK)
{
default:
case GPIO_FLOAT: /* No pull-up, pull-down */
break;
case GPIO_PULLUP: /* Pull-up */
setting = GPIO_PUPDR_PULLUP;
break;
case GPIO_PULLDOWN: /* Pull-down */
setting = GPIO_PUPDR_PULLDOWN;
break;
}
}
regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET);
regval &= ~GPIO_PUPDR_MASK(pin);
regval |= (setting << GPIO_PUPDR_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
/* Set the alternate function (Only alternate function pins) */
if (pinmode == GPIO_MODER_ALT)
{
setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
}
else
{
setting = 0;
}
if (pin < 8)
{
regoffset = STM32_GPIO_AFRL_OFFSET;
pos = pin;
}
else
{
regoffset = STM32_GPIO_AFRH_OFFSET;
pos = pin - 8;
}
regval = getreg32(base + regoffset);
regval &= ~GPIO_AFR_MASK(pos);
regval |= (setting << GPIO_AFR_SHIFT(pos));
putreg32(regval, base + regoffset);
/* Set speed (Only outputs and alternate function pins) */
if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT)
{
switch (cfgset & GPIO_SPEED_MASK)
{
default:
case GPIO_SPEED_2MHZ: /* 2 MHz Low speed output */
setting = GPIO_OSPEED_2MHZ;
break;
case GPIO_SPEED_25MHZ: /* 25 MHz Medium speed output */
setting = GPIO_OSPEED_25MHZ;
break;
case GPIO_SPEED_50MHZ: /* 50 MHz High speed output */
setting = GPIO_OSPEED_50MHZ;
break;
case GPIO_SPEED_100MHZ: /* 100 MHz Very High speed output */
setting = GPIO_OSPEED_100MHZ;
break;
}
}
else
{
setting = 0;
}
regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET);
regval &= ~GPIO_OSPEED_MASK(pin);
regval |= (setting << GPIO_OSPEED_SHIFT(pin));
putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET);
/* Set push-pull/open-drain (Only outputs and alternate function pins) */
regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET);
setting = GPIO_OTYPER_OD(pin);
if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) &&
(cfgset & GPIO_OPENDRAIN) != 0)
{
regval |= setting;
}
else
{
regval &= ~setting;
}
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: stm32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previously selected as alternative function
* (GPIO_ALT|GPIO_CNF_AFPP|...).
*
* This is a safety function and prevents hardware from shocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port
*
* To-Do: Auto Power Disable
****************************************************************************/
int stm32_unconfiggpio(uint32_t cfgset)
{
/* Reuse port and pin number and set it to default HiZ INPUT */
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
cfgset |= GPIO_INPUT | GPIO_FLOAT;
/* To-Do: Mark its unuse for automatic power saving options */
return stm32_configgpio(cfgset);
}
/****************************************************************************
* Name: stm32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void stm32_gpiowrite(uint32_t pinset, bool value)
{
uint32_t base;
uint32_t bit;
unsigned int port;
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32_NPORTS)
{
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number */
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Set or clear the output on the pin */
if (value)
{
bit = GPIO_BSRR_SET(pin);
}
else
{
bit = GPIO_BSRR_RESET(pin);
}
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
}
}
/****************************************************************************
* Name: stm32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool stm32_gpioread(uint32_t pinset)
{
uint32_t base;
unsigned int port;
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32_NPORTS)
{
/* Get the port base address */
base = g_gpiobase[port];
/* Get the pin number and return the input state of that pin */
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
}
return 0;
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32U5_STM32_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
#include <nuttx/irq.h>
#include <arch/stm32u5/chip.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32_gpio.h"
#else
# error "Unsupported STM32U5 chip"
#endif
/****************************************************************************
* Pre-Processor Declarations
****************************************************************************/
/* Bit-encoded input to stm32_configgpio() */
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually
* configured by software in several modes:
*
* - Input floating
* - Input pull-up
* - Input-pull-down
* - Output open-drain with pull-up or pull-down capability
* - Output push-pull with pull-up or pull-down capability
* - Alternate function push-pull with pull-up or pull-down capability
* - Alternate function open-drain with pull-up or pull-down capability
* - Analog
*
* 20-bit Encoding: 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* Inputs: MMUU .... ...X PPPP BBBB
* Outputs: MMUU .... FFOV PPPP BBBB
* Alternate Functions: MMUU AAAA FFO. PPPP BBBB
* Analog: MM.. .... .... PPPP BBBB
*/
/* Mode:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* MM.. .... .... .... ....
*/
#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */
# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */
# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */
/* Input/output pull-ups/downs (not used with analog):
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* ..UU .... .... .... ....
*/
#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */
#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT)
# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */
# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */
/* Alternate Functions:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... AAAA .... .... ....
*/
#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */
#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT)
# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT)
# define GPIO_AF0 (0 << GPIO_AF_SHIFT)
# define GPIO_AF1 (1 << GPIO_AF_SHIFT)
# define GPIO_AF2 (2 << GPIO_AF_SHIFT)
# define GPIO_AF3 (3 << GPIO_AF_SHIFT)
# define GPIO_AF4 (4 << GPIO_AF_SHIFT)
# define GPIO_AF5 (5 << GPIO_AF_SHIFT)
# define GPIO_AF6 (6 << GPIO_AF_SHIFT)
# define GPIO_AF7 (7 << GPIO_AF_SHIFT)
# define GPIO_AF8 (8 << GPIO_AF_SHIFT)
# define GPIO_AF9 (9 << GPIO_AF_SHIFT)
# define GPIO_AF10 (10 << GPIO_AF_SHIFT)
# define GPIO_AF11 (11 << GPIO_AF_SHIFT)
# define GPIO_AF12 (12 << GPIO_AF_SHIFT)
# define GPIO_AF13 (13 << GPIO_AF_SHIFT)
# define GPIO_AF14 (14 << GPIO_AF_SHIFT)
# define GPIO_AF15 (15 << GPIO_AF_SHIFT)
/* Output/Alt function frequency selection:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... FF.. .... ....
*/
#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */
#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT)
# define GPIO_SPEED_2MHZ (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
# define GPIO_SPEED_25MHZ (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */
# define GPIO_SPEED_50MHZ (2 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */
# define GPIO_SPEED_100MHZ (3 << GPIO_SPEED_SHIFT) /* 100 MHz Very High speed output */
/* Output/Alt function type selection:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... ..O. .... ....
*/
#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */
#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */
/* If the pin is a GPIO digital output, then this identifies the initial
* output value. If the pin is an input, this bit is overloaded to provide
* the qualifier to distinguish input pull-up and -down:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... ...V .... ....
*/
#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* External interrupt selection (GPIO inputs only):
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... ...X .... ....
*/
#define GPIO_EXTI (1 << 8) /* Bit 8: Configure as EXTI interrupt */
/* This identifies the GPIO port:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... .... PPPP ....
*/
#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
/* This identifies the bit in the port:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... .... .... BBBB
*/
#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */
#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Base addresses for each GPIO block */
EXTERN const uint32_t g_gpiobase[STM32_NPORTS];
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_configgpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
* function, it must be unconfigured with stm32_unconfiggpio() with
* the same cfgset first before it can be set to non-alternative function.
*
* Returned Value:
* OK on success
* ERROR on invalid port, or when pin is locked as ALT function.
*
****************************************************************************/
int stm32_configgpio(uint32_t cfgset);
/****************************************************************************
* Name: stm32_unconfiggpio
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state (and possibly mark it's unused) and unlock it
* whether it was previously selected as alternative function
* (GPIO_ALT|GPIO_CNF_AFPP|...).
*
* This is a safety function and prevents hardware from shocks, as
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
* while it should operate in PWM mode could produce excessive on-board
* currents and trigger over-current/alarm function.
*
* Returned Value:
* OK on success
* ERROR on invalid port
*
****************************************************************************/
int stm32_unconfiggpio(uint32_t cfgset);
/****************************************************************************
* Name: stm32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void stm32_gpiowrite(uint32_t pinset, bool value);
/****************************************************************************
* Name: stm32_gpioread
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool stm32_gpioread(uint32_t pinset);
/****************************************************************************
* Name: stm32_gpiosetevent
*
* Description:
* Sets/clears GPIO based event and interrupt triggers.
*
* Input Parameters:
* pinset - GPIO pin configuration
* risingedge - Enables interrupt on rising edges
* fallingedge - Enables interrupt on falling edges
* event - Generate event when set
* func - When non-NULL, generate interrupt
* arg - Argument passed to the interrupt callback
*
* Returned Value:
* Zero (OK) is returned on success, otherwise a negated errno value is
* returned to indicate the nature of the failure.
*
****************************************************************************/
int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
bool event, xcpt_t func, void *arg);
/****************************************************************************
* Function: stm32_dumpgpio
*
* Description:
* Dump all GPIO registers associated with the provided base address
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
int stm32_dumpgpio(uint32_t pinset, const char *msg);
#else
# define stm32_dumpgpio(p,m)
#endif
/****************************************************************************
* Function: stm32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32_start().
*
****************************************************************************/
void stm32_gpioinit(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_GPIO_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include <nuttx/board.h>
#include <nuttx/power/pm.h>
#include "chip.h"
#include "stm32_rcc.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
#define up_idlepm()
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power. */
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG))
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_irq.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <arch/irq.h>
#include <arch/armv8-m/nvicpri.h>
#include "nvic.h"
#include "ram_vectors.h"
#include "arm_arch.h"
#include "arm_internal.h"
#include "stm32.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Get a 32-bit version of the default priority */
#define DEFPRIORITY32 \
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
NVIC_SYSH_PRIORITY_DEFAULT)
/* Given the address of a NVIC ENABLE register, this is the offset to
* the corresponding CLEAR ENABLE register.
*/
#define NVIC_ENA_OFFSET (0)
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_current_regs[] holds a references to the current interrupt level
* register storage structure. If is non-NULL only during interrupt
* processing. Access to g_current_regs[] must be through the macro
* CURRENT_REGS for portability.
*/
volatile uint32_t *g_current_regs[1];
/* This is the address of the exception vector table (determined by the
* linker script).
*/
extern uint32_t _vectors[];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_dumpnvic
*
* Description:
* Dump some interesting NVIC registers
*
****************************************************************************/
#if defined(CONFIG_DEBUG_IRQ_INFO)
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
leave_critical_section(flags);
}
#else
# define stm32_dumpnvic(msg, irq)
#endif
/****************************************************************************
* Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv,
* stm32_dbgmonitor, stm32_pendsv, stm32_reserved
*
* Description:
* Handlers for various exceptions. None are handled and all are fatal
* error conditions. The only advantage these provide over the default
* unexpected interrupt handler is that they provide a diagnostic output.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
static int stm32_nmi(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
}
static int stm32_busfault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
static int stm32_usagefault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
}
static int stm32_pendsv(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
}
static int stm32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
}
static int stm32_reserved(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;
}
#endif
/****************************************************************************
* Name: stm32_prioritize_syscall
*
* Description:
* Set the priority of an exception. This function may be needed
* internally even if support for prioritized interrupts is not enabled.
*
****************************************************************************/
#ifdef CONFIG_ARMV8M_USEBASEPRI
static inline void stm32_prioritize_syscall(int priority)
{
uint32_t regval;
/* SVCALL is system handler 11 */
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
}
#endif
/****************************************************************************
* Name: stm32_irqinfo
*
* Description:
* Given an IRQ number, provide the register and bit setting to enable or
* disable the irq.
*
****************************************************************************/
static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
int n;
DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= STM32_IRQ_FIRST)
{
n = irq - STM32_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
*bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
else
{
*regaddr = NVIC_SYSHCON;
if (irq == STM32_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == STM32_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == STM32_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == STM32_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
}
else
{
return ERROR; /* Invalid or unsupported exception */
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_irqinitialize
****************************************************************************/
void up_irqinitialize(void)
{
uint32_t regaddr;
int num_priority_registers;
int i;
/* Disable all interrupts */
for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
/* The standard location for the vector table is at the beginning of FLASH
* at address 0x0800:0000. If we are using the STMicro DFU bootloader,
* then the vector table will be offset to a different location in FLASH
* and we will need to set the NVIC vector location to this alternative
* location.
*/
putreg32((uint32_t)_vectors, NVIC_VECTAB);
#ifdef CONFIG_ARCH_RAMVECTORS
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
up_ramvec_initialize();
#endif
/* Set all interrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
/* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
* lines that the NVIC supports:
*
* 0 -> 32 interrupt lines, 8 priority registers
* 1 -> 64 " " " ", 16 priority registers
* 2 -> 96 " " " ", 32 priority registers
* ...
*/
num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
/* Now set all of the interrupt lines to the default priority */
regaddr = NVIC_IRQ0_3_PRIORITY;
while (num_priority_registers--)
{
putreg32(DEFPRIORITY32, regaddr);
regaddr += 4;
}
/* currents_regs is non-NULL only while processing an interrupt */
CURRENT_REGS = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL);
irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV8M_USEBASEPRI
stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_ARM_MPU
irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
up_enable_irq(STM32_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG_FEATURES
irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL);
#ifndef CONFIG_ARM_MPU
irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
#endif
irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault, NULL);
irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault, NULL);
irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL);
irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor, NULL);
irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL);
#endif
stm32_dumpnvic("initial", NR_IRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
up_irq_enable();
#endif
}
/****************************************************************************
* Name: up_disable_irq
*
* Description:
* Disable the IRQ specified by 'irq'
*
****************************************************************************/
void up_disable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (stm32_irqinfo(irq, &regaddr, &bit, NVIC_CLRENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to disable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Clear Enable register. For other exceptions, we need to
* clear the bit in the System Handler Control and State Register.
*/
if (irq >= STM32_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval &= ~bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: up_enable_irq
*
* Description:
* Enable the IRQ specified by 'irq'
*
****************************************************************************/
void up_enable_irq(int irq)
{
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (stm32_irqinfo(irq, &regaddr, &bit, NVIC_ENA_OFFSET) == 0)
{
/* Modify the appropriate bit in the register to enable the interrupt.
* For normal interrupts, we need to set the bit in the associated
* Interrupt Set Enable register. For other exceptions, we need to
* set the bit in the System Handler Control and State Register.
*/
if (irq >= STM32_IRQ_FIRST)
{
putreg32(bit, regaddr);
}
else
{
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
}
}
/****************************************************************************
* Name: arm_ack_irq
*
* Description:
* Acknowledge the IRQ
*
****************************************************************************/
void arm_ack_irq(int irq)
{
}
/****************************************************************************
* Name: up_prioritize_irq
*
* Description:
* Set the priority of an IRQ.
*
* Since this API is not supported on all architectures, it should be
* avoided in common implementations where possible.
*
****************************************************************************/
#ifdef CONFIG_ARCH_IRQPRIO
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < STM32_IRQ_FIRST)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= STM32_IRQ_FIRST;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
stm32_dumpnvic("prioritize", irq);
return OK;
}
#endif

400
arch/arm/src/stm32u5/stm32_lowputc.c Normal file
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@ -0,0 +1,400 @@
/****************************************************************************
* arch/arm/src/stm32u5/stm32_lowputc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "arm_arch.h"
#include "chip.h"
#include "stm32.h"
#include "stm32_rcc.h"
#include "stm32_gpio.h"
#include "stm32_uart.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Select USART parameters for the selected console */
#ifdef HAVE_CONSOLE
# if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_LPUART1_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2
# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN
# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD
# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS
# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY
# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP
# define STM32_CONSOLE_TX GPIO_LPUART1_TX
# define STM32_CONSOLE_RX GPIO_LPUART1_RX
# ifdef CONFIG_LPUART1_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR
# if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART1_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART1_BASE
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR
# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP
# define STM32_CONSOLE_TX GPIO_USART1_TX
# define STM32_CONSOLE_RX GPIO_USART1_RX
# ifdef CONFIG_USART1_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART2_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP
# define STM32_CONSOLE_TX GPIO_USART2_TX
# define STM32_CONSOLE_RX GPIO_USART2_RX
# ifdef CONFIG_USART2_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
# if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART3_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP
# define STM32_CONSOLE_TX GPIO_USART3_TX
# define STM32_CONSOLE_RX GPIO_USART3_RX
# ifdef CONFIG_USART3_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
# if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART4_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART4_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN
# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART4_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP
# define STM32_CONSOLE_TX GPIO_UART4_TX
# define STM32_CONSOLE_RX GPIO_UART4_RX
# ifdef CONFIG_UART4_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
# if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# elif defined(CONFIG_UART5_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_UART5_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1
# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN
# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD
# define STM32_CONSOLE_BITS CONFIG_UART5_BITS
# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY
# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP
# define STM32_CONSOLE_TX GPIO_UART5_TX
# define STM32_CONSOLE_RX GPIO_UART5_RX
# ifdef CONFIG_UART5_RS485
# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
# if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
# define STM32_CONSOLE_RS485_DIR_POLARITY false
# else
# define STM32_CONSOLE_RS485_DIR_POLARITY true
# endif
# endif
# endif
/* CR1 settings */
# if STM32_CONSOLE_BITS == 9
# define USART_CR1_M0_VALUE USART_CR1_M0
# define USART_CR1_M1_VALUE 0
# elif STM32_CONSOLE_BITS == 7
# define USART_CR1_M0_VALUE 0
# define USART_CR1_M1_VALUE USART_CR1_M1
# else /* 8 bits */
# define USART_CR1_M0_VALUE 0
# define USART_CR1_M1_VALUE 0
# endif
# if STM32_CONSOLE_PARITY == 1 /* odd parity */
# define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS)
# elif STM32_CONSOLE_PARITY == 2 /* even parity */
# define USART_CR1_PARITY_VALUE USART_CR1_PCE
# else /* no parity */
# define USART_CR1_PARITY_VALUE 0
# endif
# define USART_CR1_CLRBITS \
(USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \
USART_CR1_MME | USART_CR1_OVER8 | USART_CR1_DEDT_MASK | \
USART_CR1_DEAT_MASK | USART_CR1_ALLINTS)
# define USART_CR1_SETBITS (USART_CR1_M0_VALUE|USART_CR1_M1_VALUE|USART_CR1_PARITY_VALUE)
/* CR2 settings */
# if STM32_CONSOLE_2STOP != 0
# define USART_CR2_STOP2_VALUE USART_CR2_STOP2
# else
# define USART_CR2_STOP2_VALUE 0
# endif
# define USART_CR2_CLRBITS \
(USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
USART_CR2_LINEN | USART_CR2_SWAP | USART_CR2_RXINV | USART_CR2_TXINV | \
USART_CR2_DATAINV | USART_CR2_MSBFIRST | USART_CR2_ABREN | \
USART_CR2_ABRMOD_MASK | USART_CR2_RTOEN | USART_CR2_ADD_MASK)
# define USART_CR2_SETBITS USART_CR2_STOP2_VALUE
/* CR3 settings */
# define USART_CR3_CLRBITS \
(USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
USART_CR3_NACK | USART_CR3_SCEN | USART_CR3_DMAR | USART_CR3_DMAT | \
USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_CTSIE | USART_CR3_ONEBIT | \
USART_CR3_OVRDIS | USART_CR3_DDRE | USART_CR3_DEM | USART_CR3_DEP | \
USART_CR3_SCARCNT2_MASK | USART_CR3_WUS_MASK | USART_CR3_WUFIE)
# define USART_CR3_SETBITS 0
# undef USE_OVER8
/* Calculate USART BAUD rate divider */
/* Baud rate for standard USART (SPI mode included):
*
* In case of oversampling by 16, the equation is:
* baud = fCK / UARTDIV
* UARTDIV = fCK / baud
*
* In case of oversampling by 8, the equation is:
*
* baud = 2 * fCK / UARTDIV
* UARTDIV = 2 * fCK / baud
*/
# define STM32_USARTDIV8 \
(((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
# define STM32_USARTDIV16 \
((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD)
/* Use oversamply by 8 only if the divisor is small. But what is small? */
# if STM32_USARTDIV8 > 2000
# define STM32_BRR_VALUE STM32_USARTDIV16
# else
# define USE_OVER8 1
# define STM32_BRR_VALUE \
((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1))
# endif
#endif /* HAVE_CONSOLE */
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Variables
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: arm_lowputc
*
* Description:
* Output one byte on the serial console
*
****************************************************************************/
void arm_lowputc(char ch)
{
#ifdef HAVE_CONSOLE
/* Wait until the TX data register is empty */
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
USART_ISR_TXE) == 0);
#ifdef STM32_CONSOLE_RS485_DIR
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Then send the character */
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
#ifdef STM32_CONSOLE_RS485_DIR
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) &
USART_ISR_TC) == 0);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
!STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
#endif /* HAVE_CONSOLE */
}
/****************************************************************************
* Name: stm32_lowsetup
*
* Description:
* This performs basic initialization of the USART used for the serial
* console. Its purpose is to get the console output available as soon
* as possible.
*
****************************************************************************/
void stm32_lowsetup(void)
{
#if defined(HAVE_UART)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
#endif
#if defined(HAVE_CONSOLE)
/* Enable USART APB1/2 clock */
modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN);
#endif
/* Enable the console USART and configure GPIO pins needed for rx/tx.
*
* NOTE: Clocking for selected U[S]ARTs was already provided in
* stm32_rcc.c
*/
#ifdef STM32_CONSOLE_TX
stm32_configgpio(STM32_CONSOLE_TX);
#endif
#ifdef STM32_CONSOLE_RX
stm32_configgpio(STM32_CONSOLE_RX);
#endif
#ifdef STM32_CONSOLE_RS485_DIR
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR,
!STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
/* Enable and configure the selected console device */
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Configure CR2 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
cr &= ~USART_CR2_CLRBITS;
cr |= USART_CR2_SETBITS;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET);
/* Configure CR1 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
cr &= ~USART_CR1_CLRBITS;
cr |= USART_CR1_SETBITS;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
/* Configure CR3 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
cr &= ~USART_CR3_CLRBITS;
cr |= USART_CR3_SETBITS;
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET);
/* Configure the USART Baud Rate */
putreg32(STM32_BRR_VALUE,
STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET);
/* Select oversampling by 8 or by 16 */
cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#ifdef USE_OVER8
cr |= USART_CR1_OVER8;
#else
cr &= ~USART_CR1_OVER8;
#endif
/* Enable Rx, Tx, and the USART */
cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE);
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
#endif /* HAVE_UART */
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_LOWPUTC_H
#define __ARCH_ARM_SRC_STM32U5_STM32_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization of serial console.
*
****************************************************************************/
void stm32_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_LOWPUTC_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_lse.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
#include "stm32_pwr.h"
#include "stm32_rcc.h"
#include "stm32_waste.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC)
#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY
# if CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
# error "Invalid LSE drive capability setting"
#endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
static const uint32_t drives[4] =
{
RCC_BDCR_LSEDRV_LOW,
RCC_BDCR_LSEDRV_MEDLO,
RCC_BDCR_LSEDRV_MEDHI,
RCC_BDCR_LSEDRV_HIGH
};
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) oscillator and the LSE system clock.
*
****************************************************************************/
void stm32_rcc_enablelse(void)
{
bool writable;
uint32_t regval;
volatile int32_t timeout;
#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
volatile int32_t drive = 0;
#endif
/* Check if both the External Low-Speed (LSE) oscillator and the LSE system
* clock are already running.
*/
regval = getreg32(STM32_RCC_BDCR);
if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY |
RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) !=
(RCC_BDCR_LSEON | RCC_BDCR_LSERDY |
RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN))
{
/* The LSE is in the RTC domain and write access is denied to this
* domain after reset, you have to enable write access using DBP bit in
* the PWR CR register before to configuring the LSE.
*/
writable = stm32_pwr_enablebkp(true);
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON
* bit the RCC BDCR register.
*/
regval |= RCC_BDCR_LSEON;
#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY
/* Set start-up drive capability for LSE oscillator. LSE must be OFF
* to change drive strength.
*/
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
regval |= CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY <<
RCC_BDCR_LSEDRV_SHIFT;
putreg32(regval, STM32_RCC_BDCR);
regval |= RCC_BDCR_LSEON;
#endif
#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
do
{
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
regval |= drives[drive++];
putreg32(regval, STM32_RCC_BDCR);
regval |= RCC_BDCR_LSEON;
#endif
putreg32(regval, STM32_RCC_BDCR);
/* Wait for the LSE clock to be ready (or until a timeout elapsed)
*/
for (timeout = LSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the LSERDY flag is the set in the BDCR */
regval = getreg32(STM32_RCC_BDCR);
if (regval & RCC_BDCR_LSERDY)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
if (timeout != 0)
{
break;
}
}
while (drive < sizeof(drives) / sizeof(drives[0]));
#endif
if (timeout != 0)
{
/* Enable LSE system clock. The LSE system clock seems to provide
* a means to gate the LSE clock distribution to peripherals. It
* must be enabled for MSI PLL mode (syncing the MSI to the LSE).
*/
regval |= RCC_BDCR_LSESYSEN;
putreg32(regval, STM32_RCC_BDCR);
/* Wait for the LSE system clock to be ready */
while (!((regval = getreg32(STM32_RCC_BDCR)) &
RCC_BDCR_LSESYSRDY))
{
stm32_waste();
}
}
#ifdef CONFIG_STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
/* Set running drive capability for LSE oscillator. */
regval &= ~RCC_BDCR_LSEDRV_MASK;
regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT;
putreg32(regval, STM32_RCC_BDCR);
#endif
/* Disable backup domain access if it was disabled on entry */
(void)stm32_pwr_enablebkp(writable);
}
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_lsi.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
#include "stm32_rcc.h"
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32_rcc_enablelsi(void)
{
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
* bit the RCC BDCR register.
*/
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_LSION);
/* Wait for the internal LSI oscillator to be stable. */
while ((getreg32(STM32_RCC_BDCR) & RCC_BDCR_LSIRDY) == 0);
}
/****************************************************************************
* Name: stm32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32_rcc_disablelsi(void)
{
/* Disable the Internal Low-Speed (LSI) RC Oscillator by resetting the
* LSION bit the RCC BDCR register.
*/
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_LSION, 0);
/* LSIRDY should go low after 3 LSI clock cycles */
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_mpuinit.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "mpu.h"
#include "stm32_mpuinit.h"
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ARM_MPU)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef MAX
# define MAX(a,b) a > b ? a : b
#endif
#ifndef MIN
# define MIN(a,b) a < b ? a : b
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only restricted SAM3U
* resources.
*
****************************************************************************/
void stm32_mpuinitialize(void)
{
uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart);
uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend);
DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart &&
dataend >= datastart);
/* Show MPU information */
mpu_showtype();
/* Configure user flash and SRAM space */
mpu_user_flash(USERSPACE->us_textstart,
USERSPACE->us_textend - USERSPACE->us_textstart);
mpu_user_intsram(datastart, dataend - datastart);
/* Then enable the MPU */
mpu_control(true, false, true);
}
/****************************************************************************
* Name: stm32_mpu_uheap
*
* Description:
* Map the user-heap region.
*
* This logic may need an extension to handle external SDRAM).
*
****************************************************************************/
void stm32_mpu_uheap(uintptr_t start, size_t size)
{
mpu_user_intsram(start, size);
}
#endif /* CONFIG_BUILD_PROTECTED && CONFIG_ARM_MPU */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_mpuinit.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_MPUINIT_H
#define __ARCH_ARM_SRC_STM32U5_STM32_MPUINIT_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_mpuinitialize
*
* Description:
* Configure the MPU to permit user-space access to only unrestricted MCU
* resources.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void stm32_mpuinitialize(void);
#else
# define stm32_mpuinitialize()
#endif
/****************************************************************************
* Name: stm32_mpu_uheap
*
* Description:
* Map the user heap region.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void stm32_mpu_uheap(uintptr_t start, size_t size);
#else
# define stm32_mpu_uheap(start,size)
#endif
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_MPUINIT_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_pwr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <assert.h>
#include <errno.h>
#include <stdbool.h>
#include <stdint.h>
#include "arm_arch.h"
#include "stm32_pwr.h"
#include "stm32_rcc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define PWR_TIMEOUT (10 * CONFIG_BOARD_LOOPSPERMSEC)
/****************************************************************************
* Private Functions
****************************************************************************/
static inline uint16_t stm32_pwr_getreg(uint8_t offset)
{
return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset);
}
static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value)
{
putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset);
}
static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits,
uint16_t setbits)
{
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits,
(uint32_t)setbits);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: enableclk
*
* Description:
* Enable/disable the clock to the power control peripheral. Enabling must
* be done after the APB1 clock is validly configured, and prior to using
* any functionality controlled by the PWR block (i.e. much of anything
* else provided by this module).
*
* Input Parameters:
* enable - True: enable the clock to the Power control (PWR) block.
*
* Returned Value:
* True: the PWR block was previously enabled.
*
****************************************************************************/
bool stm32_pwr_enableclk(bool enable)
{
uint32_t regval;
bool wasenabled;
regval = getreg32(STM32_RCC_AHB3ENR);
wasenabled = ((regval & RCC_AHB3ENR_PWREN) != 0);
/* Power interface clock enable. */
if (wasenabled && !enable)
{
/* Disable power interface clock */
regval &= ~RCC_AHB3ENR_PWREN;
putreg32(regval, STM32_RCC_AHB3ENR);
}
else if (!wasenabled && enable)
{
/* Enable power interface clock */
regval |= RCC_AHB3ENR_PWREN;
putreg32(regval, STM32_RCC_AHB3ENR);
}
return wasenabled;
}
/****************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
* Enables access to the backup domain (RTC registers, RTC backup data
* registers and backup SRAM).
*
* Input Parameters:
* writable True: enable ability to write to backup domain registers
*
* Returned Value:
* True: The backup domain was previously writable.
*
****************************************************************************/
bool stm32_pwr_enablebkp(bool writable)
{
uint16_t regval;
bool waswritable;
/* Get the current state of the PWR disable Backup domain register */
regval = stm32_pwr_getreg(STM32_PWR_DBPR_OFFSET);
waswritable = ((regval & PWR_DBPR_DBP) != 0);
/* Enable or disable the ability to write */
if (waswritable && !writable)
{
/* Disable backup domain access */
regval &= ~PWR_DBPR_DBP;
stm32_pwr_putreg(STM32_PWR_DBPR_OFFSET, regval);
}
else if (!waswritable && writable)
{
/* Enable backup domain access */
regval |= PWR_DBPR_DBP;
stm32_pwr_putreg(STM32_PWR_DBPR_OFFSET, regval);
/* Enable does not happen right away */
up_udelay(4);
}
return waswritable;
}
/****************************************************************************
* Name stm32_pwr_adjustvcore
*
* Description:
* Adjusts the voltage used for digital peripherals (V_CORE) before
* raising or after decreasing the system clock frequency. Compare
* [RM0456], section 10.5.4 Dynamic voltage scaling management.
*
* Input Parameters:
* sysclock - The frequency in Hertz the system clock will or has been set
* to.
*
****************************************************************************/
void stm32_pwr_adjustvcore(unsigned sysclock)
{
volatile int timeout;
uint32_t vos_range;
/* Select the applicable V_CORE voltage range depending on the new system
* clock frequency.
*/
DEBUGASSERT(sysclock <= 160000000);
if (sysclock > 110000000)
{
vos_range = PWR_VOSR_VOS_RANGE1 | PWR_VOSR_BOOSTEN;
}
else if (sysclock > 55000000)
{
vos_range = PWR_VOSR_VOS_RANGE2 | PWR_VOSR_BOOSTEN;
}
else if (sysclock > 25000000)
{
vos_range = PWR_VOSR_VOS_RANGE3;
}
else
{
vos_range = PWR_VOSR_VOS_RANGE4;
}
modreg32(vos_range, PWR_VOSR_VOS_MASK | PWR_VOSR_BOOSTEN, STM32_PWR_VOSR);
/* Wait until the new V_CORE voltage range has been applied. */
for (timeout = PWR_TIMEOUT; timeout; timeout--)
{
if (getreg32(STM32_PWR_VOSR) & PWR_VOSR_VOSRDY)
{
break;
}
}
DEBUGASSERT(timeout > 0);
/* Wait until the voltage level for the currently used VOS is ready. */
for (timeout = PWR_TIMEOUT; timeout; timeout--)
{
if (getreg32(STM32_PWR_SVMSR) & PWR_SVMSR_ACTVOSRDY)
{
break;
}
}
DEBUGASSERT(timeout > 0);
#if 0
/* Wait until the embedded power distribution (EPOD) booster has been
* enabled, if applicable.
*/
DEBUGASSERT(timeout > 0);
if (vos_range & PWR_VOSR_BOOSTEN)
{
for (timeout = PWR_TIMEOUT; timeout; timeout--)
{
if (getreg32(STM32_PWR_VOSR) & PWR_VOSR_BOOSTRDY)
{
break;
}
}
}
#endif
DEBUGASSERT(timeout > 0);
}
/****************************************************************************
* Name stm32_pwr_enable_smps
*
* Description:
* Select between the Low-Drop Out (LDO) or Switched Mode Power Suppy
* (SMPS) regulator. Compare [RM0456], section 10.5.1 SMPS and LDO
* embedded regulators.
*
* Input Parameters:
* enable - If true, the SMPS regulator will be enabled, otherwise the LDO,
*
****************************************************************************/
void stm32_pwr_enablesmps(bool enable)
{
volatile int timeout;
uint32_t regsel = enable ? PWR_CR3_REGSEL_SMPS : PWR_CR3_REGSEL_LDO;
/* Select the respective regulator. */
modreg32(regsel, PWR_CR3_REGSEL, STM32_PWR_CR3);
/* Wait until the respective regulator has been activated. */
for (timeout = PWR_TIMEOUT; timeout; timeout--)
{
if (enable)
{
if ((getreg32(STM32_PWR_SVMSR) & PWR_SVMSR_REGS) ==
PWR_SVMSR_REGS_SMPS)
{
break;
}
}
else
{
if ((getreg32(STM32_PWR_SVMSR) & PWR_SVMSR_REGS) ==
PWR_SVMSR_REGS_LDO)
{
break;
}
}
}
DEBUGASSERT(timeout > 0);
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_pwr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_PWR_H
#define __ARCH_ARM_SRC_STM32U5_STM32_PWR_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/stm32_pwr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: enableclk
*
* Description:
* Enable/disable the clock to the power control peripheral. Enabling must
* be done after the APB1 clock is validly configured, and prior to using
* any functionality controlled by the PWR block (i.e. much of anything
* else provided by this module).
*
* Input Parameters:
* enable - True: enable the clock to the Power control (PWR) block.
*
* Returned Value:
* True: the PWR block was previously enabled.
*
****************************************************************************/
bool stm32_pwr_enableclk(bool enable);
/****************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
* Enables write access to the backup domain (RTC registers, RTC backup
* data registers and backup SRAM). Compare [RM0456], section 10.4.7
* Battery Backup domain, Backup domain access.
*
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
* True: The backup domain was previously writable.
*
****************************************************************************/
bool stm32_pwr_enablebkp(bool writable);
/****************************************************************************
* Name stm32_pwr_adjustvcore
*
* Description:
* Adjusts the voltage used for digital peripherals (V_CORE) before
* raising or after decreasing the system clock frequency. Compare
* [RM0456], section 10.5.4 Dynamic voltage scaling management.
*
* Input Parameters:
* sysclock - The frequency in Hertz the system clock will be raised to.
*
****************************************************************************/
void stm32_pwr_adjustvcore(unsigned sysclock);
/****************************************************************************
* Name stm32_pwr_enable_smps
*
* Description:
* Select between the Low-Drop Out (LDO) or Switched Mode Power Suppy
* (SMPS) regulator. Compare [RM0456], section 10.5.1 SMPS and LDO
* embedded regulators.
*
* Input Parameters:
* enable - If true, the SMPS regulator will be enabled, otherwise the LDO,
*
****************************************************************************/
void stm32_pwr_enablesmps(bool enable);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_PWR_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_rcc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
#include <debug.h>
#include <arch/board/board.h>
#include "arm_internal.h"
#include "arm_arch.h"
#include "chip.h"
#include "stm32_rcc.h"
#include "stm32_flash.h"
#include "stm32.h"
#include "stm32_waste.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
* hosed anyway.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name
*
* Description
* The RTC needs to reset the Backup Domain to change RTCSEL and resetting
* the Backup Domain renders to disabling the LSE as consequence. In
* order to avoid resetting the Backup Domain when we already configured
* LSE we will reset the Backup Domain early (here).
*
* Input Parameters
* None
*
* Returned Value
* None
*
****************************************************************************/
#if defined(CONFIG_STM32U5_PWR) && defined(CONFIG_STM32U5_RTC)
static inline void rcc_resetbkp(void)
{
bool init_stat;
/* Check if the RTC is already configured */
init_stat = stm32_rtc_is_initialized();
if (!init_stat)
{
uint32_t bkregs[STM32U5_RTC_BKCOUNT];
int i;
/* Backup backup-registers before RTC reset. */
for (i = 0; i < STM32U5_RTC_BKCOUNT; i++)
{
bkregs[i] = getreg32(STM32U5_RTC_BKR(i));
}
/* Enable write access to the backup domain (RTC registers, RTC
* backup data registers and backup SRAM).
*/
(void)stm32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must
* reset the backup domain (having backed up the RTC_MAGIC token)
*/
modifyreg32(STM32U5_RCC_BDCR, 0, RCC_BDCR_BDRST);
modifyreg32(STM32U5_RCC_BDCR, RCC_BDCR_BDRST, 0);
/* Restore backup-registers, except RTC related. */
for (i = 0; i < STM32U5_RTC_BKCOUNT; i++)
{
if (RTC_MAGIC_REG == STM32U5_RTC_BKR(i))
{
continue;
}
putreg32(bkregs[i], STM32U5_RTC_BKR(i));
}
(void)stm32_pwr_enablebkp(false);
}
}
#else
# define rcc_resetbkp()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name
*
* Description
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all peripherals enabled in the NuttX
* configuration file.
*
* If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
* Input Parameters
* None
*
* Returned Value
* None
*
****************************************************************************/
void stm32_clockconfig(void)
{
#if 0
/* Make sure that we are starting in the reset state */
rcc_reset();
/* Reset backup domain if appropriate */
rcc_resetbkp();
#endif
#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
stm32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions in
* board.h
*/
stm32_stdclockconfig();
#endif
/* Enable peripheral clocking */
stm32_rcc_enableperipherals();
}
/****************************************************************************
* Name
*
* Description
* Re-enable the clock and restore the clock settings based on settings in
* board.h. This function is only available to support low-power modes of
* operation
* re-enable/re-start the PLL
*
* This function performs a subset of the operations performed by
* stm32_clockconfig()
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
* Input Parameters
* None
*
* Returned Value
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void stm32_clockenable(void)
{
#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
stm32_board_clockconfig();
#else
/* Invoke standard, fixed clock configuration based on definitions in
* board.h
*/
stm32_stdclockconfig();
#endif
}
#endif

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_rcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_RCC_H
#define __ARCH_ARM_SRC_STM32U5_STM32_RCC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "arm_arch.h"
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32u585xx_rcc.h"
#else
# error "Unsupported STM32U5 chip"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#elseO
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* This symbol references the Cortex-M33 vector table (as positioned by the
* linker script, ld.script or ld.script.dfu. The standard location for the
* vector table is at the beginning of FLASH at address 0x0800:0000. If we
* are using the STMicro DFU bootloader, then the vector table will be offset
* to a different location in FLASH and we will need to set the NVIC vector
* location to this alternative location.
*/
extern uint32_t _vectors[]; /* See stm32_vectors.S */
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_mcoconfig
*
* Description:
* Selects the clock source to output on MCO pin (PA8) for stm32u585xx.
* PA8 should be configured in alternate function mode.
*
* Input Parameters:
* source - One of the RCC_CFGR_MCO definitions from chip/stm32u585xx_rcc.h
*
* Returned Value:
* None
*
****************************************************************************/
static inline void stm32_mcoconfig(uint32_t source)
{
uint32_t regval;
/* Set MCO source */
regval = getreg32(STM32_RCC_CFGR1);
regval &= ~(RCC_CFGR1_MCOSEL_MASK);
regval |= (source & RCC_CFGR1_MCOSEL_MASK);
putreg32(regval, STM32_RCC_CFGR1);
}
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_clockconfig
*
* Description:
* Called to establish the clock settings based on the values in board.h.
* This function (by default) will reset most everything, enable the PLL,
* and enable peripheral clocking for all periperipherals enabled in the
* NuttX configuration file.
*
* If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void stm32_clockconfig(void);
/****************************************************************************
* Name: stm32_board_clockconfig
*
* Description:
* Any STM32U5 board may replace the "standard" board clock configuration
* logic with its own, custom clock configuration logic.
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG
void stm32_board_clockconfig(void);
#endif
/****************************************************************************
* Name: stm32_stdclockconfig
*
* Description:
* The standard logic to configure the clocks based on settings in board.h.
* Applicable if no custom clock config is provided. This function is
* chip type specific and implemented in corresponding modules such as e.g.
* stm3262xx_rcc.c
*
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void);
#endif
/****************************************************************************
* Name: stm32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
* board.h. This function is only available to support low-power modes of
* operation: When re-awakening from deep-sleep modes, it is necessary to
* re-enable/re-start the PLL
*
* This function performs a subset of the operations performed by
* stm32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then
* clocking will be enabled by an externally provided, board-specific
* function called stm32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void stm32_clockenable(void);
#endif
/****************************************************************************
* Name: stm32_rcc_enablelse
*
* Description:
* Enable the External Low-Speed (LSE) Oscillator.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void stm32_rcc_enablelse(void);
/****************************************************************************
* Name: stm32_rcc_enablelsi
*
* Description:
* Enable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32_rcc_enablelsi(void);
/****************************************************************************
* Name: stm32_rcc_disablelsi
*
* Description:
* Disable the Internal Low-Speed (LSI) RC Oscillator.
*
****************************************************************************/
void stm32_rcc_disablelsi(void);
/****************************************************************************
* Name: stm32_rcc_enableperipherals
*
* Description:
* Enable all the chip peripherals according to configuration. This is
* chip type specific and thus implemented in corresponding modules such as
* e.g. stm3262xx_rcc.c
*
****************************************************************************/
void stm32_rcc_enableperipherals(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_RCC_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_SPI_H
#define __ARCH_ARM_SRC_STM32U5_STM32_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/stm32_spi.h"
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
struct spi_dev_s; /* Forward reference */
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_spibus_initialize
*
* Description:
* Initialize the selected SPI bus
*
* Input Parameters:
* bus number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
FAR struct spi_dev_s *stm32_spibus_initialize(int bus);
/****************************************************************************
* Name: stm32_spi_slave_initialize
*
* Description:
* Initialize the selected SPI bus for slave operation
*
* Input Parameters:
* bus number
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
FAR struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus);
/****************************************************************************
* Name: stm32_spi1/2/...select and stm32_spi1/2/...status
*
* Description:
* The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status,
* and stm32_spi1/2/...cmddata must be provided by board-specific logic.
* These are implementations of the select, status, and cmddata methods of
* the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h).
* All other methods (including stm32_spibus_initialize()) are provided by
* common STM32 logic. To use this common SPI logic on your board:
*
* 1. Provide logic in stm32_boardinitialize() to configure SPI chip select
* pins.
* 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status()
* functions in your board-specific logic. These functions will perform
* chip selection and status operations using GPIOs in the way your
* board is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file,
* then provide stm32_spi1/2/...cmddata() functions in your board-
* specific logic. These functions will perform cmd/data selection
* operations using GPIOs in the way your board is configured.
* 4. Add a calls to stm32_spibus_initialize() in your low level
* application initialization logic
* 5. The handle returned by stm32_spibus_initialize() may then be used to
* bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_STM32U5_SPI1
void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32U5_SPI2
void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid);
int stm32_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_STM32U5_SPI3
void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid);
int stm32_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
/****************************************************************************
* Name: stm32_spi1/2/...register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based
* MMC/SD driver when an SD card is inserted or removed, then
* CONFIG_SPI_CALLBACK should be defined and the following function(s) must
* be implemented. These functions implements the registercallback method
* of the SPI interface (see include/nuttx/spi/spi.h for details)
*
* Input Parameters:
* dev - Device-specific state data
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:
* 0 on success; negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_STM32U5_SPI1
int stm32_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32U5_SPI2
int stm32_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#ifdef CONFIG_STM32U5_SPI3
int stm32_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
FAR void *arg);
#endif
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_SPI_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/init.h>
#include <arch/board/board.h>
#include "arm_arch.h"
#include "arm_internal.h"
#include "nvic.h"
#include "stm32.h"
#include "stm32_gpio.h"
#include "stm32_userspace.h"
#include "stm32_start.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Memory Map ***************************************************************/
/* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
* Mapped as boot memory address 0x0000:0000 at reset.
* 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
* 0x2000:0000 - Start of internal SRAM1 and start of .data (_sdata)
* - End of .data (_edata) and start of .bss (_sbss)
* - End of .bss (_ebss) and bottom of idle stack
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
* start of heap. NOTE that the ARM uses a decrement before
* store stack so that the correct initial value is the end of
* the stack + 4;
* 0x2002:ffff - End of internal SRAM1
* 0x2003:0000 - Start of internal SRAM2
* 0x2003:ffff - End of internal SRAM2
*/
#define SRAM2_START STM32U5_SRAM2_BASE
#define SRAM2_END (SRAM2_START + STM32U5_SRAM2_SIZE)
#define HEAP_BASE ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE)
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void stm32_fpuconfig(void);
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) arm_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
#ifdef CONFIG_ARMV8M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Name: stm32_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit while
* either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV8M_LAZYFPU
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void stm32_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define stm32_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: _start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __start(void)
{
const uint32_t *src;
uint32_t *dest;
#ifdef CONFIG_ARMV8M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile
("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
#ifdef CONFIG_STM32U5_SRAM2_INIT
/* The SRAM2 region is parity checked, but upon power up, it will be in
* a random state and probably invalid with respect to parity, potentially
* generating faults if accessed. If elected, we will write zeros to the
* memory, forcing the parity to be set to a valid state.
* NOTE: this is optional because this may be inappropriate, especially
* if the memory is being used for it's battery backed purpose. In that
* case, the first-time initialization needs to be performed by the board
* under application-specific circumstances. On the other hand, if we're
* using this memory for, say, additional heap space, then this is handy.
*/
for (dest = (uint32_t *)SRAM2_START; dest < (uint32_t *)SRAM2_END; )
{
*dest++ = 0;
}
#endif
/* Configure the UART so that we can get debug output as soon as possible */
stm32_clockconfig();
stm32_fpuconfig();
stm32_lowsetup();
stm32_gpioinit();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = &_sbss; dest < &_ebss; )
{
*dest++ = 0;
}
showprogress('B');
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
{
*dest++ = *src++;
}
showprogress('C');
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arm_earlyserialinit();
#endif
showprogress('D');
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
stm32_userspace();
showprogress('E');
#endif
/* Initialize onboard resources */
stm32_board_initialize();
showprogress('F');
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
nx_start();
/* Shoulnd't get here */
for (; ; );
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_START_H
#define __ARCH_ARM_SRC_STM32U5_STM32_START_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_board_initialize
*
* Description:
* All STM32U5 architectures must provide the following entry point. This
* entry point is called early in the initialization -- after all memory
* has been configured and mapped but before any devices have been
* initialized.
*
****************************************************************************/
void stm32_board_initialize(void);
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_START_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_tim.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_TIM_H
#define __ARCH_ARM_SRC_STM32U5_STM32_TIM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/stm32_tim.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Helpers ******************************************************************/
#define STM32U5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
#define STM32U5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
#define STM32U5_TIM_GETCLOCK(d) ((d)->ops->getclock(d))
#define STM32U5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
#define STM32U5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d))
#define STM32U5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
#define STM32U5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
#define STM32U5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
#define STM32U5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
#define STM32U5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s))
#define STM32U5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
#define STM32U5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
#define STM32U5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
#define STM32U5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s))
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* TIM Device Structure */
struct stm32_tim_dev_s
{
struct stm32_tim_ops_s *ops;
};
/* TIM Modes of Operation */
enum stm32_tim_mode_e
{
STM32U5_TIM_MODE_UNUSED = -1,
/* One of the following */
STM32U5_TIM_MODE_MASK = 0x0310,
STM32U5_TIM_MODE_DISABLED = 0x0000,
STM32U5_TIM_MODE_UP = 0x0100,
STM32U5_TIM_MODE_DOWN = 0x0110,
STM32U5_TIM_MODE_UPDOWN = 0x0200,
STM32U5_TIM_MODE_PULSE = 0x0300,
/* One of the following */
STM32U5_TIM_MODE_CK_INT = 0x0000,
#if 0
STM32U5_TIM_MODE_CK_INT_TRIG = 0x0400,
STM32U5_TIM_MODE_CK_EXT = 0x0800,
STM32U5_TIM_MODE_CK_EXT_TRIG = 0x0c00,
#endif
/* Clock sources, OR'ed with CK_EXT */
#if 0
STM32U5_TIM_MODE_CK_CHINVALID = 0x0000,
STM32U5_TIM_MODE_CK_CH1 = 0x0001,
STM32U5_TIM_MODE_CK_CH2 = 0x0002,
STM32U5_TIM_MODE_CK_CH3 = 0x0003,
STM32U5_TIM_MODE_CK_CH4 = 0x0004
#endif
/* Todo: external trigger block */
};
/* TIM Channel Modes */
enum stm32_tim_channel_e
{
STM32U5_TIM_CH_DISABLED = 0x00,
/* Common configuration */
STM32U5_TIM_CH_POLARITY_POS = 0x00,
STM32U5_TIM_CH_POLARITY_NEG = 0x01,
/* MODES: */
STM32U5_TIM_CH_MODE_MASK = 0x06,
/* Output Compare Modes */
STM32U5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */
#if 0
STM32U5_TIM_CH_OUTCOMPARE = 0x06,
#endif
/* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */
};
/* TIM Operations */
struct stm32_tim_ops_s
{
/* Basic Timers */
int (*setmode)(FAR struct stm32_tim_dev_s *dev,
enum stm32_tim_mode_e mode);
int (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
uint32_t (*getclock)(FAR struct stm32_tim_dev_s *dev);
void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint32_t period);
uint32_t (*getperiod)(FAR struct stm32_tim_dev_s *dev);
uint32_t (*getcounter)(FAR struct stm32_tim_dev_s *dev);
/* General and Advanced Timers Adds */
int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
enum stm32_tim_channel_e mode);
int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel,
uint32_t compare);
int (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
/* Timer interrupts */
int (*setisr)(FAR struct stm32_tim_dev_s *dev,
xcpt_t handler, void *arg, int source);
void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);
void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source);
void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source);
int (*checkint)(FAR struct stm32_tim_dev_s *dev, int source);
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/* Power-up timer and get its structure */
FAR struct stm32_tim_dev_s *stm32_tim_init(int timer);
/* Power-down timer, mark it as unused */
int stm32_tim_deinit(FAR struct stm32_tim_dev_s *dev);
/****************************************************************************
* Name: stm32_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the form
* /dev/timer0
* timer - the timer number.
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
#ifdef CONFIG_TIMER
int stm32_timer_initialize(FAR const char *devpath, int timer);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_TIM_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_tim_lowerhalf.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <nuttx/timers/timer.h>
#include <arch/board/board.h>
#include "stm32_tim.h"
#if defined(CONFIG_TIMER) && \
(defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \
defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \
defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \
defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \
defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \
defined(CONFIG_STM32U5_TIM17))
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define STM32U5_TIM1_RES 16
#define STM32U5_TIM2_RES 32
#define STM32U5_TIM3_RES 16
#define STM32U5_TIM4_RES 16
#define STM32U5_TIM5_RES 32
#define STM32U5_TIM6_RES 16
#define STM32U5_TIM7_RES 16
#define STM32U5_TIM8_RES 16
#define STM32U5_TIM15_RES 16
#define STM32U5_TIM16_RES 16
#define STM32U5_TIM17_RES 16
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* timer_lowerhalf_s structure.
*/
struct stm32_lowerhalf_s
{
FAR const struct timer_ops_s *ops; /* Lower half operations */
FAR struct stm32_tim_dev_s *tim; /* stm32 timer driver */
tccb_t callback; /* Current upper half interrupt callback */
FAR void *arg; /* Argument passed to upper half callback */
bool started; /* True: Timer has been started */
const uint8_t resolution; /* Number of bits in the timer (16 or 32 bits) */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Interrupt handling *******************************************************/
static int stm32_timer_handler(int irq, void *context, void *arg);
/* "Lower half" driver methods **********************************************/
static int stm32_start(FAR struct timer_lowerhalf_s *lower);
static int stm32_stop(FAR struct timer_lowerhalf_s *lower);
static int stm32_getstatus(FAR struct timer_lowerhalf_s *lower,
FAR struct timer_status_s *status);
static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower,
uint32_t timeout);
static void stm32_setcallback(FAR struct timer_lowerhalf_s *lower,
tccb_t callback, FAR void *arg);
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct timer_ops_s g_timer_ops =
{
.start = stm32_start,
.stop = stm32_stop,
.getstatus = stm32_getstatus,
.settimeout = stm32_settimeout,
.setcallback = stm32_setcallback,
.ioctl = NULL,
};
#ifdef CONFIG_STM32U5_TIM1
static struct stm32_lowerhalf_s g_tim1_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM1_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM2
static struct stm32_lowerhalf_s g_tim2_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM2_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM3
static struct stm32_lowerhalf_s g_tim3_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM3_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM4
static struct stm32_lowerhalf_s g_tim4_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM4_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM5
static struct stm32_lowerhalf_s g_tim5_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM5_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM6
static struct stm32_lowerhalf_s g_tim6_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM6_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM7
static struct stm32_lowerhalf_s g_tim7_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM7_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM8
static struct stm32_lowerhalf_s g_tim8_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM8_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM15
static struct stm32_lowerhalf_s g_tim15_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM15_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM16
static struct stm32_lowerhalf_s g_tim16_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM16_RES,
};
#endif
#ifdef CONFIG_STM32U5_TIM17
static struct stm32_lowerhalf_s g_tim17_lowerhalf =
{
.ops = &g_timer_ops,
.resolution = STM32U5_TIM17_RES,
};
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_timer_handler
*
* Description:
* timer interrupt handler
*
* Input Parameters:
*
* Returned Value:
*
****************************************************************************/
static int stm32_timer_handler(int irq, void *context, void *arg)
{
FAR struct stm32_lowerhalf_s *lower =
(FAR struct stm32_lowerhalf_s *)arg;
uint32_t next_interval_us = 0;
STM32U5_TIM_ACKINT(lower->tim, 0);
if (lower->callback(&next_interval_us, lower->arg))
{
if (next_interval_us > 0)
{
STM32U5_TIM_SETPERIOD(lower->tim, next_interval_us);
}
}
else
{
stm32_stop((struct timer_lowerhalf_s *)lower);
}
return OK;
}
/****************************************************************************
* Name: stm32_start
*
* Description:
* Start the timer, resetting the time to the current timeout,
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_start(FAR struct timer_lowerhalf_s *lower)
{
FAR struct stm32_lowerhalf_s *priv =
(FAR struct stm32_lowerhalf_s *)lower;
if (!priv->started)
{
STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_UP);
if (priv->callback != NULL)
{
STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0);
STM32U5_TIM_ENABLEINT(priv->tim, 0);
}
priv->started = true;
return OK;
}
/* Return EBUSY to indicate that the timer was already running */
return -EBUSY;
}
/****************************************************************************
* Name: stm32_stop
*
* Description:
* Stop the timer
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_stop(FAR struct timer_lowerhalf_s *lower)
{
FAR struct stm32_lowerhalf_s *priv =
(FAR struct stm32_lowerhalf_s *)lower;
if (priv->started)
{
STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_DISABLED);
STM32U5_TIM_DISABLEINT(priv->tim, 0);
STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0);
priv->started = false;
return OK;
}
/* Return ENODEV to indicate that the timer was not running */
return -ENODEV;
}
/****************************************************************************
* Name: stm32_getstatus
*
* Description:
* get timer status
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the "lower-
* half" driver state structure.
* status - The location to return the status information.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_getstatus(FAR struct timer_lowerhalf_s *lower,
FAR struct timer_status_s *status)
{
FAR struct stm32_lowerhalf_s *priv =
(FAR struct stm32_lowerhalf_s *)lower;
uint64_t maxtimeout;
uint32_t timeout;
uint32_t clock;
uint32_t period;
uint32_t clock_factor;
DEBUGASSERT(priv);
/* Return the status bit */
status->flags = 0;
if (priv->started)
{
status->flags |= TCFLAGS_ACTIVE;
}
if (priv->callback)
{
status->flags |= TCFLAGS_HANDLER;
}
/* Get timeout */
maxtimeout = (1 << priv->resolution) - 1;
clock = STM32U5_TIM_GETCLOCK(priv->tim);
period = STM32U5_TIM_GETPERIOD(priv->tim);
if (clock == 1000000)
{
timeout = period;
}
else
{
timeout = (maxtimeout * 1000000) / clock;
}
status->timeout = timeout;
/* Get the time remaining until the timer expires (in microseconds) */
clock_factor = (clock == 1000000)? 1: (clock / 1000000);
status->timeleft = (timeout - STM32U5_TIM_GETCOUNTER(priv->tim)) *
clock_factor;
return OK;
}
/****************************************************************************
* Name: stm32_settimeout
*
* Description:
* Set a new timeout value (and reset the timer)
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* timeout - The new timeout value in microseconds.
*
* Returned Value:
* Zero on success; a negated errno value on failure.
*
****************************************************************************/
static int stm32_settimeout(FAR struct timer_lowerhalf_s *lower,
uint32_t timeout)
{
FAR struct stm32_lowerhalf_s *priv =
(FAR struct stm32_lowerhalf_s *)lower;
uint64_t maxtimeout;
if (priv->started)
{
return -EPERM;
}
maxtimeout = (1 << priv->resolution) - 1;
if (timeout > maxtimeout)
{
uint64_t freq = (maxtimeout * 1000000) / timeout;
STM32U5_TIM_SETCLOCK(priv->tim, freq);
STM32U5_TIM_SETPERIOD(priv->tim, maxtimeout);
}
else
{
STM32U5_TIM_SETCLOCK(priv->tim, 1000000);
STM32U5_TIM_SETPERIOD(priv->tim, timeout);
}
return OK;
}
/****************************************************************************
* Name: stm32_sethandler
*
* Description:
* Call this user provided timeout handler.
*
* Input Parameters:
* lower - A pointer the publicly visible representation of the
* "lower-half" driver state structure.
* callback - The new timer expiration function pointer. If this
* function pointer is NULL, then the reset-on-expiration
* behavior is restored,
* arg - Argument that will be provided in the callback
*
* Returned Value:
* The previous timer expiration function pointer or NULL is there was
* no previous function pointer.
*
****************************************************************************/
static void stm32_setcallback(FAR struct timer_lowerhalf_s *lower,
tccb_t callback, FAR void *arg)
{
FAR struct stm32_lowerhalf_s *priv =
(FAR struct stm32_lowerhalf_s *)lower;
irqstate_t flags = enter_critical_section();
/* Save the new callback */
priv->callback = callback;
priv->arg = arg;
if (callback != NULL && priv->started)
{
STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0);
STM32U5_TIM_ENABLEINT(priv->tim, 0);
}
else
{
STM32U5_TIM_DISABLEINT(priv->tim, 0);
STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0);
}
leave_critical_section(flags);
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_timer_initialize
*
* Description:
* Bind the configuration timer to a timer lower half instance and
* register the timer drivers at 'devpath'
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the
* form /dev/timer0
* timer - the timer's number.
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
int stm32_timer_initialize(FAR const char *devpath, int timer)
{
FAR struct stm32_lowerhalf_s *lower;
switch (timer)
{
#ifdef CONFIG_STM32U5_TIM1
case 1:
lower = &g_tim1_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM2
case 2:
lower = &g_tim2_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM3
case 3:
lower = &g_tim3_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM4
case 4:
lower = &g_tim4_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM5
case 5:
lower = &g_tim5_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM6
case 6:
lower = &g_tim6_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM7
case 7:
lower = &g_tim7_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM8
case 8:
lower = &g_tim8_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM15
case 15:
lower = &g_tim15_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM16
case 16:
lower = &g_tim16_lowerhalf;
break;
#endif
#ifdef CONFIG_STM32U5_TIM17
case 17:
lower = &g_tim17_lowerhalf;
break;
#endif
default:
return -ENODEV;
}
/* Initialize the elements of lower half state structure */
lower->started = false;
lower->callback = NULL;
lower->tim = stm32_tim_init(timer);
if (lower->tim == NULL)
{
return -EINVAL;
}
/* Register the timer driver as /dev/timerX. The returned value from
* timer_register is a handle that could be used with timer_unregister().
* REVISIT: The returned handle is discard here.
*/
FAR void *drvr = timer_register(devpath,
(FAR struct timer_lowerhalf_s *)lower);
if (drvr == NULL)
{
/* The actual cause of the failure may have been a failure to allocate
* perhaps a failure to register the timer driver (such as if the
* 'depath' were not unique). We know here but we return EEXIST to
* indicate the failure (implying the non-unique devpath).
*/
return -EEXIST;
}
return OK;
}
#endif /* CONFIG_TIMER */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "arm_internal.h"
#include "arm_arch.h"
#include "chip.h"
#include "stm32.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
* divided by 8. The SysTick can work either with this clock or with the
* Cortex clock (HCLK), configurable in the SysTick Control and Status
* register.
*/
/* Power up default is HCLK, not HCLK/8.
* And I don't know now to re-configure it yet
*/
#undef CONFIG_STM32U5_SYSTICK_HCLKd8
#ifdef CONFIG_STM32U5_SYSTICK_HCLKd8
# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
#else
# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
#endif
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
#if SYSTICK_RELOAD > 0x00ffffff
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: stm32_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
static int stm32_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
/* Set the SysTick interrupt to the default priority */
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Make sure that the SYSTICK clock source is set correctly */
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
regval = getreg32(NVIC_SYSTICK_CTRL);
#ifdef CONFIG_STM32U5_SYSTICK_HCLKd8
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
#else
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
#endif
putreg32(regval, NVIC_SYSTICK_CTRL);
#endif
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
/* Attach the timer interrupt vector */
(void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */
up_enable_irq(STM32_IRQ_SYSTICK);
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_STC_STM32U5_STM32_UART_H
#define __ARCH_ARM_STC_STM32U5_STM32_UART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/serial/serial.h>
#include "chip.h"
#if defined(CONFIG_STM32U5_STM32U585XX)
# include "hardware/stm32_uart.h"
#else
# error "Unsupported STM32U5 chip"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Make sure that we have not enabled more U[S]ARTs than are supported by the
* device.
*/
#if !defined(CONFIG_STM32U5_HAVE_UART5)
# undef CONFIG_STM32U5_UART5
#endif
#if !defined(CONFIG_STM32U5_HAVE_UART4)
# undef CONFIG_STM32U5_UART4
#endif
#if !defined(CONFIG_STM32U5_HAVE_USART3)
# undef CONFIG_STM32U5_USART3
#endif
#if !defined(CONFIG_STM32U5_HAVE_USART2)
# undef CONFIG_STM32U5_USART2
#endif
#if !defined(CONFIG_STM32U5_HAVE_USART1)
# undef CONFIG_STM32U5_USART1
#endif
#if !defined(CONFIG_STM32U5_HAVE_LPUART1)
# undef CONFIG_STM32U5_LPUART1
#endif
/* Sanity checks */
#if !defined(CONFIG_STM32U5_LPUART1)
# undef CONFIG_STM32U5_LPUART1_SERIALDRIVER
# undef CONFIG_STM32U5_LPUART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_USART1)
# undef CONFIG_STM32U5_USART1_SERIALDRIVER
# undef CONFIG_STM32U5_USART1_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_USART2)
# undef CONFIG_STM32U5_USART2_SERIALDRIVER
# undef CONFIG_STM32U5_USART2_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_USART3)
# undef CONFIG_STM32U5_USART3_SERIALDRIVER
# undef CONFIG_STM32U5_USART3_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_UART4)
# undef CONFIG_STM32U5_UART4_SERIALDRIVER
# undef CONFIG_STM32U5_UART4_1WIREDRIVER
#endif
#if !defined(CONFIG_STM32U5_UART5)
# undef CONFIG_STM32U5_UART5_SERIALDRIVER
# undef CONFIG_STM32U5_UART5_1WIREDRIVER
#endif
/* Is there a USART enabled? */
#if defined(CONFIG_STM32U5_LPUART1) || defined(CONFIG_STM32U5_USART1) || \
defined(CONFIG_STM32U5_USART2) || defined(CONFIG_STM32U5_USART3) || \
defined(CONFIG_STM32U5_UART4) || defined(CONFIG_STM32U5_UART5)
# define HAVE_UART 1
#endif
/* Is there a serial console? */
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 1
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART1_SERIALDRIVER)
# undef CONFIG_LPUART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 2
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART2_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 3
# define HAVE_CONSOLE 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART3_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 4
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART4_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 5
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART5_SERIALDRIVER)
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# define CONSOLE_UART 6
# define HAVE_CONSOLE 1
#else
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define CONSOLE_UART 0
# undef HAVE_CONSOLE
#endif
/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX
* configuration
*/
#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA)
# undef CONFIG_USART1_RXDMA
# undef CONFIG_USART2_RXDMA
# undef CONFIG_USART3_RXDMA
# undef CONFIG_UART4_RXDMA
# undef CONFIG_UART5_RXDMA
#endif
/* Disable the DMA configuration on all unused USARTs */
#ifndef CONFIG_STM32U5_LPUART1_SERIALDRIVER
# undef CONFIG_LPUART1_RXDMA
#endif
#ifndef CONFIG_STM32U5_USART1_SERIALDRIVER
# undef CONFIG_USART1_RXDMA
#endif
#ifndef CONFIG_STM32U5_USART2_SERIALDRIVER
# undef CONFIG_USART2_RXDMA
#endif
#ifndef CONFIG_STM32U5_USART3_SERIALDRIVER
# undef CONFIG_USART3_RXDMA
#endif
#ifndef CONFIG_STM32U5_UART4_SERIALDRIVER
# undef CONFIG_UART4_RXDMA
#endif
#ifndef CONFIG_STM32U5_UART5_SERIALDRIVER
# undef CONFIG_UART5_RXDMA
#endif
/* Is DMA available on any (enabled) USART? */
#undef SERIAL_HAVE_DMA
#if defined(CONFIG_LPUART1_RXDMA) || defined(CONFIG_USART1_RXDMA) || \
defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \
defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA)
# define SERIAL_HAVE_DMA 1
#endif
/* Is DMA used on the console UART? */
#undef SERIAL_HAVE_CONSOLE_DMA
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_LPUART1_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_USART3_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_UART4_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_UART5_RXDMA)
# define SERIAL_HAVE_CONSOLE_DMA 1
#endif
/* Is DMA used on all (enabled) USARTs */
#define SERIAL_HAVE_ONLY_DMA 1
#if defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#elif defined(CONFIG_STM32U5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA)
# undef SERIAL_HAVE_ONLY_DMA
#endif
/* Is RS-485 used? */
#if defined(CONFIG_LPUART1_RS485) || defined(CONFIG_USART1_RS485) || \
defined(CONFIG_USART2_RS485) || defined(CONFIG_USART3_RS485) || \
defined(CONFIG_UART4_RS485) || defined(CONFIG_UART5_RS485)
# define HAVE_RS485 1
#endif
#ifdef HAVE_RS485
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE)
#else
# define USART_CR1_USED_INTS (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE)
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_serial_dma_poll
*
* Description:
* Must be called periodically if any STM32 UART is configured for DMA.
* The DMA callback is triggered for each fifo size/2 bytes, but this can
* result in some bytes being transferred but not collected if the incoming
* data is not a whole multiple of half the FIFO size.
*
* May be safely called from either interrupt or thread context.
*
****************************************************************************/
#ifdef SERIAL_HAVE_DMA
void stm32_serial_dma_poll(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_STC_STM32U5_STM32_UART_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_uid.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/stm32_memorymap.h"
#include "stm32_uid.h"
#ifdef STM32U5_SYSMEM_UID
/****************************************************************************
* Public Functions
****************************************************************************/
void stm32_get_uniqueid(uint8_t uniqueid[12])
{
int i;
for (i = 0; i < 12; i++)
{
uniqueid[i] = *((uint8_t *)(STM32U5_SYSMEM_UID) + i);
}
}
#endif /* STM32U5_SYSMEM_UID */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_uid.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_UID_H
#define __ARCH_ARM_SRC_STM32U5_STM32_UID_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
void stm32_get_uniqueid(uint8_t uniqueid[12]);
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_UID_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_userspace.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <nuttx/userspace.h>
#include "stm32_mpuinit.h"
#include "stm32_userspace.h"
#ifdef CONFIG_BUILD_PROTECTED
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
****************************************************************************/
void stm32_userspace(void)
{
uint8_t *src;
uint8_t *dest;
uint8_t *end;
/* Clear all of user-space .bss */
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
dest = (uint8_t *)USERSPACE->us_bssstart;
end = (uint8_t *)USERSPACE->us_bssend;
while (dest != end)
{
*dest++ = 0;
}
/* Initialize all of user-space .data */
DEBUGASSERT(USERSPACE->us_datasource != 0 &&
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
USERSPACE->us_datastart <= USERSPACE->us_dataend);
src = (uint8_t *)USERSPACE->us_datasource;
dest = (uint8_t *)USERSPACE->us_datastart;
end = (uint8_t *)USERSPACE->us_dataend;
while (dest != end)
{
*dest++ = *src++;
}
/* Configure the MPU to permit user-space access to its FLASH and RAM */
stm32_mpuinitialize();
}
#endif /* CONFIG_BUILD_PROTECTED */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_userspace.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_USERSPACE_H
#define __ARCH_ARM_SRC_STM32U5_STM32_USERSPACE_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: stm32_userspace
*
* Description:
* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*
****************************************************************************/
#ifdef CONFIG_BUILD_PROTECTED
void stm32_userspace(void);
#endif
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_USERSPACE_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_waste.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "stm32_waste.h"
/****************************************************************************
* Private Data
****************************************************************************/
uint32_t idle_wastecounter = 0;
/****************************************************************************
* Public Functions
****************************************************************************/
void stm32_waste(void)
{
idle_wastecounter++;
}

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/****************************************************************************
* arch/arm/src/stm32u5/stm32_waste.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32U5_STM32_WASTE_H
#define __ARCH_ARM_SRC_STM32U5_STM32_WASTE_H
/* Waste CPU Time */
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/* Waste CPU Time
*
* stm32_waste() is the logic that will be executed when portions of kernel
* or user-app is polling some register or similar, waiting for desired
* status. This time is wasted away. This function offers a measure of badly
* written piece of software or some undesired behavior.
*
* At the same time this function adds to some IDLE time which portion
* cannot be used for other purposes (yet).
*/
void stm32_waste(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32U5_STM32_WASTE_H */

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/****************************************************************************
* arch/arm/src/stm32u5/stm32u585xx_rcc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <arch/stm32u5/chip.h>
#include <arch/board/board.h>
#include "stm32_pwr.h"
#include "stm32_flash.h"
#include "stm32_rcc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
* hosed anyway. Normally this is very fast, but I have seen at least one
* board that required this long, long timeout for the HSE to be ready.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* Same for HSI and MSI */
#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
#define MSIRDY_TIMEOUT HSERDY_TIMEOUT
/* HSE divisor to yield ~1MHz RTC clock */
#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
#if defined(CONFIG_STM32U5_HAVE_HSI48) && defined(STM32_USE_CLK48)
# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48
# define STM32_USE_HSI48
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: rcc_enableahb1
*
* Description:
* Enable selected AHB1 peripherals
*
****************************************************************************/
static inline void rcc_enableahb1(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB1ENR register to enabled the clocks
* of selected AHB1 peripherals.
*/
regval = getreg32(STM32_RCC_AHB1ENR);
#ifdef CONFIG_STM32U5_GPDMA1
regval |= RCC_AHB1ENR_GPDMA1EN;
#endif
#ifdef CONFIG_STM32U5_CORDIC
regval |= RCC_AHB1ENR_CORDIC;
#endif
#ifdef CONFIG_STM32U5_FMAC
regval |= RCC_AHB1ENR_FMACEN;
#endif
#ifdef CONFIG_STM32U5_MDF1
regval |= RCC_AHB1ENR_MDF1EN;
#endif
#ifdef CONFIG_STM32U5_FLASH
regval |= RCC_AHB1ENR_FLASHEN;
#endif
#ifdef CONFIG_STM32U5_CRC
regval |= RCC_AHB1ENR_CRCEN;
#endif
#ifdef CONFIG_STM32U5_TSC
regval |= RCC_AHB1ENR_TSCEN;
#endif
#ifdef CONFIG_STM32U5_RAMCFG
regval |= RCC_AHB1ENR_RAMCFGEN;
#endif
#ifdef CONFIG_STM32U5_DMA2D
regval |= RCC_AHB1ENR_DMA2DEN;
#endif
#ifdef CONFIG_STM32U5_GTZC1
regval |= RCC_AHB1ENR_GTZC1EN;
#endif
#ifdef CONFIG_STM32U5_BKPSRAM
regval |= RCC_AHB1ENR_BKPSRAMEN;
#endif
#ifdef CONFIG_STM32U5_DCACHE1
regval |= RCC_AHB1ENR_DCACHE1EN;
#endif
#ifdef CONFIG_STM32U5_SRAM1
regval |= RCC_AHB1ENR_SRAM1EN;
#endif
putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableahb2
*
* Description:
* Enable selected AHB2 peripherals
*
****************************************************************************/
static inline void rcc_enableahb2(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB2ENR1 and AHB2ENR2 registers to
* enable the clocks of selected AHB2 peripherals.
*/
regval = getreg32(STM32_RCC_AHB2ENR1);
#if STM32_NPORTS > 0
regval |= (RCC_AHB2ENR1_GPIOAEN
#if STM32_NPORTS > 1
| RCC_AHB2ENR1_GPIOBEN
#endif
#if STM32_NPORTS > 2
| RCC_AHB2ENR1_GPIOCEN
#endif
#if STM32_NPORTS > 3
| RCC_AHB2ENR1_GPIODEN
#endif
#if STM32_NPORTS > 4
| RCC_AHB2ENR1_GPIOEEN
#endif
#if STM32_NPORTS > 5
| RCC_AHB2ENR1_GPIOFEN
#endif
#if STM32_NPORTS > 6
| RCC_AHB2ENR1_GPIOGEN
#endif
#if STM32_NPORTS > 7
| RCC_AHB2ENR1_GPIOHEN
#endif
#if STM32_NPORTS > 8
| RCC_AHB2ENR1_GPIOIEN
#endif
);
#endif
#if defined(CONFIG_STM32U5_ADC1)
regval |= RCC_AHB2ENR1_ADC1EN;
#endif
#if defined(CONFIG_STM32U5_DCMI_PSSI)
regval |= RCC_AHB2ENR1_DCMI_PSSIEN;
#endif
#ifdef CONFIG_STM32U5_OTG
regval |= RCC_AHB2ENR1_OTGEN;
#endif
#ifdef CONFIG_STM32U5_AES
regval |= RCC_AHB2ENR1_AESEN;
#endif
#ifdef CONFIG_STM32U5_HASH
regval |= RCC_AHB2ENR1_HASHEN
#endif
#ifdef CONFIG_STM32U5_RNG
regval |= RCC_AHB2ENR1_RNGEN;
#endif
#ifdef CONFIG_STM32U5_PKA
regval |= RCC_AHB2ENR_PKAEN;
#endif
#ifdef CONFIG_STM32U5_SAES
regval |= RCC_AHB2ENR1_SAES;
#endif
#ifdef CONFIG_STM32U5_OCTOSPIM
regval |= RCC_AHB2ENR1_OCTOSPIM;
#endif
#ifdef CONFIG_STM32U5_OTFDEC1
regval |= RCC_AHB2ENR1_OTFDEC1;
#endif
#ifdef CONFIG_STM32U5_OTFDEC2
regval |= RCC_AHB2ENR1_OTFDEC2;
#endif
#ifdef CONFIG_STM32U5_SDMMC1EN
regval |= RCC_AHB2ENR1_SDMMC1EN;
#endif
#ifdef CONFIG_STM32U5_SDMMC2EN
regval |= RCC_AHB2ENR1_SDMMC2EN;
#endif
#ifdef CONFIG_STM32U5_SRAM2
regval |= RCC_AHB2ENR1_SRAM2EN;
#endif
#ifdef CONFIG_STM32U5_SRAM3
regval |= RCC_AHB2ENR1_SRAM3EN;
#endif
putreg32(regval, STM32_RCC_AHB2ENR1);
regval = getreg32(STM32_RCC_AHB2ENR2);
#ifdef CONFIG_STM32U5_FSMC
regval |= RCC_AHB2ENR2_FSMCEN;
#endif
#ifdef CONFIG_STM32U5_OCTOSPI1
regval |= RCC_AHB2ENR2_OCTOSPI1EN;
#endif
#ifdef CONFIG_STM32U5_OCTOSPI2
regval |= RCC_AHB2ENR2_OCTOSPI2EN;
#endif
putreg32(regval, STM32_RCC_AHB2ENR2);
}
/****************************************************************************
* Name: rcc_enableahb3
*
* Description:
* Enable selected AHB3 peripherals
*
****************************************************************************/
static inline void rcc_enableahb3(void)
{
uint32_t regval;
/* Set the appropriate bits in the AHB3ENR register to enabled the clocks
* of selected AHB3 peripherals.
*/
regval = getreg32(STM32_RCC_AHB3ENR);
#ifdef CONFIG_STM32U5_LPGPIO1
regval |= RCC_AHB3ENR_LPGPIO1EN;
#endif
#ifdef CONFIG_STM32U5_PWR
regval |= RCC_AHB3ENR_PWREN;
#endif
#ifdef CONFIG_STM32U5_ADC4
regval |= RCC_AHB3ENR_ADC4EN;
#endif
#ifdef CONFIG_STM32U5_DAC1
regval |= RCC_AHB3ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32U5_LPDMA1
regval |= RCC_AHB3ENR_LPDMA1EN;
#endif
#ifdef CONFIG_STM32U5_ADF1
regval |= RCC_AHB3ENR_ADF1EN;
#endif
#ifdef CONFIG_STM32U5_GTZC2
regval |= RCC_AHB3ENR_GTZC2EN;
#endif
#ifdef CONFIG_STM32U5_SRAM4
regval |= RCC_AHB3ENR_SRAM4EN;
#endif
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
}
/****************************************************************************
* Name: rcc_enableapb1
*
* Description:
* Enable selected APB1 peripherals
*
****************************************************************************/
static inline void rcc_enableapb1(void)
{
uint32_t regval;
/* Set the appropriate bits in the APB1ENR register to enabled the clocks
* of selected APB1 peripherals.
*/
regval = getreg32(STM32_RCC_APB1ENR1);
#ifdef CONFIG_STM32U5_TIM2
regval |= RCC_APB1ENR1_TIM2EN;
#endif
#ifdef CONFIG_STM32U5_TIM3
regval |= RCC_APB1ENR1_TIM3EN;
#endif
#ifdef CONFIG_STM32U5_TIM4
regval |= RCC_APB1ENR1_TIM4EN;
#endif
#ifdef CONFIG_STM32U5_TIM5
regval |= RCC_APB1ENR1_TIM5EN;
#endif
#ifdef CONFIG_STM32U5_TIM6
regval |= RCC_APB1ENR1_TIM6EN;
#endif
#ifdef CONFIG_STM32U5_TIM7
regval |= RCC_APB1ENR1_TIM7EN;
#endif
#ifdef CONFIG_STM32U5_WWDG
regval |= RCC_APB1ENR1_WWDGEN;
#endif
#ifdef CONFIG_STM32U5_SPI2
regval |= RCC_APB1ENR1_SPI2EN;
#endif
#ifdef CONFIG_STM32U5_USART2
regval |= RCC_APB1ENR1_USART2EN;
#endif
#ifdef CONFIG_STM32U5_USART3
regval |= RCC_APB1ENR1_USART3EN;
#endif
#ifdef CONFIG_STM32U5_UART4
regval |= RCC_APB1ENR1_UART4EN;
#endif
#ifdef CONFIG_STM32U5_UART5
regval |= RCC_APB1ENR1_UART5EN;
#endif
#ifdef CONFIG_STM32U5_I2C1
regval |= RCC_APB1ENR1_I2C1EN;
#endif
#ifdef CONFIG_STM32U5_I2C2
regval |= RCC_APB1ENR1_I2C2EN;
#endif
#ifdef CONFIG_STM32U5_CRS
regval |= RCC_APB1ENR1_CRSEN;
#endif
putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */
/* Second APB1 register */
regval = getreg32(STM32_RCC_APB1ENR2);
#ifdef CONFIG_STM32U5_I2C4
regval |= RCC_APB1ENR2_I2C4EN;
#endif
#ifdef CONFIG_STM32U5_LPTIM2
regval |= RCC_APB1ENR2_LPTIM2EN;
#endif
#ifdef CONFIG_STM32U5_FDCAN1
regval |= RCC_APB1ENR2_FDCAN1EN;
#endif
#ifdef CONFIG_STM32U5_UCPD1
regval |= RCC_APB1ENR2_UCPD1EN;
#endif
putreg32(regval, STM32_RCC_APB1ENR2);
}
/****************************************************************************
* Name: rcc_enableapb2
*
* Description:
* Enable selected APB2 peripherals
*
****************************************************************************/
static inline void rcc_enableapb2(void)
{
uint32_t regval;
/* Set the appropriate bits in the APB2ENR register to enabled the clocks
* of selected APB2 peripherals.
*/
regval = getreg32(STM32_RCC_APB2ENR);
#ifdef CONFIG_STM32U5_TIM1
regval |= RCC_APB2ENR_TIM1EN;
#endif
#ifdef CONFIG_STM32U5_SPI1
regval |= RCC_APB2ENR_SPI1EN;
#endif
#ifdef CONFIG_STM32U5_TIM8
regval |= RCC_APB2ENR_TIM8EN;
#endif
#ifdef CONFIG_STM32U5_USART1
regval |= RCC_APB2ENR_USART1EN;
#endif
#ifdef CONFIG_STM32U5_TIM15
regval |= RCC_APB2ENR_TIM15EN;
#endif
#ifdef CONFIG_STM32U5_TIM16
regval |= RCC_APB2ENR_TIM16EN;
#endif
#ifdef CONFIG_STM32U5_TIM17
regval |= RCC_APB2ENR_TIM17EN;
#endif
#ifdef CONFIG_STM32U5_SAI1
regval |= RCC_APB2ENR_SAI1EN;
#endif
#ifdef CONFIG_STM32U5_SAI2
regval |= RCC_APB2ENR_SAI2EN;
#endif
putreg32(regval, STM32_RCC_APB2ENR);
}
/****************************************************************************
* Name: rcc_enableapb3
*
* Description:
* Enable selected APB3 peripherals
*
****************************************************************************/
static inline void rcc_enableapb3(void)
{
uint32_t regval;
/* Set the appropriate bits in the APB3ENR register to enabled the clocks
* of selected APB3 peripherals.
*/
regval = getreg32(STM32_RCC_APB3ENR);
#ifdef CONFIG_STM32U5_SYSCFG
regval |= RCC_APB3ENR_SYSCFGEN;
#endif
#ifdef CONFIG_STM32U5_SPI3
regval |= RCC_APB3ENR_SPI3EN;
#endif
#ifdef CONFIG_STM32U5_LPUART1
regval |= RCC_APB3ENR_LPUART1EN;
#endif
#ifdef CONFIG_STM32U5_I2C3EN
regval |= RCC_APB3ENR_I2C3EN;
#endif
#ifdef CONFIG_STM32U5_LPTIM1
regval |= RCC_APB3ENR_LPTIM1EN;
#endif
#ifdef CONFIG_STM32U5_LPTIM3
regval |= RCC_APB3ENR_LPTIM3EN;
#endif
#ifdef CONFIG_STM32U5_LPTIM4
regval |= RCC_APB3ENR_LPTIM4EN;
#endif
#ifdef CONFIG_STM32U5_OPAMP
regval |= RCC_APB3ENR_OPAMPEN;
#endif
#ifdef CONFIG_STM32U5_COMP
regval |= RCC_APB3ENR_COMPEN;
#endif
#ifdef CONFIG_STM32U5_VREF
regval |= RCC_APB3ENR_VREFEN;
#endif
#ifdef CONFIG_STM32U5_RTCAPB
regval |= RCC_APB3ENR_RTCAPBEN;
#endif
putreg32(regval, STM32_RCC_APB3ENR);
}
/****************************************************************************
* Name: rcc_enableccip
*
* Description:
* Set peripherals independent clock configuration.
*
****************************************************************************/
static inline void rcc_enableccip(void)
{
/* Certain peripherals have no clock selected even when their enable bit is
* set. Set some defaults in the CCIPR register so those peripherals
* will at least have a clock.
*/
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_rcc_enableperipherals
****************************************************************************/
void stm32_rcc_enableperipherals(void)
{
rcc_enableccip();
rcc_enableahb1();
rcc_enableahb2();
rcc_enableahb3();
rcc_enableapb1();
rcc_enableapb2();
rcc_enableapb3();
}
/****************************************************************************
* Name: stm32_stdclockconfig
*
* Description:
* Called to change to new clock based on settings in board.h
*
* NOTE: This logic would need to be extended if you need to select low-
* power clocking modes!
****************************************************************************/
#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG
void stm32_stdclockconfig(void)
{
uint32_t regval;
volatile int32_t timeout;
/* Enable Internal Multi-Speed System (MSIS) and Kernel (MSIK) Clock */
#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16)
/* Enable Internal High-Speed Clock (HSI) */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_HSION; /* Enable HSI */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSI is ready (or until a timeout elapsed) */
for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSIRDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#endif
#if defined(STM32_BOARD_USEHSI)
/* Already set above */
#elif defined(STM32_BOARD_USEMSI)
/* Enable Internal Multi-Speed Clock (MSI) */
/* Wait until the MSI is either off or ready (or until a timeout elapsed) */
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
{
if ((regval = getreg32(STM32_RCC_CR)),
(regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
{
/* If so, then break-out with timeout > 0 */
break;
}
}
/* setting MSIRANGE */
regval = getreg32(STM32_RCC_CR);
regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */
putreg32(regval, STM32_RCC_CR);
/* Wait until the MSI is ready (or until a timeout elapsed) */
for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the MSIRDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#elif defined(STM32_BOARD_USEHSE)
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_HSEON; /* Enable HSE */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSE is ready (or until a timeout elapsed) */
for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSERDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#else
# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined
#endif
/* Check for a timeout. If this timeout occurs, then we are hosed. We
* have no real back-up plan, although the following logic makes it look
* as though we do.
*/
if (timeout > 0)
{
/* Select main regulator voltage range according to system clock
* frequency.
*/
/* Ensure Power control is enabled before modifying it. */
stm32_pwr_enableclk(true);
/* Select correct main regulator range */
regval = getreg32(STM32_PWR_CR1);
regval &= ~PWR_CR1_VOS_MASK;
if (STM32_SYSCLK_FREQUENCY > 80000000)
{
regval |= PWR_CR1_VOS_RANGE0;
}
else if (STM32_SYSCLK_FREQUENCY > 26000000)
{
regval |= PWR_CR1_VOS_RANGE1;
}
else
{
regval |= PWR_CR1_VOS_RANGE0;
}
putreg32(regval, STM32_PWR_CR1);
/* Wait for voltage regulator to stabilize */
while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF)
{
}
/* Set the HCLK source/divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_HPRE_MASK;
regval |= STM32_RCC_CFGR_HPRE;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK2 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE2_MASK;
regval |= STM32_RCC_CFGR_PPRE2;
putreg32(regval, STM32_RCC_CFGR);
/* Set the PCLK1 divider */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_PPRE1_MASK;
regval |= STM32_RCC_CFGR_PPRE1;
putreg32(regval, STM32_RCC_CFGR);
#ifdef CONFIG_STM32U5_RTC_HSECLOCK
/* Set the RTC clock divisor */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_RTCPRE_MASK;
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
putreg32(regval, STM32_RCC_CFGR);
#endif
/* Set the PLL source and main divider */
regval = getreg32(STM32_RCC_PLLCFG);
/* Configure Main PLL */
/* Set the PLL dividers and multipliers to configure the main PLL */
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |
STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ |
STM32_PLLCFG_PLLR);
#ifdef STM32_PLLCFG_PLLP_ENABLED
regval |= RCC_PLLCFG_PLLPEN;
#endif
#ifdef STM32_PLLCFG_PLLQ_ENABLED
regval |= RCC_PLLCFG_PLLQEN;
#endif
#ifdef STM32_PLLCFG_PLLR_ENABLED
regval |= RCC_PLLCFG_PLLREN;
#endif
/* XXX The choice of clock source to PLL (all three) is independent
* of the sys clock source choice, review the STM32_BOARD_USEHSI
* name; probably split it into two, one for PLL source and one
* for sys clock source.
*/
#ifdef STM32_BOARD_USEHSI
regval |= RCC_PLLCFG_PLLSRC_HSI16;
#elif defined(STM32_BOARD_USEMSI)
regval |= RCC_PLLCFG_PLLSRC_MSI;
#else /* if STM32_BOARD_USEHSE */
regval |= RCC_PLLCFG_PLLSRC_HSE;
#endif
putreg32(regval, STM32_RCC_PLLCFG);
/* Enable the main PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
{
}
#ifdef CONFIG_STM32U5_SAI1PLL
/* Configure SAI1 PLL */
regval = getreg32(STM32_RCC_PLLSAI1CFG);
/* Set the PLL dividers and multipliers to configure the SAI1 PLL */
regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP
| STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR);
#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED
regval |= RCC_PLLSAI1CFG_PLLPEN;
#endif
#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED
regval |= RCC_PLLSAI1CFG_PLLQEN;
#endif
#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED
regval |= RCC_PLLSAI1CFG_PLLREN;
#endif
putreg32(regval, STM32_RCC_PLLSAI1CFG);
/* Enable the SAI1 PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLSAI1ON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
{
}
#endif
#ifdef CONFIG_STM32U5_SAI2PLL
/* Configure SAI2 PLL */
regval = getreg32(STM32_RCC_PLLSAI2CFG);
/* Set the PLL dividers and multipliers to configure the SAI2 PLL */
regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP |
STM32_PLLSAI2CFG_PLLR);
#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED
regval |= RCC_PLLSAI2CFG_PLLPEN;
#endif
#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED
regval |= RCC_PLLSAI2CFG_PLLREN;
#endif
putreg32(regval, STM32_RCC_PLLSAI2CFG);
/* Enable the SAI2 PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLSAI2ON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLL is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0)
{
}
#endif
/* Enable FLASH 5 wait states */
regval = FLASH_ACR_LATENCY_5;
putreg32(regval, STM32_FLASH_ACR);
/* Select the main PLL as system clock source */
regval = getreg32(STM32_RCC_CFGR);
regval &= ~RCC_CFGR_SW_MASK;
regval |= RCC_CFGR_SW_PLL;
putreg32(regval, STM32_RCC_CFGR);
/* Wait until the PLL source is used as the system clock source */
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
{
}
#if defined(CONFIG_STM32U5_IWDG) || defined(CONFIG_STM32U5_RTC_LSICLOCK)
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();
#endif
#if defined(STM32_USE_LSE)
/* Low speed external clock source LSE
*
* TODO: There is another case where the LSE needs to
* be enabled: if the MCO1 pin selects LSE as source.
* XXX and other cases, like automatic trimming of MSI for USB use
*/
/* ensure Power control is enabled since it is indirectly required
* to alter the LSE parameters.
*/
stm32_pwr_enableclk(true);
/* XXX other LSE settings must be made before turning on the oscillator
* and we need to ensure it is first off before doing so.
*/
/* Turn on the LSE oscillator
* XXX this will almost surely get moved since we also want to use
* this for automatically trimming MSI, etc.
*/
stm32_rcc_enablelse();
# if defined(STM32_BOARD_USEMSI)
/* Now that LSE is up, auto trim the MSI */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_MSIPLLEN;
putreg32(regval, STM32_RCC_CR);
# endif
#endif /* STM32_USE_LSE */
}
}
#endif